KR20090022417A - Semiconductor element and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a semiconductor device and a method of manufacturing the same. The technical problem to be solved is to form a gate oxide film having a predetermined thickness on the drain / source to prevent the leakage current is generated, the gate oxide film on the drain / source This is to prevent phenomena such as ion doping only on the surface of the drain / source region generated when formed thick.

To this end, the present invention is formed between the semiconductor substrate including the device isolation film, the device isolation film, the drain / source formed at a predetermined distance apart from each other, the drain / source and the device isolation film and formed on the upper surface of the semiconductor substrate, drain / source and A gate oxide film thinner than the thickness formed on the upper surface of the semiconductor substrate; a gate formed on the first central upper surface of the first upper surface of the first oxide surface formed on the upper surface of the semiconductor substrate; The first oxide film having a predetermined thickness on the first edge upper surface, which is a region other than the gate, of the first upper surface, which is the upper surface of the oxide film, and the upper surface of the first oxide film and the side surface of the first oxide film formed on the first edge of the gate oxide film. The second acid formed on the upper surface of the nitride film formed on the upper surface of the nitride film and the first oxide film formed on a predetermined thickness and on the side surface of the nitride film Disclosed are a semiconductor device including a film and a method of manufacturing the same.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND THE MANUFACTURING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to form a gate oxide film having a predetermined thickness on the drain / source of a transistor operating at a high voltage, thereby preventing leakage current from occurring and The present invention relates to a semiconductor device and a method of manufacturing the same, which can prevent a phenomenon such as ion doping only on the surface of the drain / source region generated when the gate oxide film is formed thick.

In general, power devices such as liquid crystal display device drive LDIs of a liquid crystal display are transistors that operate low voltage (LV) and medium voltage (MV) to drive related integrated circuits. In addition, all transistors capable of operating a high voltage (HV) for driving a liquid crystal display are required.

In the case of a source driver IC such as a liquid crystal display, a source driver IC requires a dual transistor forming process operating at a high voltage (HV) and a low voltage (LV), and a gate driver. In the case of a gate driver IC, a triple transistor formation process that operates at a high voltage HV, a medium voltage MV, and a low voltage LV is required.

When forming transistors that operate at respective voltages, the gate oxide film becomes thicker from low voltage LV to high voltage HV. At this time, a leakage current may be generated between the oxide layer and the drain / source of the transistor, and the leakage current is generated more in a high voltage (HV) transistor operated by applying a high voltage. In order to prevent such leakage current generation, when a transistor operating at a high voltage HV is fabricated, a method of forming a gate oxide film on the region where the drain / source of the transistor is to be formed is used. However, when impurities are implanted into the drain / source region that proceeds after the gate oxide film is formed, the gate oxide film prevents ions from diffusing after ion implantation, resulting in a defect in which ions are doped only on the drain / source region surface.

SUMMARY OF THE INVENTION The present invention has been made to overcome the above-mentioned problems, and an object of the present invention is to form a gate oxide film having a predetermined thickness on the drain / source of a transistor operating at a high voltage, thereby preventing leakage current from occurring, and The present invention provides a semiconductor device capable of preventing a phenomenon such as ion doping only on a surface of a drain / source region generated when a thick gate oxide film is formed on a source, and a manufacturing method thereof.

In order to achieve the above object, a semiconductor device and a method of manufacturing the same according to the present invention include a semiconductor substrate including an isolation layer, a drain / source formed between the isolation layer and spaced apart from each other by a predetermined distance, and the drain / source And a gate oxide layer formed on the device isolation layer and the semiconductor substrate, and having a thickness formed on the drain / source and the device isolation layer to be thinner than a thickness formed on the semiconductor substrate, and the gate oxide layer formed on the semiconductor substrate. A gate formed on a first central upper surface of the first upper surface, which is an upper surface, and a first thickness formed on an upper surface of the first edge, which is an area other than the gate formed of a side surface of the gate and a first upper surface, which is an upper surface of the gate oxide film; An oxide film and the first oxide film formed on an upper surface of the first edge of the gate oxide film. The surface and a second oxide film formed on the upper surface and the side surface of the nitride film of the nitride film formed on a top surface of the first nitride film and the first oxide film formed to a predetermined thickness on the side surface of the first oxide film may be formed, including.

The thickness of the gate oxide film formed in the region corresponding to the drain / source may be 100 kPa to 200 kPa.

A substrate preparation step of preparing a semiconductor substrate including an isolation layer, a gate oxide layer forming step of forming a gate oxide layer with a predetermined thickness on the isolation layer and the semiconductor substrate, and forming a gate in the center of the gate oxide layer Forming a first oxide layer having a predetermined thickness on the gate and the gate oxide layer, and forming a nitride layer having a predetermined thickness on the first oxide layer. A forming step, a second oxide layer forming step of forming a second oxide film layer having a predetermined thickness on the nitride layer, a planarizing step of planarizing the second oxide layer so that the gate is exposed to the outside, and a planarization step The second oxide layer, the nitride layer, and the first oxide layer formed in the region of the substrate may be removed, and the gate oxide layer may be An etching step of etching a region other than the portion of the second oxide film, the nitride film, and the first oxide film remaining with only a predetermined thickness, and an ion implantation step of forming a drain / source region by ion implanting impurities into the semiconductor substrate. can do.

In the etching step, etching may be performed until the thickness of regions other than the portion where the second oxide film, the nitride film, and the first oxide film remain in the gate oxide film layer is 100 kPa to 200 kPa.

As described above, the semiconductor device and the method of manufacturing the same according to the present invention form a gate oxide film having a predetermined thickness on the drain / source of a transistor operating at a high voltage, thereby preventing leakage current from occurring, and It is possible to prevent a phenomenon such as ion doping only on the surface of the drain / source region generated when the gate oxide film is formed thick.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily implement the present invention.

Referring to FIG. 1, there is shown a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

As illustrated in FIG. 1, the semiconductor device 1000 may include a low voltage transistor 100, a medium voltage transistor 200, and a high voltage transistor 300.

The low voltage transistor 100, the medium voltage transistor 200, and the high voltage transistor 300 may include the semiconductor substrate 110, the gate oxide layers 120, 220, and 320, the gates 130, 230, and 330, and the first oxide layer 140. , 240, 340, nitride films 150, 250, and 350, second oxide films 160, 260, and 360, and drain / sources 170, 270, and 370.

The low voltage transistor 100, the medium voltage transistor 200, and the high voltage transistor 300 have the same structure except for the gate oxide layers 120, 220, and 230, and the low voltage transistor 100 and the medium voltage transistor 200. The gate oxide layers 120 and 220 are formed on the semiconductor substrate 110 in the drain / source region, and only the thicknesses of the gate oxide layers 120 and 220 are different depending on the voltage applied to the transistor. Hereinafter, the high voltage transistor 300 will be described.

The semiconductor substrate 110 may include an N-type or P-type single crystal semiconductor substrate 110 and an isolation layer 111 for separating each semiconductor device from the semiconductor substrate 110. The device isolation layer 111 may be formed using any one selected from thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like. However, the method is not limited thereto.

The gate oxide layer 320 is formed to cover the drain / source 370, the device isolation layer 111, and the upper surface of the semiconductor substrate 110. The gate oxide film 320 formed on the upper surface of the semiconductor substrate 110 is formed to be thicker than the thickness of the gate oxide film 320 formed on the drain / source 370 and the device isolation layer 111. Steps are generated on the top surface of the oxide film 320. An upper surface of the gate oxide film 320 formed in a region corresponding to the semiconductor substrate 110 is formed of a first central upper surface 321a and a first oxide film 340 having a gate 330 formed as a first upper surface 321. It includes a first edge upper surface 321b. The upper surface of the gate oxide film 320 formed in the region corresponding to the drain / source 370 and the device isolation layer 111 is the second upper surface 322, and the thickness of the gate oxide film 320 in this region is 100 to 200 Å. Becomes When the gate oxide layer 320 is formed to be less than 100 mA, the reliability of the semiconductor device may be reduced due to leakage current generated when a high voltage is applied. When the gate oxide layer 320 is formed to exceed 200 mA, impurities are implanted into the drain / source region. Thereafter, the ions do not diffuse, resulting in a defect that is ion doped only on the drain / source region surface.

The gate 330 is formed to cover the first central upper surface 321a of the gate oxide layer 320, and the first oxide layer 340 is formed on the side surface 331 of the gate 330. The gate 330 may be formed of any one selected from doped polysilicon, MoW, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy and Al alloy, but the material is not limited thereto.

The first oxide film 340 is formed to a predetermined thickness on the side surface 331 of the gate 330 and the first edge upper surface 321b of the gate oxide film 320. In this case, a bent portion is formed at the intersection of the side surface 331 of the gate 330 and the first edge upper surface 321b of the gate oxide film 320. The first oxide layer 340 may be made of any one material selected from silicon dioxide (SiO ₂ ), alumina (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), and zirconia (ZrO ₂ ), but the material It is not intended to limit.

The nitride film 350 is formed to have a predetermined thickness on the upper surface 342 connected to the side surface 341 of the first oxide film 340 and the bent portion. In this case, the nitride film 350 has a bent portion formed at the intersection of the side surface 341 and the upper surface 342 of the first oxide film 340. The nitride film 350 may be formed of nitride (SiNx), but the material is not limited thereto.

The second oxide film 360 is formed to cover all of the side surface 351 of the nitride film 350 and the upper surface 352 connected through the bent portion, and surfaces other than the contact with the nitride film 350 are curved. . The first oxide layer 340 may be made of any one material selected from silicon dioxide (SiO ₂ ), alumina (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), and zirconia (ZrO ₂ ), but the material It is not intended to limit.

The drain / source 370 is in the region corresponding to the second upper surface 322 of the gate oxide layer 320, and the gate 330 inside the semiconductor substrate 110 in which the device isolation layer 111 is not formed. It is formed by ion implantation of impurities using as a mask.

In the following description, a manufacturing method for obtaining a high voltage transistor among the semiconductor elements described above will be described.

Referring to FIG. 2, the method of manufacturing the high voltage transistor 300 of the semiconductor device of FIG. 1 may include a substrate preparation step S1, a gate oxide film forming step S2, a gate forming step S3, and a first oxide film forming step ( S4), a nitride layer forming step S5, a second oxide layer forming step S6, a planarization step S7, an etching step S8, and an ion implantation step S9.

3A to 3I, cross-sectional views illustrating a method of manufacturing the semiconductor device shown in FIG. 2 are shown.

As shown in FIG. 3A, in the substrate preparation step (S1), an element isolation layer 111 for separating each semiconductor element is formed on an N-type or P-type single crystal semiconductor substrate 110 to prepare a substrate. The device isolation layer 112 may be formed using any one selected from thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like. However, the method is not limited thereto.

As shown in FIG. 3B, in the gate oxide layer forming step S2, the gate oxide layer 320a is deposited to cover the semiconductor substrate 110 and the device isolation layer 111. The gate oxide layer 320a may be made of any one material selected from silicon dioxide (SiO ₂ ), alumina (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), and zirconia (ZrO ₂ ). It is not limited. The gate oxide layer 320a may be any one selected from a thermal oxidation method, a chemical vapor deposition method, an electrochemical oxidation method, and an equivalent method thereof. It may be formed, and preferably, a wet process using TEOS (Tetra Ethyl Ortho Silicate) gas may be formed, but the method is not limited thereto.

As illustrated in FIG. 3C, in the gate forming step S3, a gate 330 forming material is deposited on the gate oxide layer 320a and patterned to form the gate 330. The gate 330 may be any one selected from doped polysilicon, MoW, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy and Al alloy, but is not limited thereto.

As shown in FIG. 3D, the first oxide layer 340a is deposited to cover the gate oxide layer 320a and the gate 330 in the first oxide layer forming step S4. The first oxide layer 340a may be made of any one material selected from silicon dioxide (SiO ₂ ), alumina (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), and zirconia (ZrO ₂ ). It does not limit the material. The first oxide layer 340a may be any one selected from a thermal oxidation method, a chemical vapor deposition method, an electrochemical oxidation method, and an equivalent method thereof. It may be formed by using, and preferably, a wet process using TEOS (Tetra Ethyl Ortho Silicate) gas may be formed, but the method is not limited thereto.

As illustrated in FIG. 3E, the nitride layer 350a is deposited to cover the first oxide layer 340a in the forming of the nitride layer. The nitride layer 350a may be formed of nitride (SiNx), but the material is not limited thereto. The nitride layer 350a may be formed using any one selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like, but the method is limited thereto. It is not.

As shown in FIG. 3F, in the second oxide film forming step S6, the second oxide film layer 360a is deposited to cover the nitride film layer 350a and formed thicker than the thickness of the gate 330. The second oxide layer 360a may be made of any one material selected from silicon dioxide (SiO ₂ ), alumina (Al ₂ O ₃ ), hafnium dioxide (HfO ₂ ), and zirconia (ZrO ₂ ). It does not limit the material. The second oxide layer 360a may include any one selected from a thermal oxidation method, a chemical vapor deposition method, an electrochemical oxidation method, and an equivalent method thereof. It may be formed by using, and preferably, a wet process using TEOS (Tetra Ethyl Ortho Silicate) gas may be formed, but the method is not limited thereto.

As shown in FIG. 3G, the planarization operation is performed until the gate 330 is exposed to the surface on which the second oxide layer 360a is formed. The planarization may be formed by any one method selected from chemical mechanical polishing (CMP) and equivalent methods, and the method is not limited thereto.

As shown in FIG. 3H, in the etching step S8, the first oxide layer 340a except for the first oxide layer 340, the nitride layer 350, and the second oxide layer 360 formed on the side surface of the gate 330. ), The nitride film layer 350a and the second oxide film layer 360a are etched. In this case, the second oxide layer 360a is anisotropically etched on the side surface of the gate 330 to form the second oxide layer 360, which is a sidewall spacer of the gate 330. The gate oxide film 320 is etched so that the gate oxide film 320a in a region other than the region where the gate 330, the first oxide film 340, the nitride film 350, and the second oxide film 360 is formed is 100 kPa to 200 kPa. To form. When the thickness of the gate oxide layer 320 is less than 100 μs, the reliability of the semiconductor device is changed due to the leakage current generated when the high voltage is applied. When the gate oxide layer 320 exceeds 200 μs, impurities are implanted into the drain / source region. The ion is not diffused, and a defect of ion doping only on the drain / source region surface occurs.

As shown in FIG. 3I, in the ion implantation step S9, the source / inside of the semiconductor substrate is formed among the regions corresponding to the device isolation layer 111 and the region where the gate 330 is formed using the gate 330 as a mask. To form the drain, dopants are ion implanted with p-type or n-type impurities. P-type impurities are doped into the source / drain to form a PMOS transistor when holes flow in the formation of the channel region, and electrons flow when the channel region is formed by doping the n-type impurities to form an NMOS transistor.

What has been described above is only one embodiment for carrying out the semiconductor device and the manufacturing method thereof according to the present invention, the present invention is not limited to the above embodiment, as claimed in the following claims Without departing from the gist of the present invention, those skilled in the art to which the present invention pertains to the technical spirit of the present invention to the extent that various modifications can be made.

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a method of manufacturing a transistor operating at a high voltage among the semiconductor devices of FIG. 1.

3A to 3I are cross-sectional views illustrating a method of manufacturing the semiconductor device illustrated in FIG. 2.

<Description of Symbols for Main Parts of Drawings>

1000; Semiconductor device

100; Low voltage transistor 200; Medium voltage transistor

300; High voltage transistor 110; Semiconductor substrate

111; An isolation layer 320; Gate oxide

330; Gate 340; First oxide film

350; Insulating film 360; Second oxide film

370; Drain / Source

Claims (4)

A semiconductor substrate including an isolation layer; A drain / source formed between the device isolation layers and formed to be spaced apart from each other by a predetermined distance; A gate oxide layer formed on the drain / source, the device isolation layer, and the semiconductor substrate, and having a thickness formed on the drain / source and the device isolation layer to be thinner than a thickness formed on the semiconductor substrate; A gate formed on the first central upper surface of the first upper surface of the gate oxide layer formed on the semiconductor substrate; A first oxide film having a predetermined thickness on a first edge upper surface, which is a region other than the gate, among the side surfaces of the gate and the first upper surface which is an upper surface of the gate oxide film; A nitride film having a predetermined thickness on an upper surface of the first oxide film and a side surface of the first oxide film formed on the first edge of the gate oxide film; And And a second oxide film formed on an upper surface of the nitride film and a side surface of the nitride film formed on an upper surface of the first oxide film. The method of claim 1, The thickness of the gate oxide film formed in the region corresponding to the drain / source is a semiconductor device, characterized in that 100 ~ 200Å. A substrate preparation step of preparing a semiconductor substrate including an isolation layer; Forming a gate oxide layer on the device isolation layer and the semiconductor substrate at a predetermined thickness; A gate forming step of forming a gate in the center of the gate oxide film; Forming a first oxide layer having a predetermined thickness on the gate and the gate oxide layer; A nitride film layer forming step of forming a nitride film layer having a predetermined thickness on the first oxide film layer; Forming a second oxide layer having a predetermined thickness on the nitride layer; Planarizing the second oxide layer to expose the gate to the outside; All of the second oxide layer, the nitride layer, and the first oxide layer formed in a region other than the side of the gate is removed, and the second oxide layer, the nitride layer, and the first oxide layer remain in the gate oxide layer. Etching an area of the layer leaving only a predetermined thickness; And And implanting an ion into the semiconductor substrate to form a drain / source region. The method of claim 3, wherein in the etching step And etching until the thickness of regions other than the portion where the second oxide film, the nitride film, and the first oxide film remain in the gate oxide film layer is 100 kPa to 200 kPa.

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