KR20090029572A - Array substrate for liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device and a method for manufacturing the same, and more particularly, to an array substrate for a high aperture liquid crystal display device using an organic insulating material as a protective film and a method for manufacturing the same.

To this end, in the present invention, a first mask process step of forming a semiconductor layer, source and drain electrodes and data wirings on a substrate; A second mask process step of forming a passivation layer having a first hole and a second hole exposing a part of each of the drain electrodes and selected from a group of organic insulating materials;

Forming a gate insulating film on the passivation layer including the first and second holes with one of a group of inorganic insulating materials, forming a gate wiring and a gate electrode on the gate insulating layer, and performing a drain And a fourth mask process step of forming a drain contact hole by removing the gate insulating layer corresponding to a portion of the electrode, and a fifth mask process step of forming a pixel electrode in contact with the drain electrode.

The above-described configuration has an advantage of providing a pixel design having excellent film quality between array elements without forming an additional insulating film.

Description

An array substrate for a liquid crystal display device and a method of manufacturing the same {An Array Substrate of Liquid Crystal Display Device and the method for fabricating

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device and a method for manufacturing the same, and more particularly, to an array substrate for a high aperture liquid crystal display device using an organic insulating material as a protective film and a method for manufacturing the same.

In general, the liquid crystal display, which is one of the flat panel display devices, has a better visibility than the cathode ray tube (CRT) and is smaller than the cathode ray tube of the screen size having the same average power consumption. Along with the devices and the field emission display devices, they are recently attracting attention as the next generation display devices for mobile phones, computer monitors, and televisions.

The driving principle of the liquid crystal display device is to use optical anisotropy and polarization property of the liquid crystal. The liquid crystal has a long and thin structure, and thus the liquid crystal has directivity in the arrangement of the molecules. can do.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Hereinafter, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1 is a plan view illustrating a unit pixel of a conventional array substrate for a liquid crystal display device, and FIG. 2 is a cross-sectional view taken along a line II-II of FIG. 1, and a state in which an array substrate and a color filter substrate are opposed to each other. It is shown.

As shown in FIGS. 1 and 2, the color filter substrate 5 and the array substrate 10, which are divided into the display area AA and the non-display area NAA, are opposed to each other. The liquid crystal layer 15 is interposed between the gaps 10). In this case, the color filter substrate 5 includes the color filter substrate 5, the array substrate 10, and the liquid crystal layer 15.

A black matrix 12 is provided on the lower surface of the transparent substrate 1 of the color filter substrate 5 to shield light incident to the non-display area NAA, and a color is formed below the black matrix 12. The color filter layer 14 including the red, green, and blue sub color filters 14a, 14b, and 14c, and the common electrode 16 are sequentially disposed below the color filter layer 14.

In this case, an overcoat layer (not shown) may be further configured for the purpose of planarization between the color filter layer 14 and the common electrode 16.

The gate wiring 20 and the gate electrode 25 extending from the gate wiring 20 in one direction are formed on an upper surface of the transparent substrate 2 of the array substrate 10. The gate insulating layer 45 is formed on the entire upper surface of the gate line 20 and the gate electrode 25 as one selected from the group of inorganic insulating materials.

On the gate insulating layer 45, an active layer 40 made of pure amorphous silicon (a-Si: H) and an ohmic contact layer 41 made of amorphous silicon (n + a-Si: H) containing impurities are sequentially stacked. Is formed. In this case, the active layer 40 and the ohmic contact layer 41 may be referred to as a semiconductor layer 42.

On the semiconductor layer 42, a data line 30 perpendicularly intersecting with the gate line 20 to define a pixel region P, a source electrode 32 extending from the data line 30, and the source electrode A drain electrode 34 spaced apart from the 32 is formed. In this case, the gate electrode 25, the gate insulating layer 45, the semiconductor layer 42, and the source and drain electrodes 32 and 34 form a thin film transistor T serving as a switching function of the liquid crystal display.

Here, the ohmic contact layer 41 corresponding to the spaced apart portions of the source and drain electrodes 32 and 34 is separated and formed on both sides, and the lower portion of the active layer 40 is overetched to form a channel (ch). To be used.

The passivation layer 55 is formed on the entire upper surface of the thin film transistor T. In this case, the passivation layer 55 is formed of one selected from the group of organic insulating materials including photoacryl or benzocyclobutene (BCB) having a low dielectric constant.

The pixel electrode 70 in contact with the drain electrode 34 is configured to correspond to the pixel region P on the protective film 55 including the drain contact hole CH1 exposing a part of the drain electrode 34. do.

In general, the passivation layer 55 is formed of one selected from the group of inorganic insulation materials such as silicon nitride (SiNx) and silicon oxide (SiO ₂ ) as an excellent film quality. However, the inorganic insulation material may be used as the protection film 55. In this case, the parasitic capacitance between the data line 30 and the pixel electrode 70 is severely generated due to the high dielectric constant.

The distortion of the data signal due to the parasitic capacitance may cause a poor image quality such as cross-talk. Therefore, the data line 30 and the pixel electrode 70 have to be configured to be spaced apart at regular intervals.

In addition, the black matrix 12 is provided with sufficient margin to shield the pixel electrode 70 corresponding to both sides of the data line 30 and the data line 30 in consideration of the bonding error between the two substrates 5 and 10. It was inevitable to lower the aperture ratio due to the design of.

In order to solve this problem, the parasitic between the pixel electrode 70 and the data line 30 is formed by forming the above-described passivation layer 55 made of an organic insulating material having a low dielectric constant but not having better film quality than the inorganic insulating material. The method of greatly reducing capacitance is mainly used.

In this method, even when the pixel electrode 70 and the data line 30 are designed to overlap each other by the passivation layer 55 having a small dielectric constant, the data signal is distorted due to parasitic capacitance between the pixel electrode 70 and the data line 30. As a phenomenon that does not occur, there is an advantage that can implement a high opening rate.

However, the passivation layer 55 formed of the above-described organic insulating material may be easily exposed to contaminants such as dust and foreign matters because the film quality is not excellent. Therefore, the channel ch portion covered by the passivation layer 55 may cause a problem that an operating characteristic of the thin film transistor T is reduced due to the off current.

In addition, the pixel electrode 70 formed of a transparent conductive metal such as indium tin oxide (ITO) or indium zinc oxide (IZO) has a poor interface property with the passivation layer 55 and thus cannot guarantee reliability. .

As an alternative to this, a method of forming the first and second insulating films using inorganic insulating materials having excellent film quality characteristics on the upper side and the lower side of the passivation layer 55 is used.

This will be described in detail with reference to the accompanying drawings.

FIG. 3 is a cross-sectional view taken along the line II-II of FIG. 1. In detail, FIG. 1 is a view showing a state in which the first and second insulating films are formed on the upper side and the lower side of the protective film made of the organic insulating material in the configuration of FIG. 1. Duplicate explanations should be avoided.

As shown, the semiconductor layer 42 including the gate wiring on the substrate 2 (20 in FIG. 1) and the gate insulating film 45 and the active and ohmic contact layers 40 and 41 on the gate electrode 25. This is located in turn.

The data line 30 and the source and drain electrodes 32 and 34 are positioned on the semiconductor layer 42. At this time, the ohmic contact layer 41 corresponding to the spaced apart portions of the source and drain electrodes 32 and 34 are separated and formed on both sides, and the lower portion of the active layer 40 is overetched to form a channel (ch). To be used.

The first insulating layer 54 is formed on the data line 30 and the source and drain electrodes 32 and 34 as one selected from a group of inorganic insulating materials. In this case, the first insulating layer 54 serves to prevent an operation characteristic of the thin film transistor T from being deteriorated due to the off current of the channel ch.

In addition, the passivation layer 55 is formed on the substrate 10 on which the first insulating layer 54 is formed by using one of organic insulating material groups, and the second insulating layer 56 is formed on the passivation layer 55 by one of inorganic insulating materials. This is formed by lamination in turn.

The drain contact hole CH1 exposing a part of the drain electrode 34 is removed by sequentially removing the second insulating film 56, the protective film 55, and the first insulating film 54 corresponding to a part of the drain electrode 34. Is formed.

The pixel electrode 70, which is in contact with the drain electrode 34 through the drain contact hole CH1, extends to overlap the data line 30 corresponding to the pixel area P. In this case, the second insulating layer 56 is configured to be interposed between the pixel electrode 70 and the passivation layer 55 to improve the interface characteristics of the pixel electrode 70.

The above-described configuration has the advantage of preventing the malfunction of the thin film transistor T due to the off current in the channel ch part, and improving the interface characteristics of the pixel electrode 70. It is a situation where the process limit which results from patterning the 1st insulating film 54, the protective film 55, and the 2nd insulating film 56 collectively is encountered.

In detail, the passivation layer 55 interposed between the first and second insulating layers 54 and 56 may be a dispenser or spin coater for an organic insulating material including photoacryl or benzocyclobutene. ) Is uniformly applied onto the substrate 2 and formed.

However, due to the characteristics of the above-described coating process, since the thickness of the protective film 55 is close to 3 μm, the second insulating film 56, the protective film 55, and the first insulating film 54 are collectively patterned by applying dry etching. It's hard to do.

For this reason, an increase in the number of mask processes due to an additional photolithography process for removing the first insulating film 54 under the protective film 55 not only increases the initial investment cost and manufacturing cost of the equipment, but also the first and second insulating films. There is a problem of increasing the additional process and production costs associated with forming (54, 56).

Disclosure of Invention The present invention has been made to solve the above-described problem, and an object thereof is to provide an array substrate for a high aperture liquid crystal display device having excellent film quality between array elements without forming an additional insulating film.

According to an embodiment of the present invention, an array substrate for a liquid crystal display device includes a semiconductor layer formed on a substrate, a data line formed in one direction on the semiconductor layer, and extended from the data line and in contact with the semiconductor layer. A portion of the semiconductor layer and the drain electrode exposed between the source and drain electrodes, the drain electrode spaced apart from the source electrode, the source and drain electrodes and the data wiring, and spaced apart from the source and drain electrodes. A protective film including first and second holes respectively exposed;

A gate insulating film covering the first and second holes and including a drain contact hole exposing a portion of the drain electrode, a gate wiring on the gate insulating film, and extending from the gate wiring and having the gate insulating film interposed therebetween And a gate electrode overlapping the semiconductor layer, and a pixel electrode contacting the drain electrode through the drain contact hole.

In this case, the semiconductor layer includes an active layer made of pure amorphous silicon and an ohmic contact layer made of amorphous silicon including impurities, and separately separating the ohmic contact layer positioned between the source and drain electrodes. The active layer corresponding to the ohmic contact layer separated on both sides is overetched to configure this portion as a channel.

The channel is covered by the gate insulating layer, and the gate insulating layer is positioned between the pixel electrode and the passivation layer.

The gate insulating layer may include one selected from the group of inorganic insulating materials including silicon oxide and silicon nitride, and the protective layer may include one selected from the group of organic insulating materials including photoacryl and benzocyclobutene.

One end of the data line includes a data pad, a third hole in which a portion of the passivation layer covering the data pad is removed, and a data pad contact hole in which a portion of the gate insulating layer covering the third hole is removed. It further comprises a data pad electrode in contact with the pad.

One end of the gate line further includes a gate pad and a gate pad electrode in contact with the gate pad, wherein the semiconductor layer is made of polycrystalline silicon.

According to an exemplary embodiment of the present invention, an array substrate for a liquid crystal display device includes forming a semiconductor layer, a source, a drain electrode, and a data line on a substrate, and including the semiconductor layer, the source, the drain electrode, and a data line. Forming a passivation layer on the substrate having a first hole and a second hole exposing a part of each of the semiconductor layer and the drain electrode, and selecting one of a group of organic insulating materials;

Forming a gate insulating film on the passivation layer including the first and second holes with a selected one of an inorganic insulating material group, forming a gate wiring and a gate electrode on the gate insulating film, and a part of the drain electrode Forming a drain contact hole exposing the drain contact hole and forming a pixel electrode in contact with the drain electrode.

In this case, the semiconductor layer includes an active layer made of pure amorphous silicon and an ohmic contact layer made of amorphous silicon including impurities, and separately separating the ohmic contact layer positioned between the source and drain electrodes. The active layer corresponding to the ohmic contact layers separated on both sides is overetched to form this portion as a channel.

The channel is covered by the gate insulating layer, and the gate insulating layer is positioned between the pixel electrode and the passivation layer.

The gate insulating layer may be formed of one selected from the group of inorganic insulating materials including silicon oxide and silicon nitride, and the protective layer may be formed of one selected from the group of organic insulating materials including photoacryl and benzocyclobutene.

One end of the data line includes a data pad, a third hole in which a portion of the passivation layer covering the data pad is removed, and a data pad contact hole in which a portion of the gate insulating layer covering the third hole is removed. It further comprises a data pad electrode in contact with the pad.

One end of the gate line further includes a gate pad and a gate pad electrode in contact with the gate pad, wherein the semiconductor layer is formed of polycrystalline silicon.

In the present invention, first, it is possible to prevent the malfunction of the thin film transistor due to the off current through protecting the channel with an inorganic insulating material having excellent film quality characteristics.

Second, an interfacial characteristic of the pixel electrode can be improved by interposing a gate insulating film between the pixel electrode and the passivation layer.

Third, there is no need to configure an additional insulating film can reduce the production cost.

Fourth, the mask process can be reduced.

--- Example ---

The present invention is to provide a pixel design having excellent film quality between array elements in an array substrate for a high aperture liquid crystal display device using an organic insulating material without forming an additional insulating film.

In addition, the array substrate for high-aperture liquid crystal display device is produced by a five mask process.

Hereinafter, a liquid crystal display according to the present invention will be described with reference to the accompanying drawings.

4 is a plan view illustrating unit pixels of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4.

4 and 5, the switching region S, the pixel region P, and the data region D are defined on the substrate 100, and the plurality of regions S, P, and D are defined. The semiconductor layer 142 is configured to correspond to the defined switching region S on the substrate 100.

The data line 130, the data pad 162 positioned at one end of the data line 130, and the source electrode 132 extending from the data line 130 are disposed on the semiconductor layer 142 in one direction. And a drain electrode 134 spaced apart from the source electrode 132.

The semiconductor layer 142 includes an active layer 140 made of pure amorphous silicon (a-Si: H) and an ohmic contact layer 141 made of amorphous silicon (n + a-Si: H) containing impurities. . At this time, the ohmic contact layer 141 disposed under the source and drain electrodes 132 and 134 is separated and the active layer 140 exposed under the ohmic contact layer 141 is overetched to remove the portion. It is used as a channel (ch).

In this case, first and second semiconductor patterns 140b and 141b are formed under the data line 130 and the data pad 162. The first and second semiconductor patterns 140b and 141b extend from the active and ohmic contact layers 140 and 141, respectively, and are inevitably configured to reduce the number of mask processes.

The passivation layer 155 is formed on the source and drain electrodes 132 and 134, the data line 130, and the data pad 162 by selecting one of a group of organic insulating materials including photoacryl or benzocyclobutene. In this case, the passivation layer 155 may include a channel hole H1, a drain hole H2, and a data pad hole (not shown) for exposing a portion of each of the channel ch part, the drain electrode 134, and the data pad 162. ).

On the passivation layer 155 including the channel hole H1, the drain hole H2, and the data pad hole (not shown), the gate insulating layer 145 is formed of one selected from a group of inorganic insulating materials including silicon oxide and silicon nitride. do.

On the gate insulating layer 145, a gate wiring 120 defining a pixel area P perpendicularly crossing the data wiring 130, a gate pad 152 positioned at one end of the gate wiring 120, and The gate electrode 125 extends from the gate line 120.

The region defined by the vertical cross between the gate line 120 and the data line 130 is referred to as a pixel area P. In this case, a thin film transistor including a gate electrode 125, a gate insulating layer 145, a semiconductor layer 142, and source and drain electrodes 132 and 134 at an intersection point of the gate line 120 and the data line 130. (T) is located.

In this case, the gate insulating layer 145 includes a drain contact hole CH2 and a data pad contact hole CH3 for exposing a part of each of the drain electrode 134 and the data pad 162.

The pixel electrode 170, which is in contact with the drain electrode 134 through the drain contact hole CH2, is formed on the gate electrode 125 and the gate line 120 to correspond to the pixel region P. Referring to FIG. In this case, the pixel electrode 170 is designed to extend to the data line 130 so that portions of the pixel electrode 170 overlap each other.

In addition, the gate pad electrode 154 and the data pad electrode 164 made of a transparent conductive material are respectively formed on the gate pad 152 and the data pad 162.

Unlike the conventional structure, the gate insulating film 145 made of an inorganic insulating material having excellent film quality not only protects the channel ch portion, but also the gate insulating film between the pixel electrode 170 and the protective film 155. Since the 145 is positioned, there is an advantage in that the contact characteristic of the pixel electrode 170 can be improved.

In addition, the present invention can provide a pixel design having excellent film quality between array elements without forming an additional insulating film, and has the advantage of manufacturing an array substrate for a high aperture liquid crystal display device in a five mask process.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

6A to 6H, 7A to 7H, and 8A to 8H are cross-sectional views illustrating a process sequence by cutting along the lines V-V, V-V, and V-V of FIG. 4, respectively.

6A to 6C, 7A to 7C, and 8A to 8C are cross-sectional views illustrating a first mask process step.

As illustrated in FIGS. 6A to 8A, a step of defining a switching region S, a pixel region P, a gate region G, and a data region D on the substrate 100 is performed. A pure amorphous silicon layer 140a made of pure amorphous silicon (a-Si: H) and amorphous silicon (n +) including impurities on the substrate 100 having the plurality of regions S, P, G, and D defined therein. The impurity amorphous silicon layer 141a made of a-Si: H) is sequentially stacked.

Next, on the substrate 100 on which the pure and impurity amorphous silicon layers 140a and 140b are formed, copper (Cu), molybdenum (Mo), molybdenum alloy (MoTi), aluminum (Al), aluminum alloy (AlNd) and The source and drain metal layers 138 are formed of one or more selected from the group of conductive metals including chromium (Cr) and the like.

Subsequently, a photoresist is formed on the substrate 100 on which the source and drain metal layers 138 are formed to form a photoresist layer 180, and half with a transmissive portion A on an upper side of the photoresist layer 180. The halftone mask HTM consisting of the transmissive part B and the blocking part C is aligned.

The halftone mask HTM forms a translucent film on the transflective portion B to lower the intensity of light or to reduce the amount of light transmitted so that the photosensitive layer 180 may be incompletely exposed. In this case, in addition to the halftone mask HTM, a slit mask may be used to control the amount of light transmitted by placing a slit shape on the transflective portion B.

In addition, the blocking unit C serves to completely block light, and the transmitting unit A transmits light so that the photosensitive layer 180 exposed to light is chemically changed, that is, fully exposed.

At this time, the transflective portion B is positioned between the blocking portions C on both sides corresponding to the switching region S, and the blocking portion C is positioned corresponding to the data region D. The entire region except for the transmission portion A is located.

Next, as shown in FIGS. 6B to 8B, when the process of exposing and developing the upper half spaced from the above-described halftone mask (HTM of FIGS. 6A to 8A) is performed, the amount of the switching region S is increased. There is no change in thickness in the blocking portion (C of FIG. 6A), and the first photosensitive pattern 182 whose thickness is lowered by about half corresponding to the semi-transmissive portion (C of FIG. 6A) between the blocking portions (C of FIG. 6A). ) Is formed.

In addition, second and third photosensitive patterns 184 and 186 having no thickness change corresponding to the data region D are formed, respectively, and photosensitive layers corresponding to the entire region except for the above (180 in FIGS. 6A to 8A). ) Are removed to expose the underlying source and drain metal layers (138 of FIGS. 6A-8A).

Next, the first to third photosensitive patterns 182, 184, and 186 are used as masks, and the exposed source and drain metal layers (138 of FIGS. 6A to 8A) are patterned using a first mask to form the switching region. The active layer 140, the ohmic contact layer 141, and the source and drain patterns 136 are sequentially stacked to correspond to (S), and the first and second semiconductor patterns 140b correspond to the data region D. FIG. And data lines 130 and data pads 162 including 141b, respectively.

In this case, the first and second semiconductor patterns 140b and 141b extend from the active and ohmic contact layers 140 and 141, respectively, and the data line 130 and the data pad 162 may be reduced to reduce the number of mask processes. It is inevitably configured in the lower part.

6C to 8C, when the ashing of the first to third photosensitive patterns (182, 184 and 186 of FIGS. 6B to 8B) is performed, the first to third photosensitive patterns 182, 184, 186, the thickness is reduced to about half. In particular, the portion of the first photosensitive pattern 182 corresponding to the transflective portion (B of FIG. 6A) is removed to expose the source and drain patterns 136 of FIG. 6B.

Next, the first to third photosensitive patterns 182, 184, and 186 are used as masks, and the exposed source and drain patterns (136 of FIG. 6B) are patterned by a wet etching process, so that both sides are spaced apart from each other. And drain electrodes 132 and 134. Subsequently, the ohmic contact layer 141 exposed between the source and drain electrodes 132 and 134 is spaced apart from each other, and the active layer corresponding to the ohmic contact layer 141 separated to both sides is formed. 140 is overetched to utilize this portion as a channel (ch).

In this case, the active layer 140 and the ohmic contact layer 141 may be referred to as a semiconductor layer 142.

Next, the first to third photosensitive patterns 182, 184, and 186 are removed by a strip process.

As described above, the first mask process step is finally completed through the above-described process step.

6D and 6E, 7D and 7E, and 8D and 8E are process cross-sectional views illustrating a second mask process step.

As shown in FIGS. 6D to 8D, photoacryl and benzocyclobutene are formed on the entire upper surface of the substrate 100 on which the semiconductor layer 142, the source and drain electrodes 132 and 134, the data wiring 130, and the like are formed. The passivation layer 155 is formed of one selected from the group of organic insulating materials included.

Next, as shown in FIGS. 6E to 8E, the passivation layer 155 corresponding to each of the channel ch part, the drain electrode 134, and the data pad 162 is patterned using a second mask to form the channel. A channel hole H1, a drain hole H2, and a data pad hole H3 exposing a portion of the (ch) portion, the drain electrode 134, and the data pad 162 are formed.

In the second mask process, in particular, the channel hole H1 is formed such that the passivation layer 155 does not exist on the exposed surface of the active layer 140 corresponding to the channel ch portion.

6F through 8F are cross-sectional views illustrating a third mask process step.

As shown in FIGS. 6F to 8F, a gate insulating layer is selected from the above-described inorganic insulating material groups on the passivation layer 155 including the channel hole H1, the drain hole H2, and the data pad hole H3. 145 is formed.

Next, a gate metal layer (not shown) is formed on at least one of the above-described conductive metal groups on the substrate 100 on which the gate insulating layer 145 is formed and patterned with a third mask to form the gate region ( Corresponding to G), a gate wiring (120 in FIG. 4) having a gate pad 152 at one end and a gate electrode 125 extending from the gate wiring (120 in FIG. 4) are formed.

In this case, the gate electrode 125, the gate insulating layer 145, the semiconductor layer 142, and the source and drain electrodes 132 and 134 form a thin film transistor T.

The above-described configuration has a structure in which the gate insulating film 145 having excellent film quality protects the channel ch portion instead of the protective film 155 corresponding to the channel ch portion, so that the driving characteristics of the thin film transistor T are deteriorated. To prevent it.

In other words, in the related art, since the passivation layer 155 on the channel part ch was formed of an organic insulating material, penetration of contaminants such as dust or foreign substances was easily performed through the organic insulating material. Designing to protect the channel part with an excellent inorganic insulating material has an advantage of improving the driving characteristics of the thin film transistor (T).

6G to 8G are process cross-sectional views illustrating a fourth mask process step.

6G to 8G, the gate insulating layer 145 corresponding to each of the drain electrode 134 and the data pad 162 is patterned using a fourth mask to expose the drain electrode 134. Each of the drain contact holes CH2 and the data pad contact holes CH3 exposing the data pads 162 is formed.

At this time, unlike the prior art, the protective layer 155 and the gate insulating layer 145 are not simultaneously patterned at the time of exposing a part of the drain electrode 134 and the data pad 162, and each hole H2 and H3 is not patterned. ) And the contact hole (CH2, CH3) can be formed by the dual structure that does not require an additional mask process.

6H to 8H are cross-sectional views illustrating a fifth mask process step.

6H to 8H, indium tin oxide and indium zinc oxide may be included on the gate insulating layer 145 including the drain contact hole CH2 and the data pad contact hole CH3. Selected one of the transparent conductive metal groups is deposited to form a transparent metal layer (not shown), and the pattern is patterned using a fifth mask to contact the pixel electrode 170 in contact with the drain electrode 134 through the drain contact hole CH2. It is formed corresponding to the pixel region P.

At the same time, a data pad electrode 164 in contact with the data pad 162 and a gate pad electrode 152 in contact with the gate pad 150 are formed through the data pad contact hole CH3.

In this case, since the gate insulating layer 145 made of an inorganic insulating material is positioned between the pixel electrode 170 and the passivation layer 155, the interface characteristics of the pixel electrode 170 may be improved.

As described above, the array substrate for the liquid crystal display device according to the present invention may be manufactured by the five mask process through the above process.

As described above, in the present invention, an array substrate for a high-aperture liquid crystal display device having excellent device characteristics without using an additional insulating layer may be manufactured in a five mask process.

In this case, the present invention can be applied not only to the transverse electric field type liquid crystal display device in which the common electrode and the pixel electrode are formed on the same plane, but also to the polysilicon liquid crystal display device in which the semiconductor layer is made of polycrystalline silicon. This is obvious to me.

Accordingly, it is well known that the present invention is not limited to the above embodiments, and various modifications and changes can be made without departing from the spirit and spirit of the invention.

1 is a plan view showing a unit pixel of a conventional array substrate for a liquid crystal display device.

2 is a cross-sectional view taken along the line II-II of FIG.

3 is a cross-sectional view taken along the line II-II of FIG.

4 is a plan view showing unit pixels of an array substrate for a liquid crystal display according to the present invention;

FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4. FIG.

6A to 6H are cross-sectional views taken along the line VV of FIG. 4 and shown in a process sequence.

7A to 7H are cross-sectional views illustrating a process sequence by cutting along the line VII-VII of FIG. 4.

8A to 8H are cross-sectional views illustrating a process sequence by cutting along the line VII-VII of FIG. 4.

* Explanation of symbols for the main parts of the drawings *

100 substrate 125 gate electrode

130: data wiring 132: source electrode

134: drain electrode 140: active layer

141: ohmic contact layer 140b, 141b: first and second semiconductor patterns

142 semiconductor layer 145 gate insulating film

155: protective film 170: pixel electrode

H1: channel hole H2: drain hole

CH2: Drain contact hole ch: Channel

Claims (18)

A substrate; A semiconductor layer formed on the substrate; A data wiring formed in one direction on the semiconductor layer, a source electrode extending from the data wiring and in contact with the semiconductor layer, and a drain electrode spaced apart from the source electrode; A passivation layer covering upper portions of the source and drain electrodes and the data line and including first and second holes respectively exposing the semiconductor layer and a portion of the drain electrode exposed between the source and drain electrodes; A gate insulating layer covering the first and second holes and including a drain contact hole exposing a portion of the drain electrode; A gate wiring on the gate insulating film, a gate electrode extending from the gate wiring and overlapping the semiconductor layer with the gate insulating film interposed therebetween; A pixel electrode in contact with the drain electrode through the drain contact hole Array substrate for a liquid crystal display device comprising a. The method of claim 1, The semiconductor layer includes an active layer made of pure amorphous silicon and an ohmic contact layer made of amorphous silicon including impurities, and separately separates the ohmic contact layer positioned between the source and drain electrodes. And over-etching the active layer corresponding to the ohmic contact layer separated by the channel to form the channel as a channel. The method of claim 2, And the channel is covered by the gate insulating film. The method of claim 1, And the gate insulating layer is disposed between the pixel electrode and the passivation layer. The method of claim 1, And the gate insulating layer is formed of one selected from the group of inorganic insulating materials including silicon oxide and silicon nitride. The method of claim 1, And the passivation layer is selected from a group of organic insulating materials including photoacryl and benzocyclobutene. The method of claim 1, One end of the data line includes a data pad, a third hole in which a portion of the passivation layer covering the data pad is removed, and a data pad contact hole in which a portion of the gate insulating layer covering the third hole is removed. An array substrate for a liquid crystal display device, further comprising a data pad electrode in contact with the pad. The method of claim 1, And at least one gate pad and a gate pad electrode in contact with the gate pad at one end of the gate line. The method of claim 1, And the semiconductor layer is made of polycrystalline silicon. Preparing a substrate; Forming a semiconductor layer, source and drain electrodes, and data lines on the substrate; Forming a passivation layer on the substrate including the semiconductor layer, the source and drain electrodes, and the data line, having a first hole and a second hole exposing a part of each of the semiconductor layer and the drain electrode; Wow; Forming a gate insulating layer on the passivation layer including the first and second holes with one selected from a group of inorganic insulating materials; Forming a gate wiring and a gate electrode on the gate insulating film; Forming a drain contact hole exposing a portion of the drain electrode; Forming a pixel electrode in contact with the drain electrode Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 10, The semiconductor layer includes an active layer made of pure amorphous silicon and an ohmic contact layer made of amorphous silicon including impurities, and separately separates the ohmic contact layer positioned between the source and drain electrodes. And over-etching the active layer corresponding to the ohmic contact layer separated by a channel to form a portion as a channel. The method of claim 11, wherein And the channel is covered by the gate insulating film. The method of claim 10, And the gate insulating film is positioned between the pixel electrode and the passivation layer. The method of claim 10, And the gate insulating film is formed of one selected from the group of inorganic insulating materials including silicon oxide and silicon nitride. The method of claim 10, And the protective film is formed of one selected from the group of organic insulating materials including photoacryl and benzocyclobutene. The method of claim 10, One end of the data line includes a data pad, a third hole in which a portion of the passivation layer covering the data pad is removed, and a data pad contact hole in which a portion of the gate insulating layer covering the third hole is removed. A method of manufacturing an array substrate for a liquid crystal display device, further comprising a data pad electrode in contact with the pad. The method of claim 10, And a gate pad and a gate pad electrode in contact with the gate pad at one end of the gate wiring. The method of claim 10, And the semiconductor layer is formed of polycrystalline silicon.

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