KR20090054339A - Method for forming multilayer wiring of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer wiring of a semiconductor device, wherein a first photoresist pattern is formed on an entire surface of a semiconductor substrate on which an isolation layer is formed, and then the semiconductor substrate is first etched using the first photoresist pattern as a mask to form a semiconductor substrate. Forming a first etching pattern on the semiconductor substrate, forming a second photoresist pattern on the semiconductor substrate after forming the first etching pattern, and second etching the semiconductor substrate using the second photoresist pattern as a mask to form a second etching pattern on the semiconductor substrate. And forming a third photoresist pattern on the semiconductor substrate after forming the second etching pattern, performing an ion implantation process on the channel region of the semiconductor substrate using the third photoresist pattern as a mask, and forming a gate on the channel region. After forming the electrode, a low-concentration ion implantation process is performed to form an LDD region, and sidewalls are formed on the sidewalls of the gate electrode. Subjected to high-concentration ion implantation process after the formation of the gate electrode and the sidewall spacer regions of the document in the upper mask it is characterized in that for forming the source / drain regions. According to the present invention, the breakdown voltage between the source and the drain may be increased to increase the stability of the semiconductor device, and the operation speed of the device may be increased by reducing the RC delay time by minimizing the occurrence of parasitic overlap capacitance. In addition, it is possible to reliably implement the analog matching characteristics to facilitate circuit design design, and to increase the market competitiveness compared to semiconductor devices having the same gate length.

Light Doped Drain (LDD), Overlap Capacitance

Description

Method of forming multilayer wiring of semiconductor device {METHOD FOR MANUFACTURING SIDEWALL SPACER OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a method for forming a multilayer wiring of a semiconductor device suitable for minimizing parasitic capacitance caused by gate length reduction due to semiconductor miniaturization.

Due to the high integration of devices according to the development of semiconductor manufacturing technology, metal wirings on a circuit are gradually formed with fine line widths, and the spacing between the wirings is also miniaturized.

As a result, gate lengths of transistors using a light doped drain (LDD) structure are also decreasing. Accordingly, studies to increase device performance at the same gate length have been actively conducted. .

1 is a process flowchart illustrating a method for forming a multilayer wiring of a semiconductor device according to the prior art, for example, an LDD formation method.

Referring to FIG. 1, the method for forming a multilayer wiring of a semiconductor device according to the prior art proceeds as follows.

First, as the semiconductor substrate 100, an isolation layer 102 defining an active region and an inactive region is formed on a silicon substrate. For example, the semiconductor substrate 100 is etched to a predetermined depth to form a trench, an insulating material filling the trench, an HDP (High Density Plasma) oxide film is buried, and an insulating material by a chemical mechanical polishing (CMP) process. The trench trench (Shallow Trench Isolation: type STI) type device isolation film 102 is polished to form a thin film.

An insulating film, for example, silicon oxide film (SiO ₂ ), is deposited on the entire surface of the semiconductor substrate 100 on which the device isolation film 102 is formed, and a doped polysilicon doped with a gate conductive film, for example, an impurity is deposited thereon. Deposit about 3000Å. The gate conductive layer may be formed of silicon germanium (SiGe), cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), tantalum (Ta), titanium nitride (TiN), in addition to polysilicon doped with impurities. The tantalum nitride film TaN, the tungsten nitride film WN, or a composite thereof may be formed.

A photolithography process is performed to form a photoresist pattern (not shown) defining a gate region in the gate conductive film, and the gate conductive film exposed by the pattern is dry etched, for example, reactive ion etching (RIE). As a result, the gate electrode 106 is formed, and the insulating film beneath it is also dry-etched to form the gate insulating film 104. The photoresist pattern is removed by an ashing process.

Next, using the gate electrode 106 as an ion implantation mask, a low concentration ion implantation process (for example, a low concentration of ion implanted n-type dopant) is performed to form the LDD region 108.

Subsequently, an insulating material, for example, a silicon nitride layer (SiN) or a silicon oxynitride layer (SiON), is deposited on the entire surface of the semiconductor substrate 100 and then dry-etched, for example, reactive ion etching (RIE), to form a sidewall of the gate electrode 106. The spacer 110 is formed on the substrate.

Then, using the spacer 110 and the gate electrode 106 as an ion implantation mask, a high concentration ion implantation process (for example, a high concentration of ion implanted n-type dopant) is performed to form the source / drain region 112. .

Subsequently, as a etch stop film on the entire surface of the semiconductor substrate structure on which the semiconductor element such as the gate electrode 106, the MOS transistor having the source / drain regions, etc. were formed, a silicon nitride film (SiN) was thinly formed to a thickness of 300 kV to 500 kV. As an interlayer insulating film (IMD) 114 on the top, an insulating film such as an O ₃ -TEOS oxide film, a BPSG insulating film, an HDP CVD oxide film, etc., having excellent gap fill characteristics, is deposited thicker than about 7000 kPa. Here, the interlayer insulating layer (IMD) 114 serves to gapfill the space between the lower semiconductor devices.

Thereafter, a wiring structure as shown in FIG. 1 is finally formed through a patterning process, an etching process, a tungsten deposition process, a CMP process, and the like, for forming a contact hole.

At this time, in the conventional semiconductor device manufacturing process, as the length of the gate becomes smaller and smaller, parasitic capacitance, for example, overlap capacitance A, as illustrated in FIG. 2, may be generated.

Such overlap capacitance, as can be seen by reference sign B of FIG. 2, may degrade the puch through voltage between the source and the drain, thereby reducing the stability of the semiconductor device.

Accordingly, the present invention is to implement a more stable semiconductor device by improving the breakdown voltage drop phenomenon occurs as the gate length is reduced in the semiconductor LDD structure.

In addition, the present invention, by reducing the parasitic capacitance (overlap capacitance) to achieve a matching characteristic with analog devices more easily and stably in a semiconductor device having the same gate length.

According to a preferred embodiment of the present invention, after forming a first photoresist pattern on the entire surface of the semiconductor substrate on which the device isolation layer is formed, the semiconductor substrate is first etched using the first photoresist pattern as a mask. Forming a first etching pattern on the semiconductor substrate, forming a second photoresist pattern on the semiconductor substrate after forming the first etching pattern, and secondly forming the semiconductor substrate using the second photoresist pattern as a mask; Etching to form a second etching pattern on the semiconductor substrate, and after forming the second etching pattern, forming a third photoresist pattern on the semiconductor substrate and using the third photoresist pattern as a mask. Performing an ion implantation process on the channel region of the substrate, and forming a gate electrode on the channel region Thereafter, a low concentration ion implantation process is performed to form an LDD region, and sidewall spacers are formed on the sidewalls of the gate electrode, and a high concentration ion implantation process is performed using the regions on the gate electrode and the sidewall spacers as masks, thereby forming a source / drain region. Forming a multi-layer wiring of a semiconductor device comprising the step of forming a.

According to the present invention, the breakdown voltage between the source and the drain may be increased to increase the stability of the semiconductor device, and the operation speed of the device may be increased by reducing the RC delay time by minimizing the occurrence of parasitic overlap capacitance. In addition, it is possible to reliably implement the analog matching characteristics to facilitate circuit design design, and to increase the market competitiveness compared to semiconductor devices having the same gate length.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3A to 3J are flowcharts illustrating a method of forming a multilayer wiring of a semiconductor device according to an exemplary embodiment of the present invention.

3A to 3J, the process of forming a multilayer wiring of a semiconductor device according to an exemplary embodiment of the present invention is performed as follows.

First, as shown in FIG. 3A, an isolation layer (not shown) defining an active region and an inactive region is formed on a silicon substrate as the semiconductor substrate 300, and then the entire semiconductor substrate 300 on which the isolation layer is formed. An insulating film, for example, a silicon oxide film (SiO ₂ ) is deposited on the substrate, and a gate conductive film, for example, doped polysilicon doped with impurities, is deposited on the substrate. The gate conductive layer may be formed of silicon germanium (SiGe), cobalt (Co), tungsten (W), titanium (Ti), nickel (Ni), tantalum (Ta), titanium nitride (TiN), in addition to polysilicon doped with impurities. The tantalum nitride film TaN, the tungsten nitride film WN, or a composite thereof may be formed.

Thereafter, a first photoresist (not shown) is coated on the entire surface of the semiconductor substrate 300, and then an exposure process is performed to form a first photoresist pattern 302.

In FIG. 3B, the first photoresist pattern 302 formed as described above may be subjected to primary dry etching, for example, reactive ion etching (RIE) b, to form a first etching pattern on the semiconductor substrate 300. 304). In FIG. 3B, reference numeral 300 ′ represents a semiconductor substrate after such a first dry etching process.

Next, in FIG. 3C, the first photoresist pattern 302 is removed through, for example, an ashing process, and a second photoresist (not shown) is formed on the entire surface of the first etching pattern 304. After the coating process, an exposure process is performed to form a second photoresist pattern 306, and second dry etching, for example, reactive ion etching, is performed using the second photoresist pattern 306 as a mask. A second etching pattern 308 is formed on the substrate 300 ′. In FIG. 3C, reference numeral 300 ″ denotes a semiconductor substrate after such a secondary dry etching process. As can be seen in FIG. 3C, the second etching pattern 308 includes the first etching pattern 304 of FIG. 3B.

After the second etching pattern 308 is formed, in FIG. 3D, the second photoresist pattern 306 is removed through an ashing process, and a third photoresist (not shown) is applied. The exposure process may be performed to form the third photoresist pattern 309, and the ion implantation process may be performed on the channel region 310 of the semiconductor device using the third photoresist pattern 309 as a mask.

Next, in FIG. 3E, a photoresist pattern (not shown) defining a gate region is formed on the gate conductive layer by performing a photolithography process, and the gate conductive layer exposed by the pattern is dry etched, for example, reactive ion etching (RIE). ) To form the gate electrode 314, and the insulating film underneath it is also dry-etched to form the gate insulating film 312. The photoresist pattern is removed by an etching process.

3F and 3G, after applying a fourth photoresist (not shown) on the gate electrode 314, an exposure process is performed to form a fourth photoresist pattern 316. The LDD region 318 is formed by performing a low concentration ion implantation process (for example, by implanting an n-type dopant at low concentration) using the photoresist pattern 309 as a mask. Alternatively, the LDD region 318 may be formed by performing a low concentration ion implantation process using the gate electrode 314 as an ion implantation mask without using the fourth photoresist pattern 309.

Next, in FIG. 3H, an oxide film for forming sidewall spacers (not shown) is deposited on the entire surface of the semiconductor substrate 300 ″, followed by dry etching, for example, reactive ion etching (RIE). Sidewall spacers 320 are formed on sidewalls of the electrode 314. In this case, the oxide film for forming the sidewall spacers may be deposited to a thickness of preferably 900 kPa to 1200 kPa, more preferably 1000 kPa.

Subsequently, in FIG. 3I, a fifth photoresist (not shown) is coated on the gate electrode 314 and the sidewall spacer 320, and an exposure process is performed to form a fifth photoresist pattern 322. The source / drain region 324 is formed by performing a high concentration ion implantation process (for example, ion implantation with a high concentration of an n-type dopant) using the fifth photoresist pattern 322 as a mask. Alternatively, the source / drain region 324 may be formed by performing a high concentration ion implantation process using the sidewall spacer 320 and the gate electrode 314 as an ion implantation mask. In this embodiment, the etching depth is determined in consideration of the energy and the ion implantation amount of the source / drain region 324.

Subsequently, in FIG. 3J, a silicon nitride film (SiN) is thinly formed to a thickness of 300 to 500 kV as an etch stop film on the entire surface of the semiconductor substrate structure on which semiconductor elements such as the gate electrode 314 and the MOS transistor having the source / drain regions are formed. After that, as an interlayer insulating film (IMD) 326, insulating films such as an O ₃ -TEOS oxide film, a BPSG insulating film, and an HDP CVD oxide film having excellent gap fill characteristics are deposited at a thickness of about 7000 kPa or more. Here, the interlayer insulating layer (IMD) 324 serves to fill the space between the lower semiconductor elements.

After depositing the interlayer insulating layer (IMD) 326, a barrier metal layer, for example, Ti / TiN, is deposited, and then filled with a metal material, for example, tungsten (W), and then an additional deposition process is performed to contact 328. ).

Finally, the metal line 330 is formed on the contact 328 by the pattern forming process, thereby completing the final multilayer wiring structure of the semiconductor device.

As shown in FIG. 3J, it can be seen that the overlap capacitance, which is a parasitic capacitance, does not occur as compared with the conventional multilayer wiring structure as shown in FIG. 2.

As described above, the present invention improves the breakdown voltage drop caused by the short gate length in the LDD structure of the semiconductor device, thereby stably realizing matching characteristics with the analog device in the semiconductor device having the same gate length.

Meanwhile, the embodiments of the present invention have been described in detail, but the present invention is not limited to these embodiments, and various modifications may be made by those skilled in the art within the spirit and scope of the present invention described in the claims below. to be.

1 is a cross-sectional view for explaining a method for forming a multilayer wiring of a semiconductor device according to the prior art;

2 is a diagram illustrating a multilayer wiring structure of a semiconductor device in which overlap capacitance is generated;

3A to 3J are process flowcharts illustrating a method for forming a multilayer wiring of a semiconductor device according to a preferred embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

300: semiconductor substrate 302: first photoresist pattern

304: first etching pattern 306: second photoresist pattern

308: second etching pattern 312: gate insulating film

314: gate electrode 318: LDD region

320 sidewall spacer 324 source / drain regions

Claims (5)

Forming a first etching pattern on the semiconductor substrate by first etching the semiconductor substrate using the first photoresist pattern as a mask after forming a first photoresist pattern on the entire semiconductor substrate on which the device isolation layer is formed; Forming a second photoresist pattern on the semiconductor substrate after the formation of the first etching pattern and second etching the semiconductor substrate using the second photoresist pattern as a mask to form a second etching pattern on the semiconductor substrate; and, Forming a third photoresist pattern on the semiconductor substrate after forming the second etching pattern, and performing an ion implantation process on the channel region of the semiconductor substrate using the third photoresist pattern as a mask; Forming a LDD region by forming a gate electrode on the channel region and then performing a low concentration ion implantation process; After forming sidewall spacers on the sidewalls of the gate electrode, a process of forming a source / drain region by performing a high concentration ion implantation process using the regions of the gate electrode and the upper sidewall spacers as a mask. Multi-layered wiring forming method of a semiconductor device comprising a. The method of claim 1, And the first etching pattern is included in the second etching pattern. The method of claim 1, The first and second etching is a method of forming a multilayer wiring of a semiconductor device, characterized in that the reactive ion etching (RIE). The method of claim 1, And determining an etching depth in consideration of energy and ion implantation amount of the source / drain region. The method of claim 1, And forming an interlayer insulating film, a contact, and a metal line sequentially after forming the source / drain regions.

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