KR20090060602A - Sub word line driver and semiconductor memory device including same - Google Patents

Abstract

A sub-word line driver increasing the area margin of the core region and a semiconductor memory device including the same are provided to reduce the entire chip size by excluding the sub-word line driver control block. A sub-word line driver comprises a driving unit(212) and a sink unit(214). The power supply terminal of the driving part is connected to the main word line. The driving unit controls the potential level of the sub word line. The driving unit comprises the first and the second transistor. The sub word line enable signal is inputted to the gate terminal of the first and the second transistor. The source terminal of the first transistor is connected to the main word line. The drain of the first and the second transistor is connected to the sub word line. The potential level of the sub word line is sunk according to the sink part is the potential level of the main word line.

Description

Sub-Word Line Driver and Semiconductor Memory Apparatus with the Same}

The present invention relates to a semiconductor memory device, and more particularly, to a sub word line driver of a semiconductor memory device.

In general, DRAM (Dynamic Random Access Memory) has a large number of memory cells consisting of one transistor and one capacitor to store data. Each memory cell is connected to a word line and a bit line, and when the word line is activated, the memory cell receives data from the bit line or outputs data to the bit line. The word line is divided into a main word line and a sub-word line. One main word line is connected to a plurality of preset sub word line drivers (eg, eight), and each of the plurality of sub word line drivers is connected to one sub word line. Each sub word line is directly connected to a plurality of memory cells.

A row decoder is provided in the memory cell area, and the row decoder decodes the row address to generate a main word line enable signal and a sub word line enable signal to selectively activate the main word line and the sub word line. Do this. When the main word line enable signal is enabled, the main word line driver activates one main word line. Subsequently, the sub word line driver receiving the enabled sub word line enable signal among the plurality of sub word line drivers connected to the activated main word line activates the corresponding sub word line to support data input / output operations of the corresponding memory cells. .

Hereinafter, a conventional semiconductor memory device will be described in more detail with reference to FIG. 1.

1 is a block diagram schematically illustrating a core region of a conventional semiconductor memory device.

In the drawing, a memory cell region 1 having a plurality of memory cells, a bit line sense amplifier block 2 connected to the memory cell region 1 through a plurality of bit lines (not shown), and the memory cell A word line driver block 3 connected to the region 1 through a plurality of sub word lines (not shown) and a plurality of sub word line enable signals swen <1: 4> A sub-wordline driver control block 4 is shown which inverts and transfers a sub-subwordline enable signal / swen <1: 4> to the wordline driver block 3.

The word line driver block 3 includes a main word line driver and a sub word line driver. In this case, the main word line driver is connected to a plurality of sub word line drivers through a main word line, and the main word line driver is connected to the main word line enable signal mwen from a row decoder. Activate the word line. When the main word line is activated, the corresponding sub word line drivers selectively activate each sub word line in response to the pre-allocated sub word line enable signals swen <1: 4>.

Here, when the sub word line driver deactivates the corresponding sub word line, the sub word line is not affected by the noise caused by the adjacent line, and the potential level does not rise due to the threshold voltage of the MOS transistor. To receive the sub-word word enable signal / swen <1: 4>, respectively. The sub word word enable signal / swen <1: 4> causes the potential level of the sub word line to sink to the level of the ground power supply VSS when the corresponding sub word line is not activated. Perform the function.

As such, the sub-wordline driver operates in response to the sub-wordline enable signal pair (swen <1: 4>, / swen <1: 4>), and the sub-word word enable signal (/ swen <1). Sub wordline driver control block 4 is essentially provided. The sub word line driver control block 4 is provided in a cross area formed between the bit line sense amplifier block 2 and the word line driver block 3. In (4), as many drivers as the number of the sub word line enable signals swen <1: 4> are provided. However, the core area of the semiconductor memory device including the memory cell region 1, the bit line sense amplifier block 2, the word line driver block 3, and the sub word line driver control block 4 has an extremely large area margin. As a small area, the sub word line driver control block 4 provided in the cross area is a factor that hinders the improvement of the degree of integration of the core area.

As described above, the conventional semiconductor memory device has a sub word line driver control block in the cross region between the bit line sense amplifier block and the word line driver block, and only by using the sub word line driver control block can the sub word line driver be stably operated. . However, drivers provided as many as the number of sub word line enable signals in the sub word line driver block suppress the increase in the area margin of the semiconductor memory device. In particular, it is difficult to achieve high integration of the core area of the semiconductor memory device. As such, there is a need for more technical support for arranging core regions in order to achieve high integration of semiconductor memory devices.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and there is a technical problem to provide a sub word line driver and a semiconductor memory device including the same so that the area margin of the core region is increased.

Another object of the present invention is to provide a sub word line driver and a semiconductor memory device including the same, which can reduce chip size by increasing an area margin of a core region.

According to an aspect of the present invention, a sub word line driver includes a power supply terminal connected to a main word line, and drives a sub word line enable signal to drive a potential level of the sub word line. Driving unit for controlling the; And a sink unit for sinking the potential level of the sub word line according to the potential level of the secondary main word line.

In addition, a semiconductor memory device according to another embodiment of the present invention, the main word line; Secondary main wordline; A main word line driver for driving a main word line enable signal to control potential levels of the main word line and the sub main word line; And a sub word line driver configured to control the potential level of the sub word line in response to the potential level of the main word line and the sub main word line and the sub word line enable signal.

The sub word line driver and the semiconductor memory device including the same of the present invention drive a single sub word line enable signal except a sub sub word line enable signal to control a potential level of the sub word line, thereby controlling the sub word line. Removing the driver control block has the effect of increasing the area margin of the core area.

In addition, the sub word line driver and the semiconductor memory device including the same of the present invention do not include the sub word line driver control block as the level of the sub word line is controlled by using the main word line pair, thereby providing an area of the core region. This has the effect of increasing the margin and reducing the overall chip size.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

FIG. 2 is a block diagram illustrating a word line driver block of a semiconductor memory device according to an exemplary embodiment of the present invention. For convenience of description, a memory cell area including one main word line driver and four sub word line drivers is provided. It is a figure typically shown.

As shown, the word line driver block of the semiconductor memory device according to an embodiment of the present invention drives the main word line enable signal mwen to control the potential levels of the main word line pairs M_WL and / M_WL. A main wordline driver 10; Four sub word lines S_WL <1: 4> in response to any one of the four sub word line enable signals swen <1: 4> and the potential levels of the main word line pairs M_WL and / M_WL. And first to fourth sub word line drivers 21 to 24 for controlling any one potential level.

The main word line driver 10 controls the potential level of the main word line M_WL and the sub main word line / M_WL by driving the main word line enable signal mwen. In this case, the sub main word line / M_WL has a potential level opposite to that of the main word line M_WL. When the main word line M_WL is activated, the first to fourth sub word line drivers 21 to 24 connected to the main word line M_WL have respective sub word line enable signals swen <1. In response to: 4>, one of the sub word lines S_WL <1: 4> is activated. In this case, when the main word line M_WL is not activated, the sub main word line / M_WL has a potential level of the four sub word lines S_WL <1: 4> of the ground power source VSS. Sync to level.

As such, when the main word line M_WL is deactivated, the potential levels of the four sub word lines S_WL <1: 4> are sinked under the control of the sub main word line / M_WL. The first through fourth sub word line drivers 21 through 24 do not need to receive the sub word line enable signals swen <1: 4> as signal pairs. Accordingly, the first to fourth sub word line drivers 21 to 24 do not use the sub sub word line enable signal, and use only the sub word line enable signal swen <1: 4>. An operation of controlling the potential levels of the two sub word lines S_WL <1: 4> is performed.

In the semiconductor memory device having such a configuration, the sub word line driver control block may no longer be provided outside the word line driver block. By such a configuration of the core region, the area margin of the core region itself is increased, and the overall chip size is reduced.

FIG. 3 is a detailed configuration diagram of the first sub word line driver illustrated in FIG. 2. Since the first to fourth sub word line drivers are all configured in the same form, the first sub word line driver is described in detail. It is shown to replace the description of the sub word line driver.

As illustrated, the first sub word line driver 21 includes a power supply terminal connected to the main word line M_WL, and drives the first sub word line enable signal swen <1>. A driver 212 controlling the potential level of the first sub word line S_WL <1>; And a sink unit 214 for sinking the potential level of the first sub word line S_WL <1> according to the potential level of the secondary main word line / M_WL.

In this case, the driver 212 receives a first sub word line enable signal swen <1> at a gate end thereof, a source end thereof is connected to the main word line M_WL, and a drain end thereof has a first sub word line ( A first transistor TR1 connected to S_WL <1>; And a second transistor TR2 having the first sub word line enable signal swen <1> input to a gate terminal, a drain terminal thereof connected to the first sub word line S_WL <1>, and a source terminal grounded thereto. );

The sink 214 includes a third transistor having a gate terminal connected to the sub main word line / M_WL, a drain terminal connected to the first sub word line S_WL <1>, and a source terminal grounded. TR3);

The first sub word line enable signal swen <1> may be implemented as a low enable signal.

When the main word line M_WL is inactivated, since the sub main word line / M_WL is activated, the third transistor TR3 of the sink unit 214 is turned on and the first transistor is turned on. The ground power source VSS is applied to one sub word line S_WL <1>. In this case, even if the first sub word line enable signal swen <1> is enabled, the potential level of the first sub word line S_WL <1> does not change.

On the other hand, when the main word line M_WL is activated, since the sub main word line / M_WL is deactivated, the third transistor TR3 of the sink 214 is turned off. do. In this case, since a high level potential is applied to the source terminal of the first transistor TR1 of the driver 212, the first sub word line enable signal swen <1> may be generated. Inverting is driven by the first and second transistors TR1 and TR2. Therefore, when the first sub word line enable signal swen <1> is enabled, the potential of the main word line M_WL is transferred to the first sub word line S_WL <1>, and thus, the first sub word line enable signal swen <1> is enabled. The sub word line S_WL is activated.

As described above, the sub word line driver of the present invention does not receive the sub word line enable signal as a signal pair. Therefore, since the sub word line driver control block is unnecessary, the area margin of the core region of the semiconductor memory device is increased. To this end, the main wordline driver should apply potentials having opposite levels to the main wordline pair in response to the main wordline enable signal. That is, the sub word line driver control block can be removed by replacing the function of the sub sub word line enable signal by using the sub main word line. As such, the semiconductor memory device of the present invention has the advantage that the overall chip size can be reduced as the area margin of the core region is increased.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram schematically illustrating a core region of a conventional semiconductor memory device;

2 is a block diagram showing the configuration of a word line driver block of a semiconductor memory device according to an embodiment of the present invention;

FIG. 3 is a detailed configuration diagram of the first sub word line driver illustrated in FIG. 2.

<Description of the symbols for the main parts of the drawings>

10: main word line driver 21: first sub word line driver

212: drive unit 214: sink unit

Claims (10)

A driver including a power supply terminal connected to the main word line, and controlling a potential level of the sub word line by driving a sub word line enable signal; And A sink configured to sink the potential level of the sub word line according to the potential level of a secondary main word line; The sub wordline driver comprising a. The method of claim 1, And the sub wordline enable signal is a low enable signal. The method according to claim 1 or 2, The driving unit, A first transistor having a sub word line enable signal input to a gate terminal, a source terminal connected to the main word line, and a drain terminal connected to the sub word line; And A second transistor having a sub word line enable signal input to a gate terminal, a drain terminal connected to the sub word line, and a source terminal grounded; The sub wordline driver comprising a. The method according to claim 1 or 2, And the transistor includes a transistor having a gate terminal connected to the sub main word line, a drain terminal connected to the sub word line, and a source terminal grounded. Main wordline; Secondary main wordline; A main word line driver for driving a main word line enable signal to control potential levels of the main word line and the sub main word line; And A sub word line driver controlling the potential level of the sub word line in response to the potential level of the main word line and the sub main word line and a sub word line enable signal; A semiconductor memory device comprising a. The method of claim 5, wherein And the sub word line driver is configured to sink the potential level of the sub word line to the level of ground power under the control of the sub main word line when the main word line is deactivated. The method of claim 6, The sub wordline driver, A driver including a power supply terminal connected to the main word line, and controlling a potential level of the sub word line by driving the sub word line enable signal; And A sink unit for sinking the potential level of the sub word line according to the potential level of the sub main word line; A semiconductor memory device comprising a. The method of claim 7, wherein And the sub word line enable signal is a low enable signal. The method according to claim 7 or 8, The driving unit, A first transistor having a sub word line enable signal input to a gate terminal, a source terminal connected to the main word line, and a drain terminal connected to the sub word line; And A second transistor having a sub word line enable signal input to a gate terminal, a drain terminal connected to the sub word line, and a source terminal grounded; A semiconductor memory device comprising a. The method according to claim 7 or 8, And the transistor includes a transistor having a gate terminal connected to the sub main word line, a drain terminal connected to the sub word line, and a source terminal grounded.

Images