KR20090120688A - Stacked nonvolatile memory device, method for manufacturing same, and memory card and system comprising same - Google Patents

Abstract

The present invention provides a stacked nonvolatile memory device and a memory card and a system including the same, in which multiple memory cell arrays are stacked to improve memory density. A stacked nonvolatile memory device according to some embodiments of the inventive concept may include a lower memory layer including a lower active region and a plurality of lower gate structures; A plurality of lower contact portions electrically connected to the lower active region; An upper memory layer stacked on the lower memory layer and including an upper active region and a plurality of upper gate structures; And a plurality of upper contact portions electrically connected to the upper active region, wherein the uppermost part of the plurality of upper contact parts is formed lower than the uppermost part of the plurality of upper gate structures.

Description

Stack-layered non-volatile memory device, method of manufacturing the same and memory card and system including the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a multilayer nonvolatile memory device capable of stacking multiple memory cell arrays to improve memory density, a method of manufacturing the same, and a memory card including the same. And to the system.

Among the semiconductor memory devices, the nonvolatile memory device is a memory device in which stored data is not destroyed even when power supply is cut off. Recently, as the demand for small portable electronic products such as a portable multimedia playback device, a digital camera, a PDA, and the like increases, a large capacity and high integration of a nonvolatile memory device applied thereto is rapidly progressing. Such nonvolatile memory products may be classified into PROM (Programmable ROM), EPROM (Erasable and Programmable ROM), and EEPROM (Electrically EPROM), and a typical memory device is a flash memory device. The flash memory is characterized in that the erase operation and the rewrite operation are performed in units of blocks. The flash memory is not only replaceable as a main memory in the system but also applicable to a general DRAM interface because of high integration and excellent data integrity. In addition, the flash memory can be replaced with a secondary storage device such as a hard disk because of the high integration, large capacity, and low manufacturing cost.

The operation of the flash memory is generally performed by hot electron injection or F-N tunneling, and the erasing operation is performed by F-N tunneling. In the cell transistor constituting a general flash memory, a tunneling insulating layer, a charge storage layer, a blocking insulating layer, and a control gate formed on a semiconductor substrate are sequentially stacked. Further, for example, in the case of a NAND flash device, a plurality of cell transistors are connected in series to form a string, and one or more select transistors are positioned at the end of the string.

As the directivity of flash memory devices is required to increase, attention has been paid to stacked flash memory devices in which multilayer memory cell arrays are stacked. In a single layer structure, contact portions such as common source line and bit line contact plugs are generally formed so that the height thereof is higher than that of the gate structure. However, in the stacked structure, since the total length of the contact portion is increased, an opening is incompletely formed due to an increase in aspect ratio, resulting in poor contact with the active region on the substrate or even deterioration of insulation between the contact portions. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a stacked nonvolatile memory device capable of reducing the height of a contact portion to prevent incomplete formation of a contact.

Another object of the present invention is to provide a method of manufacturing a stacked nonvolatile memory device capable of reducing the height of a contact portion to prevent incomplete formation of a contact.

Another object of the present invention is to provide a memory card and a system including the nonvolatile memory device.

According to an aspect of the present invention, there is provided a stacked nonvolatile memory device including a lower memory layer including a lower active region and a plurality of lower gate structures; A plurality of lower contact portions electrically connected to the lower active region; An upper memory layer stacked on the lower memory layer and including an upper active region and a plurality of upper gate structures; And a plurality of upper contact parts electrically connected to the upper active area. The uppermost portion of the plurality of upper contact portions may be formed lower than the uppermost portions of the plurality of upper gate structures.

In some embodiments of the present disclosure, a top of a portion of the plurality of bottom contact portions may be lower than a top of the plurality of bottom gate structures.

In some embodiments of the present disclosure, some of the plurality of lower contact portions may be extended to be connected to some of the plurality of upper contact portions.

In some embodiments of the present invention, the plurality of lower and upper contact portions may be a common source line (CSL) or a bit line contact plug.

According to another aspect of the present invention, there is provided a method of manufacturing a stacked nonvolatile memory device, including: providing a lower memory layer including a lower active region and a plurality of lower gate structures; Providing an upper memory layer on the lower memory layer, the upper memory layer including an upper active region and a plurality of upper gate structures; And forming an upper contact portion electrically connected to the upper active region and having an uppermost portion that is equal to or lower than a top of the upper gate structure.

In some embodiments of the present disclosure, forming the upper contact portion may include forming an upper contact hole exposing the upper active region; Filling the upper contact hole with a conductive material; And removing a portion of the upper contact hole filled with the conductive material to form the upper contact portion having the uppermost portion equal to or lower than the uppermost portion of the upper gate structure. In addition, the removing of the partial region of the upper contact portion may use the upper gate structure as an etching mask.

In some embodiments, the providing of the lower memory layer may include forming a lower contact hole exposing the lower active region; Filling the lower contact hole with a conductive material; And removing a portion of the lower contact hole filled with the conductive material to form the lower contact portion having the uppermost portion equal to or lower than the uppermost portion of the lower gate structure. In addition, the removing of the partial region of the lower contact portion may use the lower gate structure as an etching mask.

In some embodiments of the present disclosure, the providing of the upper memory layer may further include wafer bonding the lower memory layer and the upper memory layer.

According to another aspect of the present invention, there is provided a memory card including a nonvolatile memory device, and a memory including the aforementioned nonvolatile memory device, and a controller that controls the memory and exchanges data with the memory. do.

According to another aspect of the present invention, there is provided a system including a nonvolatile memory device including a memory including a nonvolatile memory device, a processor communicating with the memory through a bus, and an input / output communicating with the bus. Device.

In the stacked nonvolatile memory device of the present invention, the uppermost part of the common source line and / or bitline contact plug is formed lower than the uppermost part of the gate structure, thereby preventing contact failure, thereby improving the reliability of the device and improving the device size. Can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art, and the following examples can be modified in various other forms, and the scope of the present invention is It is not limited to an Example. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In addition, the thickness or size of each layer in the drawings is exaggerated for convenience and clarity of description. Like numbers in the drawings refer to like elements. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

Also, relative terms such as "top" or "above" and "bottom" or "bottom" may be used herein to describe the relationship of certain elements to other elements as illustrated in the figures. It may be understood that relative terms are intended to include other directions of the device in addition to the direction depicted in the figures. For example, if the device is flipped in the figures, elements depicted as being on the top of the other elements will be oriented on the bottom of the other elements. Thus, the exemplary term "top" may include both "bottom" and "top" directions depending on the particular direction of the figure. If the device faces in the other direction (rotated 90 degrees relative to the other direction), the relative descriptions used herein can be interpreted accordingly. Also, when referring to a component as being "on" another component, there may be other components directly in contact with or "interposed" on the other component. It can be interpreted that.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular forms may include the plural forms as well, unless the context clearly indicates otherwise. In addition, the words "comprise" and / or "comprising" herein specify the presence of the shapes, numbers, steps, actions, members, elements and / or groups thereof mentioned, and one or more other shapes, numbers, It is not intended to exclude the presence or the addition of operations, members, elements and / or groups.

1 is a block diagram of a stacked nonvolatile memory according to an embodiment of the present invention.

Referring to FIG. 1, a nonvolatile memory includes a memory cell array 10, a page buffer 20, a Y-gating circuitry 30, and a control and decoder circuit. Decoder Circuitry 40 may be provided. The memory cell array 10 may include a plurality of memory blocks, and each of the memory blocks may include a plurality of nonvolatile memory cells. The nonvolatile memory cells may be flash memory cells, for example, NAND flash memory cells. The page buffer 20 may temporarily store data to be written in the memory cell array 10 or data read from the memory cell array 10. The Y-gating circuit 30 may transmit data stored in the page buffer 20. The control and decoder circuit 40 receives a command (CMD) and an address from the outside, and outputs a control signal for writing data to the memory cell array 10 or reading data from the memory cell array 10. And an address can be decoded. The control and decoder circuit 40 may output a control signal for data input / output to the page buffer 20, and may provide address information to the Y-gating circuit 30.

FIG. 2 is a layout diagram illustrating a portion of a memory cell array of a nonvolatile memory according to an embodiment of the present invention, and may represent a portion of the memory cell array 10 described with reference to FIG. 1. 3 is a cross-sectional view of a nonvolatile memory in accordance with some embodiments of the present disclosure, taken along cut lines II ′ of FIG. 2.

2 and 3, the memory cell array 10 includes a lower memory layer 1 and an upper memory layer 2 stacked thereon. The lower memory layer 1 and the upper memory layer 2 may have the same structure, for example, the same gate structures, and may be configured to be aligned with each other. In addition, the memory cell array 10 may include a plurality of upper and lower active regions Act_1 and Act_2 defined by device isolation regions (not shown) formed in the upper and lower semiconductor layers 100_1 and 100_2, respectively. have. The upper active regions Act_2 may be formed in alignment with each other on the lower active regions Act_1. The upper and lower active regions Act_1 and Act_2 may be parallel as a line shape, respectively. Upper and lower String Selection Lines (SSL_1, SSL_2) and upper and lower portions that cross the upper and lower active regions Act_1 and Act_2, respectively, on the upper and lower active regions Act_1 and Act_2. Ground selection lines GSL_1 and GSL_2 may be located respectively. A plurality of upper and lower portions across the top of the upper and lower active regions Act_1 and Act_2 between each of the upper and lower string select lines SSL_1 and SSL_2 and the upper and lower ground select lines GSL_1 and GSL_2. Word lines WL1_1, WL2_1,..., WLn_1, WL1_2, WL2_2,..., WLn_2 may be disposed. Upper and lower string select lines SSL_1 and SSL_2, upper and lower ground select lines GSL_1 and GSL_2, and upper and lower word lines WL1_1, WL2_1, ..., WLn_1, WL1_2, WL2_2, ..., WLn_2 ) May each be parallel to each other. Upper and lower word lines WL1_1, WL2_1, ..., WLn_1, WL1_2, WL2_2, ..., WLn_2, upper and lower string select lines SSL_1 and SSL_2, and upper and lower ground select lines GSL_1 and GSL_2 Impurity regions, i.e., upper and lower source / drain regions 110_1 and 110_2 may be formed in the active regions adjacent to both sides of the substrate. As a result, string select transistors, cell transistors and ground select transistors connected in series are formed in the upper and lower memory layers 1 and 2, respectively. The string select transistor, the ground select transistor, and the cell transistors disposed therebetween may constitute one unit memory block. Impurity regions adjacent to the string select line and opposite to the ground select line may be defined as drain regions of respective string select transistors. In addition, impurity regions adjacent to the ground select line and opposite to the string select line may be defined as source regions of the ground select transistor. The lower word lines WL1_1, WL2_1,..., WLn_1 each have a tunneling insulating layer 122, a charge storage layer 124, a blocking insulating layer 126, and a cell control stacked on the substrate 100 in turn. It may include a gate 128. That is, the tunneling insulating layer 122, the charge storage layer 124, the blocking insulating layer 126, and the cell control gate 128 constitute the lower cell transistor 120_1. The tunneling insulating layer 122 and the charge storage layer 124 may be separated for the lower cell transistors 120_1 adjacent to the lower word lines WL1_1, WL2_1,..., WLn_1.

The blocking insulating layer 126 may be shared by the lower cell transistors 120_1 adjacent to the lower word lines WL1_1, WL2_1,..., WLn_1. Spacers 129 may be disposed on sidewalls of the tunneling insulating layer 122 and the charge storage layer 124, the blocking insulating layer 126, and the cell gate conductive layer 128. The spacer 129 may be composed of multiple layers. In addition, the upper word lines WL1_2, WL2_2,..., WLn_2 may have a similar stacked structure as described above with the lower word lines WL1_1, WL2_1,..., WLn_2. It will be omitted for explanation.

Typically, the widths of the upper and lower string select lines SSL_1 and SSL_2 and the upper and lower ground select lines GSL_1 and GSL_2 are respectively the upper and lower word lines WL1_1, WL2_1, WL2_1, WLn_1, WL1_2, WL2_2, It may be larger than the width of WLn_2). In addition, the upper and lower string select lines SSL_1 and SSL_2 and the upper and lower ground select lines GSL_1 and GSL_2 have the upper and lower word lines WL1_1, WL2_1, WLn_1, WLn_1, WL1_2, WL2_2, ..., WLn_2) may have the same laminated structure. Since the structure of the lower select transistor 130_1 is well known to those skilled in the art, a detailed description thereof will be omitted. A lower interlayer insulating layer 160_1 is provided to cover the lower word lines WL1_1, WL2_1,..., WLn_1, the lower string select line SSL_1, and the lower ground select line GSL_1. A common source line CSL is provided to penetrate the lower interlayer insulating layer 160_1 and connect to the source region of the lower ground select line GSL_1. The common source line CSL may be formed in parallel with the ground select line GSL_1. The common source line CSL will be described in detail later. An upper interlayer insulating layer 160_2 is provided to cover upper word lines WL1_2, WL2_2,..., WLn_2, an upper string select line SSL_2, and an upper ground select line GSL_2. A common source line CSL is provided through the upper interlayer insulating layer 160_2 and connected to the source region of the upper ground select line GSL_2. The common source line CSL may be formed in parallel with the upper ground select line GSL_2. The second interlayer insulating layer 170 may be provided on the upper interlayer insulating layer 160_2. A bit line plug BC is provided to penetrate through the second interlayer insulating layer 170, the upper interlayer insulating layer 160_1, and / or the lower layer to be connected to the drain regions of the upper and / or lower string select lines SSL_1 and SSL_2. Can be. Bit lines BL1, BL2,..., Crossing the upper word lines WL1_2, WL2_2,..., WLn_2 while being connected to the bit line plug BC on the second interlayer insulating layer 170. BLn-1, BLn) may be disposed. The bit lines BL1, BL2,..., BLn-1, BLn may be disposed in parallel with the upper and lower active regions Act_1 and Act_2.

The upper and lower semiconductor layers 100_1 and 100_2 may be conventional semiconductor substrates or epitaxial layers. The upper and lower semiconductor layers 100_1 and 100_2 are for example selected from the group consisting of a silicon substrate, a silicon-on-insulator substrate, a silicon-on-sapphire substrate, a germanium substrate, a silicon-germanium substrate, and a gallium-arsenide substrate. It may include any one. In addition, the upper and lower semiconductor layers 100_1 and 100_2 may be p-type substrates or n-type substrates. However, this is exemplary and the present invention is not necessarily limited thereto.

The lower cell transistor 120_1 includes a tunneling insulating layer 122, a charge storage layer 124, a blocking insulating layer 126, and a cell control gate 128 that are sequentially stacked. Such layers can be formed using conventional deposition methods such as thermal oxidation, chemical vapor deposition (CVD), LPCVD, PECVD or atomic layer deposition (ALD). Each of the tunneling insulating layer 122 and the blocking insulating layer 126 includes silicon oxide, silicon oxynitride, silicon nitride, silicon rich nitride (SRN), aluminum oxide, aluminum nitride, hafnium oxide, hafnium silicon oxide, and hafnium silicon oxynitride. At least one of hafnium oxynitride, hafnium aluminum oxide, zirconium oxide, tantalum oxide, hafnium tantalum oxide, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, and metal oxides. In this specification, an SRN film means a film having a larger Si / N atomic ratio than the stoichiometric Si / N atomic ratio in the Si ₃ N ₄ film. In addition, the metal included in the metal oxide may be, for example, at least one of platinum, palladium, nickel, ruthenium, cobalt, chromium, molybdenum, tungsten, manganese, iron, osmium, iridium, or tantalum. In addition, the first insulating layer 110 may be a single layer structure or a plurality of layer structures having different energy band gaps. The charge storage layer 124 may be a floating gate conductive layer or a charge trap layer. The charge storage layer 124 is formed of silicon oxide, silicon oxynitride, silicon nitride, SRN, aluminum oxide, aluminum nitride, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium oxynitride, hafnium aluminum oxide, zirconium oxide, tantalum. Oxide, hafnium tantalum oxide, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide and metal oxide. In addition, the charge storage layer 124 may be a single layer structure or a plurality of layer structures having different energy band gaps. In addition, although not shown, the charge storage layer 124 may further include nano dots or quantum dots that may capture charge. However, the materials and structures for forming the charge storage layer 124 described above are exemplary, and the present invention is not necessarily limited thereto. The cell control gate 128 includes polysilicon, aluminum, ruthenium, tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, tungsten silicide, hafnium, hafnium nitride, niobium, molybdenum, molybdenum nitride, ruthenium oxide, iridium, platinum , Cobalt, chromium, palladium, and nickel silicide. However, the materials and structures for forming the above-described layers are exemplary, and the present invention is not necessarily limited thereto.

The lower select transistor 130_1 includes a gate insulating layer and a control gate as described above, and a material and a method of forming the layers corresponding to the gate insulating layer and the control gate are respectively corresponding to the lower cell transistor 120_1. The material constituting the layers and the forming method may be the same.

The plurality of lower cell transistors 120_1 are connected in series with each other to form a string, and are connected in series with one or more lower select transistors 130_1 at the end of the string. The lower select transistor 130_1 may be a string select transistor included in the string select line described above or a ground select transistor included in the ground select line. The lower cell transistor 120_1 and the lower select transistor 130_1 may constitute a NAND flash memory. In addition, the structures of the upper cell transistor 120_2 and the upper select transistor 130_2 may be the same as those of the lower cell transistor 120_1 and the lower select transistor 130_1, which will be omitted for the sake of brevity. Shall be. Contact portions such as the common source line CSL and the bit line plug BC are electrically connected to the lower active region Act_1, that is, the lower source / drain regions 110_1. In addition, in the present embodiment, the contact parts, that is, the common source line CSL and the bit line plug BC, are also electrically connected to the upper source / drain regions 110_2, respectively. The top of some of the contact portions is formed lower than the top of the plurality of upper gate structures. In the present exemplary embodiment, the uppermost part of the common source line CSL is formed lower than the uppermost part of the upper cell transistor 120_2 and the upper select transistor 130_2.

4A through 4C are cross-sectional views illustrating a method of manufacturing the nonvolatile memory of FIG. 3 for each process.

Referring to FIG. 4A, a lower memory layer 1 including a lower source / drain region 110_1 and a plurality of lower gate structures, that is, a lower cell transistor 120_1 and a lower select transistor 130_1 is provided. Next, an upper memory layer 2 including an upper source / drain region 110_2 and an upper cell transistor 120_2 and an upper select transistor 130_2 is provided on the lower memory layer 1. The present providing step may be performed by combining the lower memory layer 1 and the upper memory layer 2 separately by using conventional wafer bonding. Alternatively, in the providing step, after forming the upper semiconductor layer (100_2) by the normal lateral epitaxial overgrowth (LEO) on the lower memory layer (1), several layers in the upper semiconductor layer (100_2) The upper gate structure may be formed by depositing the upper gate structure.

Referring to FIG. 4B, contact holes 111 exposing the lower source / drain regions 110_1 are formed. The contact holes 111 may be formed to also expose the upper source / drain region 110_1. That is, the contact holes 111 may be formed to penetrate the upper source / drain region 110_2 to expose the lower source / drain region 110_1. In addition, the contact holes 111 may be formed by a conventional etching method using a conventional mask layer (not shown), for example, a photoresist mask or a hard mask. Alternatively, the contact holes 111 may be formed using the upper gate structure, that is, the upper cell transistor 120_2 and the upper select transistor 130_2 as an etching mask. In this case, the upper gate structure is required to have an etching selectivity with respect to the sacrificial insulating layer 161. Subsequently, the contact holes 111 are filled using a conductive material 112 such as tungsten (W). The conductive material 112 is preferably formed to provide excellent electrical connection with the upper and lower source / drain regions 110_1 and 110_2, respectively. After filling the conductive material 112, it may be planarized through chemical mechanical polishing (CMP) or etch-back. In addition, the contact holes 111 may be filled using two or more conductive materials 112. In this case, this step may be implemented by performing various processes.

Referring to FIG. 4C, the upper regions of the contact holes 111 filled with the conductive material 112 are removed, so that the uppermost portion of the upper cell transistor 120_2 and the upper select transistor 130_2 is equal to or lower than the top of the upper cell transistor 120_2 and the upper select transistor 130_2. To form a contact portion 113 having. The removal may be performed by an etching method using a conventional mask layer or by etch-back. The contact unit 113 may be a common source line CSL or a bit line plug BC. Subsequently, as shown in FIG. 3, a metal contact MC electrically connected to the bit line plug BC is formed and a bit line BLn electrically connected to the metal contact MC is formed. .

In the above-described embodiment, the common source line CSL and the bit line plug BC are simultaneously formed, but this is exemplary and the present invention is not necessarily limited thereto. That is, according to the above-described method, only the common source line CSL may be formed so that the top thereof has the same height as or lower than the top of the gate structure, and then the bit line plug BC may be formed in a separate process. Can be. In this case, the metal contact MC as described above may not be formed.

5 is a cross-sectional view illustrating a nonvolatile memory device according to another embodiment of the present invention. 5, the common source line and the bit line plug are separately formed in the lower memory layer 1 and the upper memory layer 2, respectively. For the sake of brevity of description of the present embodiment, descriptions of portions overlapping with the above-described embodiment will be omitted.

Referring to FIG. 5, the lower source / drain regions 110_1 of the lower memory layer 1 and the upper source / drain regions 110_2 of the upper memory layer 2 are separate lower common source lines CSL_1 and upper portions, respectively. It is electrically connected to the common source line CSL_2. The upper and lower common source lines CSL_1 and CSL_2 may be electrically connected to other components or the outside through separate wires (not shown). At least the lower common source line CSL_1 is formed through a separate process before the upper memory layer 2 is coupled to the lower memory layer 1. As described in the above-described embodiment, the uppermost part of the lower common source line CSL_1 is formed lower than the uppermost part of the lower gate structure, that is, the lower cell transistor 120_1 and the lower select transistor 130_1. Since the description is the same as described above, a description thereof will be omitted. In addition, the uppermost part of the upper common source line CSL_2 is formed lower than the uppermost part of the lower gate structure, that is, the upper cell transistor 120_2 and the upper select transistor 130_2.

The uppermost portions of the upper and lower bitline plugs BC_1 and BC_2 are formed lower than the uppermost portions of the upper cell transistor 120_2 and the upper select transistor 130_2. The upper and lower bit line plugs BC_1 and BC_2 may be formed in the same process as the upper common source line CSL_2 or may be formed in a separate process as described above. In the present embodiment, the upper and lower bit line plugs BC_1 and BC_2 are configured to have a separate structure, but similarly to the above-described embodiment, the upper and lower bit line plugs BC_1 and BC_2 are a single unit. It can be formed as. In addition, as described above, the metal contact MC may not be formed. In this case, the uppermost portions of the upper and lower bitline plugs BC_1 and BC_2 need not be lower than the uppermost portions of the upper gate structure.

6 is a schematic diagram illustrating a memory card 5000 according to an embodiment of the present invention.

Referring to FIG. 6, a controller 510 and a memory 520 may be arranged to exchange electrical signals. For example, when a command is issued from the controller 510, the memory 520 may transmit data. The memory 520 may include a nonvolatile memory device according to any one of embodiments of the present invention. Nonvolatile memory devices according to various embodiments of the present disclosure may be disposed in an “NAND” architecture memory array (not shown) corresponding to a corresponding logic gate design as is well known in the art. Memory arrays arranged in a plurality of rows and columns may constitute one or more memory array banks (not shown). The memory 520 may include such a memory array (not shown) or a memory array bank (not shown). In addition, the card 5000 is a conventional row decoder (not shown), column decoder (not shown), I / O buffers (not shown), and / or control to drive the above-described memory array bank (not shown). A register may be further included. The card 5000 may be used in a memory device such as various types of memory cards.

7 is a schematic diagram illustrating a system 6000 according to an embodiment of the present invention.

Referring to FIG. 7, the system 6000 may include a controller 610, an input / output device 620, a memory 630, and an interface 640. . The system 6000 may be a mobile system or a system for transmitting or receiving information. The mobile system can be a PDA, portable computer, web tablet, wireless phone, mobile phone, digital music player or memory card. The controller 610 may execute a program and control the system 6000. Controller 610 may be, for example, a microprocessor, digital signal processor, microcontroller or similar device. The input / output device 620 may be used to input or output data of the system 6000. The system 6000 may be connected to an external device, such as a personal computer or a network, using the input / output device 630 to exchange data with the external device. The input / output device 620 may be, for example, a keypad, a keyboard, or a display device. The memory 630 may store code and / or data for the operation of the controller 610 and / or store data processed by the controller 610. The memory 630 may include a nonvolatile memory according to any one of embodiments of the present invention. The interface 640 may be a data transmission path between the system 6000 and another external device. The controller 610, the input / output device 620, the memory 630, and the interface 640 may communicate with each other via the bus 650. For example, such a system 6000 may be used in mobile phones, MP3 players, navigation, portable multimedia players (PMPs), solid state disks (SSDs), or consumer electronics.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope not departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

1 is a block diagram of a multi-layer nonvolatile memory according to an embodiment of the present invention.

2 is a layout diagram illustrating a portion of a memory cell array of a nonvolatile memory according to an embodiment of the present invention.

3 is a cross-sectional view of a nonvolatile memory in accordance with some embodiments of the present invention.

4A through 4C are cross-sectional views illustrating a method of manufacturing the nonvolatile memory of FIG. 3 for each process.

5 is a cross-sectional view of a nonvolatile memory in accordance with some embodiments of the present invention.

6 is a schematic diagram illustrating a memory card according to an embodiment of the present invention.

7 is a schematic diagram illustrating a system according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1, 2: memory layer, 100_1, 100_2: semiconductor layer

110_1, 110_2: source / drain regions, 120_1, 120_2: cell transistors

130_1, 130_2: select transistor, 160_1, 160_2, 170: interlayer insulating film

CSL_1, CSL_2: Common Source Line BC_1, BC_2: Bitline Plug

MC: metal contacts

Claims (12)

A lower memory layer including a lower active region and a plurality of lower gate structures; A plurality of lower contact portions electrically connected to the lower active region; An upper memory layer stacked on the lower memory layer and including an upper active region and a plurality of upper gate structures; And And a plurality of upper contact parts electrically connected to the upper active area. And a top of a portion of the plurality of upper contact portions is lower than a top of the plurality of upper gate structures. 2. The stacked nonvolatile memory as in claim 1, wherein a top of a portion of the plurality of bottom contact portions is equal to or lower than a top of the plurality of bottom gate structures. The nonvolatile memory of claim 1, wherein a portion of the plurality of lower contact portions extends to be connected to a portion of the plurality of upper contact portions. 2. The stacked nonvolatile memory of claim 1, wherein the plurality of lower and upper contact portions are a common source line (CSL) or a bit line contact plug. Providing a lower memory layer comprising a lower active region and a plurality of lower gate structures; Providing an upper memory layer on the lower memory layer, the upper memory layer including an upper active region and a plurality of upper gate structures; And And forming an upper contact portion electrically connected to the upper active region and having an upper contact portion that is equal to or lower than the uppermost portion of the upper gate structure. The method of claim 5, wherein the forming of the upper contact portion, Forming an upper contact hole exposing the upper active region; Filling the upper contact hole with a conductive material; And And removing a portion of the upper contact hole filled with the conductive material to form the upper contact portion having a top portion that is equal to or lower than the top of the upper gate structure. Method of manufacturing the device. The method of claim 6, wherein the removing of the partial region of the upper contact portion comprises: The method of claim 1, wherein the upper gate structure is used as an etching mask. The method of claim 5, wherein the providing of the lower memory layer comprises: Forming a lower contact hole exposing the lower active region; Filling the lower contact hole with a conductive material; And Removing the partial contact portion of the lower contact hole filled with the conductive material to form the lower contact portion having the uppermost portion that is equal to or lower than the uppermost portion of the lower gate structure; Method of manufacturing the device. The method of claim 8, wherein the removing of the partial region of the lower contact portion comprises: And manufacturing the lower gate structure as an etch mask. The method of claim 5, wherein providing the upper memory layer comprises: And wafer-bonding the lower memory layer and the upper memory layer. A memory comprising a nonvolatile memory device according to any one of claims 1 to 4; And And a controller for controlling the memory and exchanging data with the memory. A memory comprising the nonvolatile memory device according to any one of claims 1 to 4; A processor in communication with the memory via a bus; And And an input / output device in communication with the bus.

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