KR20100022226A - Method of operating a non volatile memory device - Google Patents

Abstract

The present invention relates to an operation of a nonvolatile memory device, wherein a program voltage is applied to a selected first word line and a first pass voltage is applied to other word lines while a program is performed for each word line. Checking the boosting level of the string connected to the program inhibiting bit line; When the boosting level is higher than a set level, applying a second pass voltage to at least one word line adjacent to a source selection line of the first word line, and re-checking the boosting level; And when the boosting level is lower than the set level, applying a third pass voltage to the second word line closest to the source selection line of the selected word line.

Description

Method of operating a non volatile memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the operation of a nonvolatile memory device, and more particularly, to a method of operating a nonvolatile memory device for word line voltage control for controlling self-boosting in a program operation.

There is an increasing demand for nonvolatile memory devices that can be electrically programmed and erased and that data can be stored without being erased even when power is not supplied. In order to develop a large-capacity memory device capable of storing a large number of data, high integration technology of memory cells has been developed. To this end, a NAND type flash memory device in which a plurality of memory cells are connected in series to form a string and a plurality of strings form a memory cell array has been proposed. .

In general, a flash memory cell includes a gate in which a tunnel insulating film, a floating gate, a dielectric film, and a control gate are stacked on a semiconductor substrate, and a junction region formed on the semiconductor substrate at both sides of the gate. It is programmed as it is injected and is erased as the injected electrons are discharged by FN tunneling.

1A is a cross-sectional view of a unit string of a flash memory device.

The unit string of the flash device includes a floating gate and a control gate between a drain select transistor (DST) for selecting a unit string and a source select transistor (SST) for selecting a ground. Memory cells MC0,..., MC31 having gates having a structure in which control gates are stacked are connected in series.

The string is connected to the bit line BL, and a plurality of structures in which the string and the bit line are connected are connected in parallel to form a block, and the block is symmetric about the bit line contact. Is deployed. The selection transistors DST and SST and the memory cells MC0 to MC31 are arranged in a matrix of rows and columns, and the gates of the drain selection transistor DST and the source selection transistor SST arranged in the same column are Respectively connected to a drain select line (DSL) and a source select line (SSL). In addition, the gates of the memory cells MC0 to MC31 arranged in the same column are connected to the corresponding plurality of word lines WL0 to WL31. A bit line BL is connected to the drain of the drain select transistor DST, and a common source line CSL is connected to the source of the source select transistor SST.

The program operation of the NAND flash memory device having the above-described structure is as follows.

Fowler-Nordheim (hereinafter referred to as "FN") is applied to the selected bit line by applying a voltage of 0V and a program voltage (Vpgm) to the selected word line. Tunneling injects electrons from the channel region into the floating gate to make the program.

However, the program voltage Vpgm may be applied not only to the selected memory cell but also to unselected memory cells arranged along the same word line so that the unselected memory cells connected to the same word line may be programmed. This phenomenon is called program disturb.

To prevent program disturb, the source of the drain select transistor (DST) of the string including the unselected memory cells connected to the selected word line and the unselected bit line is Vcc-Vth (Vcc is the power supply voltage, and Vth is the threshold of the drain select transistor. Boosts the channel voltage Vch of memory cells dependent on the same string by applying a program voltage Vpgm to a selected word line and applying a pass voltage Vpass to an unselected word line. This prevents unselected memory cells from being programmed.

That is, as shown in FIG. 1A, when the thirtieth word line is selected, the program voltage Vpgm is applied to the thirtieth word line WL29, the pass voltage Vpass is applied to the remaining word lines, and the drain selection transistor is applied. When the DST and the source select transistor SST are turned off, channel boosting occurs in the channel region of the string connected to the unselected bit line, and as shown in FIG. 1A, the channel voltage rises and is programmed. You can stop it. This requires effective channel boosting.

In addition, channel boosting is reduced when there are many programmed cells among memory cells constituting the string. To prevent this, a word line voltage may be provided as follows.

FIG. 1B is a diagram illustrating word line voltage provision according to an EASB method of a flash memory device.

Referring to FIG. 1B, an erase area self boosting (EASB) method for preventing a programmed cell from reducing boosting is performed. By turning off the line WL28 to form a low channel boosting region between the 0th to 29th wordlines WL0 to WL29, and forming a high channel boosting region between the 29th to 31st wordlines WL29 to WL31. Prohibit the program.

FIG. 1C is a partially enlarged view of FIG. 1B.

FIG. 1C is an enlarged view of the region 100 of FIG. 1B, in which the number of generated electrons is increased due to a GIDL (Gate Induced Drain Leakage) phenomenon generated when high channel boosting occurs, and a high potential difference is shown. It is shown that the distorted burn failure by hot electrons generated by the strong electron field caused by the difference may occur.

2 is a graph illustrating a relationship between a channel boosting level and a program disturbance.

When the channel boosting level is low, the FN tunneling program disturbance may occur, and when the channel boosting level is high, the program disturbance by hot electron injection may be generated in FIG. 2. Therefore, a method of adjusting the pass voltage Vpass applied to the word line for proper channel boosting may be used.

Accordingly, an object of the present invention is to operate an operation of a nonvolatile device in which a pass voltage applied to an adjacent word line is set differently according to a program state of memory cells adjacent to each word line during a program operation of the nonvolatile memory device. To provide a method.

Method of operating a nonvolatile memory device according to a feature of the present invention,

While performing the program for each word line, the program voltage is applied to the selected first word line, the first pass voltage is applied to other word lines, and the program is progressed. The boosting level of the string connected to the program inhibit bit line is adjusted. Confirming; When the boosting level is higher than a set level, applying a second pass voltage to at least one word line adjacent to a source selection line of the first word line, and re-checking the boosting level; And when the boosting level is lower than the set level, applying a third pass voltage to the second word line closest to the source selection line of the selected word line.

The second pass voltage is 1V or more and 3V or less.

The third pass voltage is greater than the second pass voltage and lower than the first pass voltage.

When the third word line adjacent to the drain select line in the first word line is in a program progress state, a pass voltage applied to the third word line is applied to the first pass voltage for a time set as a fourth pass voltage, and then the first word voltage is applied to the first pass voltage. It is characterized by changing.

For each word line, pass voltage information applied to adjacent word lines is stored to provide a pass voltage set for each word line in a subsequent program operation to perform a program.

Method of operating a nonvolatile memory device according to another aspect of the present invention,

Checking a program state of a second word line adjacent to a drain select line in the selected first word line according to a program command; And if the second word line is in the program state as a result of the checking, applying the first pass voltage for a predetermined time period, and then controlling the application of the second pass voltage to process the program.

The first pass voltage may be a voltage at which memory cells connected to the second word line may be turned on.

The first pass voltage is greater than the second pass voltage.

The set time is,

The self-boosting level is characterized in that it is time to increase to the set voltage level.

In the method of operating a nonvolatile memory device according to the present invention, a pass that can be applied to adjacent word lines to determine the degree to which each word line is boosted according to a program state of a neighboring cell through a test and to optimize the boosting level By setting the voltage in advance, it is possible to effectively boost the channel region of the cell at the time of program inhibition.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3A is a block diagram of a flash memory device.

The flash memory device 300 may include a memory cell array 3310, a page buffer unit 320, a Y decoder 330, an X decoder 340, a voltage providing unit 350, and a controller 360.

The memory cell array 310 includes a plurality of memory blocks, each memory block including a plurality of cell strings in which memory cells for data storage are connected in series, and each cell string is connected to a bit line BL. . In addition, the gates of the memory cells are connected to the word line WL in a direction orthogonal to the bit line.

The page buffer unit 320 includes a plurality of page buffers connected to the bit lines of the memory cell array 310. Each page buffer temporarily stores data to be programmed in the selected memory cell and then stores the data through the bit lines. The data stored in the memory cell is read and stored.

The Y decoder 330 provides an input / output path to the page buffer of the page buffer unit 320 according to the input address, and the X decoder 340 selects the word line of the memory cell array 310 according to the input address.

The voltage providing unit 350 generates an operating voltage to be provided to a word line connected by the X decoder 340 under the control of the controller 360, and the controller 360 outputs a control signal for controlling the operation. A located pass voltage is provided to one or more word lines among the word lines on the source select line side adjacent to the selected word line.

In the program operation of the nonvolatile memory device, a voltage is applied to the word line as follows.

FIG. 3B illustrates a portion of a circuit of the memory cell array of FIG. 3A, and FIG. 3C illustrates a cross-sectional view of a cell string.

3B and 3C, a cell string connected to a pair of bit lines BLn and BLn + 1 of a memory cell array 310 is illustrated. In the cell string, a plurality of memory cells are connected in series between a drain select transistor and a source select transistor.

In the cell string of the nonvolatile memory device 300 according to an embodiment of the present invention, 32 memory cells are connected to each other, and gates of each of the memory cells include first to 32nd word lines WL <0> to WL <31>. ) Is connected.

3C is a cross-sectional view of the cell string.

Referring to FIG. 3C, memory cells share a junction with neighboring memory cells. In one memory cell, the floating gate and the control gate are divided into insulating layers, and the drain select transistor DST and the source select transistor SST are not divided into the floating gate and the control gate.

The program operation for storing data in the nonvolatile memory device 300 of FIG. 3A is performed as follows.

As shown in FIG. 3B, one of the bit line BLn and the bit line BLn + 1 is selected for the program, and the unselected bit line causes the program inhibit. This is to solve the problem that a high voltage is applied to the word line selected for the program, so that the memory cells of the unselected bit lines can also be programmed at the same time.

To prevent program selection of unselected bit lines, a method of causing self boosting in a cell string is used.

The power supply voltage VCC is applied to the drain select line DSL and 0 V is applied to the source select line SSL for self-boosting. The precharge is performed by applying a power supply voltage VCC to the bit line.

After that, a program voltage Vpgm is applied to a word line selected for a program, and a pass voltage Vpass is applied to other word lines. The pass voltage Vpass is a voltage that allows the memory cell to be turned on.

When the program voltage Vpgm is applied to the selected word line, the voltage of the channel is simultaneously raised in the cell string. When the voltage of the channel increases to some extent, the drain select transistor DST connected to the unselected bit line is turned off due to the level difference between the voltage of the bit line and the channel voltage.

When the drain select transistor DST is turned off, the channel generated in the cell string is in a floating state. As the program voltage Vpgm applied to the selected word line is increased, the channel voltage is also increased, thereby causing the program voltage Vpgm and the channel voltage. The voltage difference between them becomes small. This prevents the memory cell connected to the selected word line from being programmed.

With the development of multi-level cells with more than two bits of data bits that can be programmed into memory cells, self-boosting has evolved into EASB (Erase Area Self Boosting). This is a word line selected according to the manner in which the program proceeds from the first word line WL <0> adjacent to the source select line SSL toward the 32nd word line WL <31> adjacent to the drain select line DSL. This is to solve the problem that self-boosting is insufficient because a memory cell of the source select line of P is programmed.

However, the method of the EASB does not sufficiently solve the problem of hot carrier injection (HCI) if the self boosting level is too high, and FN tunneling program disturbance if the self boosting level is low.

Therefore, in the program method according to the exemplary embodiment of the present invention, the pass voltage level applied to each word line is adjusted according to whether the self-boosting level of the memory cell is high or low.

To this end, in the embodiment of the present invention, the pass voltage setting process for each word line is performed in the manufacturing process of the nonvolatile memory device.

4 is a flowchart illustrating a method of operating a nonvolatile memory device according to a first embodiment of the present invention.

Referring to FIG. 4, first, a test of a nonvolatile memory device is performed on a wafer (S401). The test is to check the self-boosting level for each word line, and the boosting level generated according to the degree to which the peripheral word lines are programmed for each word line, and the peripheral pass voltage for creating a normal boosting level. You can check it. Since the above test process is a process that can be performed using test equipment of a general nonvolatile memory device, detailed description thereof will be omitted.

When the above test is performed, the boosting level for each word line is measured (S403). A pass voltage to be input to the surrounding word lines is set according to each boost level (S405).

That is, as mentioned above, when each word line is programmed according to the boosting level, a pass voltage level applied to an adjacent word line toward the SSL line is determined according to the boosting level. The determined pass voltage of each word line is stored in the controller 360 to be applied when the nonvolatile memory device is operated later.

The pass voltage is determined as follows.

When a program is selected by selecting the n + 1th word line WL <n>, a program voltage Vpgm is applied to the n + 1th word line WL <n>. A pass voltage Vpass is applied to the remaining word lines. Then measure the boost level. In this case, the boosting level is measured in a wafer test and can be measured using test equipment.

As a result of measuring the boosting level, if the boosting level is too high, it means that HCI is generated. Therefore, the voltage applied to the plurality of word lines including the nth word line WL <n-1> may be used as the first pass voltage Vpass1. Set to).

 In this state, once the boosting level is measured again, if the boosting level is too low, it means that the FN disturbance is generated. Therefore, the first pass of the voltage applied to the n-1 word line WL <n-2> is performed. The second pass voltage Vpass2 is applied to the nth word line WL <n-1> in the state in which the voltage Vpass1 is applied.

The first pass voltage Vpass1 is at a voltage level of about 1 to 3 V, and the second pass voltage Vpass2 is higher than the first pass voltage Vpass1 and lower than the pass voltage Vpass.

In the state selected to program each word line as described above, the controller 360 sets the first and second pass voltages to the pass voltages of adjacent word lines according to the boosting level of the cell string in which the program is prohibited. Save it.

Meanwhile, the n + 2 word line adjacent to the DSL line to the n + 1 word line WL <n> selected for the program with the pass voltages of the word lines set to prevent HCI and FN disturbance as described above. When cells connected to (WL <n + 1>) are in a program state, HCI or FN disturbance may not occur because the pass voltage Vpass is not turned on. To this end, the same pass voltage as the second embodiment is applied to the n + 2th word line WL <n + 1>.

5 is a diagram illustrating a voltage applied to a word line to explain a second embodiment of the present invention.

Referring to FIG. 5, a program voltage Vpgm is applied to an n + 1 word line WL <n selected for a program as in the first embodiment, and an nth word line WL <n-1 is applied. Is applied to the second pass voltage Vpass2. The first pass voltage Vpass1 is applied to the n-1th word line WL <n-2>.

In the second exemplary embodiment of the present invention, the third pass voltage Vpass3 is applied to the n + 1 word line WL <n> and the n + 2 word line WL <n + 1> adjacent to the DSL for a predetermined time. Is applied, and then pass voltage (Vpass) is applied. The pass voltage Vpass is applied to the remaining word lines.

As described above, when the third pass voltage Vpass3 is applied to the n + 2th word line WL <n + 1> for a predetermined time, the n + 2th word line WL <n + 1> is LSB programmed. Even when the threshold voltage is raised, the turn-on is sufficiently turned on, and the boosting channel is normally generated so that an error does not occur in the boosting operation.

The third pass voltage Vpass3 is higher than the pass voltage Vpass and is a voltage level at which the n + 2th word line WL <n + 1> is sufficiently turned on.

It is also possible to proceed with the program as follows.

6 is a flowchart illustrating a program operation method according to a third embodiment of the present invention.

Referring to FIG. 6, when a program command is input (S601), a program voltage Vpgm is applied to an n + 1 word line WL <n> selected for a program, and a pass voltage is applied to other word lines. Vpass) is applied.

At this time, before proceeding with the program, the state in which the program is progressed on the n + 2th word line WL <n + 1> is checked (S603). As described above, in the case where the nonvolatile memory device performs a random program (S605), the third pass voltage (i.e., the third pass voltage) is applied to the n + 2 word line WL <n + 1> for a predetermined time. Vpass3), and then change to the pass voltage (Vpass) (S607), the program proceeds (609).

In the program method using the reprogramming scheme, the n + 2th word line WL <n + 1> may be in a LSB (Least Significant Bit) program state. In this case, since the threshold voltages of the memory cells connected to the n + 2th word line WL <n + 1> are high, it may not be turned on by the pass voltage Vpass.

If the n + 2th word line WL <n + 1> is not in the LSB program state, the pass voltage Vpass is applied to all other word lines except the n + 1th word line WL <n>. Proceed to the program (S609).

As described above, according to the word line selected for the program, the pass voltage applied to the peripheral word line is adjusted so that the program prevention is normally performed.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A is a cross-sectional view of a unit string of a flash memory device.

FIG. 1B is a diagram illustrating word line voltage provision according to an EASB method of a flash memory device.

FIG. 1C is a partially enlarged view of FIG. 1B.

2 is a graph illustrating a relationship between a channel boosting level and a program disturbance.

3A is a block diagram of a flash memory device.

FIG. 3B illustrates a portion of a circuit of the memory cell array of FIG. 3A, and FIG. 3C illustrates a cross-sectional view of a cell string.

4 is a flowchart illustrating a method of operating a nonvolatile memory device according to a first embodiment of the present invention.

5 is a diagram illustrating a voltage applied to a word line to explain a second embodiment of the present invention.

* Brief description of the main parts of the drawings *

300: nonvolatile memory device 310: memory cell array

320: page buffer unit 330: Y decoder

340: X decoder 350: voltage providing unit

360 control

Claims (9)

While performing the program for each word line, the program voltage is applied to the selected first word line, the first pass voltage is applied to other word lines, and the program is progressed. The boosting level of the string connected to the program inhibit bit line is adjusted. Confirming; When the boosting level is higher than a set level, applying a second pass voltage to at least one word line adjacent to a source selection line of the first word line, and re-checking the boosting level; And If the boosting level is lower than a predetermined level, applying a third pass voltage to a second word line closest to a source selection line of the selected word line; Method of operating a nonvolatile memory device comprising a. The method of claim 1, And the second pass voltage is 1V or more and 3V or less. The method of claim 1, And wherein the third pass voltage is greater than the second pass voltage and lower than the first pass voltage. The method of claim 1, When the third word line adjacent to the drain select line to the first word line is in a program progress state, And applying a pass voltage applied to the third word line for a period of time set as a fourth pass voltage, and then changing the pass voltage to a first pass voltage. The method of claim 1, For each word line, the pass voltage information applied to adjacent word lines is stored to provide a pass voltage set for each word line in a subsequent program operation to perform a program. How it works. Checking a program state of a second word line adjacent to a drain select line in the selected first word line according to a program command; And When the second word line is in the program state as a result of the checking, applying the first pass voltage for a predetermined time and then controlling the application of the second pass voltage to proceed the program. Method of operating a nonvolatile memory device comprising a. The method of claim 6, The first pass voltage is a voltage at which memory cells connected to the second word line can be turned on. The method of claim 6, And wherein the first pass voltage is greater than the second pass voltage. The method of claim 6, The set time is, A method of operating a nonvolatile memory device, characterized in that it is time for the self boosting level to rise to a set voltage level.

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