KR20100104180A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent a SAC fail between a bit line and a storage node contact plug. CONSTITUTION: A second plug is lower than a first plug on the upper side of a semiconductor substrate(300). A first contact plug is formed on the first plug. The first plug is a landing plug(318) for a storage node contact. The second plug is a landing plug(314) for a bit line contact.

Description

Semiconductor device and method for manufacturing same {SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same that can prevent a short between the landing plug for the bit line contact and the storage node contact plug.

There is an increasing demand for the increase in capacity of semiconductor devices, but there is a limit in increasing chip size, which makes it difficult to increase the capacity of semiconductor devices. This is because, as the chip size is increased, the number of chips per wafer is reduced, which reduces the yield of semiconductor devices. Recently, in order to form a plurality of memory cells on one wafer, efforts have been made to reduce the cell area by changing the cell layout. As an example, a method of changing from an 8F2 layout to a 6F2 layout by tilting the active area has been proposed.

1 is a plan view illustrating a general semiconductor device having a 6F2 layout.

As shown in FIG. 1, a tilted active region A / R is defined in the semiconductor substrate 100, and two gate lines GL pass through one active region A / R. One bit line BL passes through the active region A / R between the two gate lines GL. Thus, storage node contact plugs are formed on the active area A / R outside the gate line GL, and bit line contact plugs are formed on the active area A / R between the gate lines GL. Is formed. That is, in the case of a semiconductor device having a 6F2 layout, both a storage node contact plug and a bitline contact plug may be disposed in one active area A / R, and thus more integrated than a semiconductor device having a conventional 8F2 layout. Is high.

FIG. 2 is a cross-sectional view of a semiconductor device for explaining the problems of the prior art, corresponding to line AA ′ of FIG. 1.

As shown in FIG. 2, the landing plug 106 for the bit line contact and the landing plug 104 for the storage node contact are formed on the semiconductor substrate 100, and the bit for the landing plug 106 for the bit line contact. The line contact plug 110 and the bit line BL are sequentially formed, and the storage node contact plug 114 is formed on the storage node contact landing plug 104. Reference numerals 105, 108, and 112 of FIG. 2 denote first, second, and third insulating films, respectively.

In the prior art, since the storage node contact plug 114 and the bitline contact plug 110 are arranged side by side, a short S1 is caused between the landing plug 106 for the bitline contact and the storage node contact plug 114. do. In addition, in the related art, the bit line BL hard mask is lost when the storage node contact plug 114 is formed, causing a SAC fail S2 between the bit line BL and the storage node contact plug 114. As a result, in the case of the above-described prior art, the characteristics and the reliability of the semiconductor element are reduced.

The present invention provides a semiconductor device capable of preventing a short between a landing plug for a bit line contact and a storage node contact plug, and a method of manufacturing the same.

In addition, the present invention provides a semiconductor device capable of preventing SAC failure between a bit line and a storage node contact plug, and a method of manufacturing the same.

In addition, the present invention provides a semiconductor device and a method of manufacturing the same that can improve the characteristics and reliability of the semiconductor device.

The semiconductor device according to the embodiment of the present invention includes a first plug formed on the semiconductor substrate, a second plug having a lower height than the first plug, and a first contact plug formed on the first plug.

The first and second plugs are formed on active regions of the semiconductor substrate.

The active region is defined by being tilted in the semiconductor substrate.

The first plug is a landing plug for storage node contact.

The second plug is a landing plug for bit line contact.

The second plug has a top CD smaller than the top CD of the first plug.

The first contact plug is a storage node contact plug.

And a second contact plug formed on the second plug and a conductive line formed on the second contact plug.

The second contact plug is a bit line contact plug.

The conductive line is a bit line.

In addition, the method of manufacturing a semiconductor device according to an embodiment of the present invention, forming a first plug and a second plug having a lower height than the first plug on the semiconductor substrate and a first contact on the first plug Forming a plug.

The first and second plugs are formed on an active region of a semiconductor substrate.

The active region is defined by being tilted in the semiconductor substrate.

The first plug is formed as a landing plug for storage node contact.

The second plug is formed as a landing plug for a bit line contact.

The second plug is formed to have a top CD smaller than the top CD of the first plug.

The forming of the first plug and the second plug may include forming an insulating film on the semiconductor substrate, forming a plurality of first plugs in the insulating film, and forming a bit line on the insulating film and the first plug. Forming a mask pattern exposing the first plug of the contact region, and etching an upper end portion of the first plug of the bit line contact region exposed by the mask pattern to form a second plug having a lower height than the first plug; Forming and removing the mask pattern.

And forming a capping film on the insulating film and the first plug after the forming of the first plug and before the forming of the mask pattern.

Etching the upper end of the first plug is performed by a plasma etching method.

When etching the upper end portion of the first plug, a portion of the thickness of the insulating layer exposed by the mask pattern is also etched.

The first contact plug is formed as a storage node contact plug.

After forming the first plug and the second plug, and before forming the first contact plug, forming a second contact plug on the second plug and conducting on the second contact plug. The method further includes forming a line.

The second contact plug is formed as a bit line contact plug.

The conductive line is formed of a bit line.

The present invention increases the distance between the storage node contact plug and the bit line contact landing plug formed on the storage node contact landing plug by forming the landing plug for the bit line contact at a lower height than the landing plug for the storage node contact. By doing so, it is possible to prevent a short between the landing plug for the bit line contact and the storage node contact plug.

The present invention also provides a bit line contact plug and a bit line which are sequentially formed on the bit line contact landing plug by forming the bit line contact landing plug to have a top surface CD smaller than the top CD of the storage node contact landing plug. CDs can be reduced, which prevents SAC failing between bitline and storage node contact plugs.

Therefore, the present invention can improve the characteristics and the reliability of the semiconductor device.

In an embodiment of the present invention, the upper end portion of the landing plug for bit line contact is selectively etched to form a landing plug for bit line contact having a height relatively lower than that of the storage node contact landing plug.

In this case, the distance between the storage node contact plug formed on the storage node contact landing plug and the bit line contact landing plug is increased, so that the present invention prevents a short between the bit line contact landing plug and the storage node contact plug. can do.

Further, in the embodiment of the present invention, as the upper end of the landing plug for bit line contact is selectively etched, the landing plug for bit line contact having a top CD smaller than the top CD of the landing node landing plug may be formed. Thus, the present invention can reduce the bit line contact plug and the CD of the bit line which are sequentially formed on the landing plug for the bit line contact, thereby preventing SAC failing between the bit line and the storage node contact plug.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a cross-sectional view for describing a semiconductor device according to example embodiments of the inventive concepts, corresponding to line AA ′ of FIG. 1.

As illustrated in FIG. 3, a tilted active region is defined in the semiconductor substrate 300, and a plurality of gate lines (not shown) are formed on the semiconductor substrate 300 in which the active region is defined. A first insulating layer 302 is formed on the semiconductor substrate 300 on which the gate line is formed, and a plurality of landing plugs 304 and 306 are formed in the first insulating layer 302. The landing plugs 304 and 306 are formed on the active region between the gate lines.

Here, the landing plug formed in the bit line contact region, that is, the landing plug 306 for the bit line contact is formed to have a lower height than the landing plug formed in the storage node contact region, that is, the landing plug 304 for the storage node contact. have. The bit line contact landing plug 306 is formed to have a top CD smaller than the top CD of the storage node contact landing plug 304.

A bit line contact plug 314 is formed on the bit line contact landing plug 306, and a bit line BL is formed on the bit line contact plug 314. The storage node contact plug 318 is formed on the landing node contact landing plug 304.

The semiconductor device according to the embodiment of the present invention includes a landing plug 306 for a bit line contact having a height lower than that of the landing plug 304 for a storage node contact, and as a result, the landing for the storage node contact. The distance between the storage node contact plug 318 and the bit line contact landing plug 306 formed on the plug 304 is increased to prevent shorting.

In addition, since the bit line contact landing plug 306 of the semiconductor device according to the embodiment has a top surface CD smaller than the top surface CD of the storage node contact landing plug 304, the landing plug for the bit line contact ( The CD of the bit line contact plug 314 and the bit line BL which are sequentially formed on 304 are also reduced, so that the SAC fail between the bit line BL and the storage node contact plug 318 is prevented.

4A to 4G are cross-sectional views illustrating processes of manufacturing a semiconductor device in accordance with an embodiment of the present invention, corresponding to line AA ′ of FIG. 1.

Referring to FIG. 4A, after forming a plurality of gate lines (not shown) on the semiconductor substrate 300 on which the tilted active regions are defined, the first insulating layer 302 is formed on the semiconductor substrate 300 on which the gate lines are formed. ). Next, the first insulating layer 302 is etched to form a plurality of holes H exposing portions of the active region between the gate lines. At this time, the hole (H) is formed to have a wider CD at the upper end due to the nature of the etching process.

Referring to FIG. 4B, landing plugs 304 and 306 are formed by filling a conductive film, such as a polysilicon film, in the hole H. Specifically, the landing plugs for storage node contacts 304 are formed on the active region portions outside the gate lines, and the landing plugs 306 for the bit line contacts are formed on the active region portions between the gate lines.

Referring to FIG. 4C, a capping layer 308 is formed on the landing plugs 304 and 306 and the first insulating layer 302 to prevent oxidation of the polysilicon layer. The capping film 308 is formed of, for example, an oxide film. Then, a mask pattern 310 is formed on the capping layer 308 to expose the upper portion of the landing plug 306 for the bit line contact.

Referring to FIG. 4D, the portion of the capping layer 308 exposed by the mask pattern 110 and the upper end of the bit line contact landing plug 306 below are etched. In this case, the upper portion of the bit line contact plug 306 may be etched using a plasma etching method, and the thickness of the portion of the first insulating layer 302 exposed by the mask pattern 310 may be together during the plasma etching. It may be etched.

As a result, the landing plug 306 for the bit line contact has a relatively lower height than the landing plug 304 for the storage node contact. Further, as the upper end of the bitline contact landing plug 306 having a wider width than the lower end is etched, the bitline contact landing plug 306 is smaller than the top CD of the storage node contact landing plug 304. Has a top CD.

Referring to FIG. 4E, the mask pattern is removed, and then a second insulating film 312 is formed on the etched capping film 308, the landing plug 306 for the bit line contact, and the first insulating film 302. Form. Next, a bit line contact plug 314 contacting the bit line contact landing plug 306 is formed in the second insulating layer 312.

Here, since the upper end portion of the bit line contact landing plug 306 is etched and the upper surface CD is reduced, the present invention provides a bit line contact plug formed on the bit line contact landing plug 306. The CD of 314 can also be formed to be reduced than before.

Referring to FIG. 4F, a conductive film is formed on the bit line contact plug 314 and the second insulating film 312. Subsequently, the conductive layer is patterned to form a bit line BL that contacts the bit line contact plug 314, and then the bit line (B) is formed on the resultant of the semiconductor substrate 300 on which the bit line BL is formed. The third insulating film 316 is formed to cover the BL.

The bit line BL extends in a direction perpendicular to the gate line and is disposed so as to pass one by one on the active region. Dog Bone). Here, since the CD of the bit line contact plug 314 is reduced than before, the CD of the bit line BL formed on the bit line contact plug 314 may also be reduced. Can be.

Referring to FIG. 4G, the third and second insulating layers 316 and 312) and the capping layer 308 are etched to form a storage node contact plug 318 that contacts the landing plug 304 for the storage node contact. .

Here, the bit line contact landing plug 306 is formed on the storage node contact landing plug 304 because the upper end thereof is etched to have a relatively lower height than the storage node contact landing plug 304. The distance between the storage node contact plug 318 and the landing plug 306 for bitline contacts is greater than the conventional case in which the bitline contact landing plug 304 and the storage node contact landing plug 306 are formed to have the same height. It is increased.

Therefore, in the embodiment of the present invention, short between the landing line 306 for the bit line contact and the storage node contact plug 318 may be prevented.

In addition, the bit line contact landing plug 306 has an upper surface CD which is reduced as compared to the conventional one as the upper end having a relatively wider width than the lower end is etched, and thus is formed on the bit line contact landing plug 306. The CD of the bit line BL is reduced. Accordingly, in the embodiment of the present invention, the SAC fail between the bit line BL and the storage node contact plug 318 caused by the loss of the hard mask of the bit line BL when the storage node contact plug 318 is etched. Can be prevented.

Therefore, in the embodiment of the present invention, a short between the landing plug 306 for the bit line contact and the storage node contact plug 318 may be prevented and a SAC fail between the bit line BL and the storage node contact plug 318 may be prevented. As a result, the characteristics and the reliability of the semiconductor device can be improved.

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete the manufacture of the semiconductor device according to the embodiment of the present invention.

Meanwhile, in the above-described embodiment of the present invention, a case in which a semiconductor device having a 6F2 layout is applied is illustrated and described. However, as another embodiment of the present invention, the semiconductor device having an 8F2 layout may also be applied. It is possible. Further, in the above-described embodiment of the present invention, the landing plug for the bit line contact is formed to have a relatively low height, but as another embodiment of the present invention, the landing plug for the storage node contact is formed to have a relatively low height. It is also possible.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1 is a plan view showing a general semiconductor device having a 6F2 layout.

FIG. 2 is a cross-sectional view of a semiconductor device for explaining the problems of the prior art, corresponding to line AA ′ in FIG. 1. FIG.

3 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention, corresponding to line AA ′ of FIG. 1.

4A to 4G are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention, corresponding to line AA ′ of FIG. 1.

Explanation of symbols on the main parts of the drawings

300: semiconductor substrate 302: first insulating film

H: Hall

304: Landing plug for storage node contact

306: Landing plug for bitline contacts

308: capping film 310: mask pattern

312: Second insulating film 314: Bit line contact plug

BL: bit line 316: third insulating film

318: storage node contact plug

Claims (24)

A first plug formed on the semiconductor substrate and a second plug having a lower height than the first plug; And A first contact plug formed on the first plug; Semiconductor device comprising a. The method of claim 1, And the first and second plugs are formed on an active region of a semiconductor substrate. The method of claim 2, And the active region is defined by being tilted in the semiconductor substrate. The method of claim 1, And the first plug is a landing plug for storage node contact. The method of claim 1, And the second plug is a landing plug for bit line contact. The method of claim 1, And the second plug has a top CD smaller than the top CD of the first plug. The method of claim 1, And the first contact plug is a storage node contact plug. The method of claim 1, A second contact plug formed on the second plug; And Conductive lines formed on the second contact plugs; A semiconductor device further comprising. The method of claim 8, And the second contact plug is a bit line contact plug. The method of claim 8, And the conductive line is a bit line. Forming a first plug on the semiconductor substrate and a second plug having a lower height than the first plug; And Forming a first contact plug on the first plug; Method of manufacturing a semiconductor device comprising a. The method of claim 11, The first and second plugs are formed on an active region of a semiconductor substrate. 13. The method of claim 12, And the active region is defined by being tilted in the semiconductor substrate. The method of claim 11, The first plug is a semiconductor device manufacturing method, characterized in that formed as a landing plug for the storage node contact. The method of claim 11, And the second plug is formed as a landing plug for bit line contact. The method of claim 11, And the second plug is formed to have an upper surface CD smaller than the upper surface CD of the first plug. The method of claim 11, Forming the first plug and the second plug, Forming an insulating film on the semiconductor substrate; Forming a plurality of first plugs in the insulating film; Forming a mask pattern on the insulating layer and the first plug to expose a first plug of a bit line contact region; Etching the upper end of the first plug of the bit line contact region exposed by the mask pattern to form a second plug having a height lower than that of the first plug; And Removing the mask pattern; Method of manufacturing a semiconductor device comprising a. The method of claim 17, After forming the first plug, and before forming the mask pattern, Forming a capping film on the insulating film and the first plug; Method of manufacturing a semiconductor device further comprising. The method of claim 17, The etching of the upper end of the first plug is a method of manufacturing a semiconductor device, characterized in that performed by the plasma etching method. The method of claim 17, When etching the upper end of the first plug, a portion of the insulating film portion exposed by the mask pattern is also etched, characterized in that the etching. The method of claim 11, The first contact plug may be formed as a storage node contact plug. The method of claim 1, After forming the first plug and the second plug, and before forming the first contact plug, Forming a second contact plug on the second plug; And Forming a conductive line on the second contact plug; Method of manufacturing a semiconductor device further comprising. The method of claim 22, And the second contact plug is formed as a bit line contact plug. The method of claim 22, And the conductive line is formed of a bit line.

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