KR20100111130A - Vertical type non volatile memory device and method for fabricating the same - Google Patents

Abstract

A substrate, a first select transistor layer formed in the substrate, an electrode layer formed by isolating the first select transistor layer by implanting oxygen ions on the first select transistor layer and repeatedly implanted with impurity ions, and separated by a spacer layer on the electrode layer. A blocking layer, a charge trap layer and a tunneling layer formed on the sidewalls of the through holes penetrating the second selection transistor layer, the first selection transistor layer, the spacer layer, and the electrode layer to selectively expose the first selection transistor layer, and a blocking layer. And a channel layer formed in the through-hole in which the charge trap layer and the tunneling layer are formed to share the channel in a direction perpendicular to the first selection transistor layer, the electrode layer, and the second selection transistor layer formed in the substrate.

Description

Vertical type nonvolatile memory device and method for fabricating the same

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly to a vertical nonvolatile memory device and a method of manufacturing the same.

The nonvolatile memory device is a memory device in which stored data is maintained even when the power is cut off. The nonvolatile memory device may be classified into a floating gate device (FG) and a charge trap device (CTD) according to a data storage method. In particular, in the field of nonvolatile memory devices, interest in charge trap devices having superior mutual interference and charge retention characteristics is increasing compared to floating gate devices. When the charge trapping device has a structure in which a tunneling layer, a charge trapping layer, a shielding layer, and a control gate electrode are sequentially stacked on a semiconductor substrate, a program-erase operation is repeatedly performed by a Fowler-Nordheim (FN) tunneling method. .

The development of nonvolatile memory devices is progressing to the development of devices having small size and high capacity. In particular, since the charge trap element traps electrons in the nitride film, there is an advantage that the stack height is lower than that of the polysilicon used in the floating gate element, which is considered as one of the next generation memory elements. In particular, the structure of the charge trap device is introducing new cell structures to increase the degree of integration of the device. For example, a method of forming channels in a vertical direction with a semiconductor substrate on a semiconductor substrate is being studied differently from a structure in which charge trap devices are sequentially stacked on a substrate.

However, the method of forming the channel on the semiconductor substrate in a direction perpendicular to the semiconductor substrate is relatively more complicated than the conventional process flow, and causes problems such as disturbance and reliability during program operation and erase operation. Accordingly, in the development of the charge trap element, there is a demand for the development of a charge trap element that can increase the program and erase windows without being more complicated than conventional processes.

Vertical nonvolatile memory device according to the invention, the substrate; A first select transistor layer formed in the substrate; An electrode layer which is repeatedly formed by being implanted with impurity ions isolated from the separation layer formed by implanting oxygen ions on the first selection transistor layer; A second selective transistor layer formed on the electrode layer by isolation from the spacer layer; A blocking layer, a charge trap layer, and a tunneling layer formed on sidewalls of the through-holes penetrating the first select transistor layer, the spacer layer, and the electrode layer, and selectively exposing the first select transistor layer; And a channel layer formed in the through hole in which the blocking layer, the charge trap layer, and the tunneling layer are formed, and sharing the channel in a direction perpendicular to the first selection transistor layer, the electrode layer, and the second selection transistor layer formed in the substrate. .

A hard mask oxide layer may be further formed on the substrate on which the channel layer is formed to separate the channel layer.

The first selective transistor layer and the second selective transistor layer may be formed of regions implanted with N-type impurity ions, and the electrode layer may be composed of regions implanted with P-type impurity ions.

Preferably, the channel layer comprises a polysilicon film.

A method of manufacturing a vertical nonvolatile memory device according to the present invention includes: implanting impurity ions into a substrate to form a first selection transistor layer; Repeatedly forming an electrode layer isolated by the separation layer by alternately implanting oxygen ions and impurity ions on the first selection transistor layer; Implanting impurity ions so as to be isolated from the electrode layer to form a second selection transistor layer; Selectively etching the electrode layers separated by the second selection transistor layer and the separation layer to form a through hole exposing the first selection transistor layer; Sequentially forming a blocking layer, a charge trap layer, and a tunneling layer on sidewalls of the through hole; And filling a through hole in which the blocking layer, the charge trap layer, and the terminating layer are formed to form a channel layer sharing a channel in a direction perpendicular to the first selection transistor layer, the electrode layer, and the second selection transistor layer. .

The forming of the first selection transistor layer and the second selection transistor layer is preferably performed by implanting N-type impurity ions.

The electrode layer is preferably formed by implanting P-type impurity ions.

After forming the second select transistor layer, the method may further include performing a thermal process for activating ions implanted in the substrate.

The through hole is preferably formed to have a radius of 20 to 50 nm.

The forming of the blocking layer, the charge trap layer and the tunneling layer may include forming a blocking material layer on the substrate on which the through hole is formed; Forming a blocking layer on the sidewall of the through-hole by performing a spacer etching process on the blocking material layer to remove the blocking material layer formed on the substrate and the bottom of the through-hole: forming a charge trap material layer on the substrate on which the blocking layer is formed step; Forming a charge trap layer on the blocking layer by removing the charge trap material layer formed on the substrate and at the bottom of the through hole by performing a spacer etching process on the charge trap material layer: a tunneling material on the substrate on which the charge trap layer is formed Forming a film; And forming a tunneling layer on the charge trap layer by performing a spacer etching process on the tunneling material layer to remove the tunneling material layer formed on the substrate and the bottom of the through hole.

The blocking material film is preferably formed including an alumina film or an oxide film.

The charge trap material film is preferably formed including a nitride film.

The tunneling material film is preferably formed including an oxide film.

The channel layer is preferably formed including a polysilicon film.

  After the forming of the channel layer, the method may further include forming a hard mask oxide layer separating the channel layer on the substrate on which the channel layer is formed.

Referring to FIG. 1, a vertical nonvolatile memory device according to the present invention may be spaced apart from a substrate 100, a first selection transistor layer 121 formed in the substrate 100, and a first selection transistor layer 121. The electrode layer 141 repeatedly stacked to be separated by the layer 131, the second selection transistor layer 151 formed on the electrode layer 141 separated by the spacer layer 131, and the second selection transistor layer 151. The blocking layer 190, the charge trap layer 200 and the tunneling layer 210 formed on the sidewalls of the through hole penetrating the insulating layer 131 and the electrode layer 141, and the through hole in which the tunneling layer 210 is formed It includes a channel layer 220 formed to be buried. The semiconductor device may further include an oxide film 230 formed on the semiconductor substrate 100 on which the channel layer 220 and the second select transistor layer 151 are formed so that the channel layer 220 is separated.

In this case, the electrode layer 141 and the second selection transistor layer 151 separated and repeatedly stacked by the first selection transistor layer 121 and the spacer layer 131 are vertically arranged in the substrate 100. The first select transistor layer 121 and the second select transistor layer 151 may be formed by implanting N-type impurity ions into the substrate 100. The spacer layer 131 may be formed by implanting oxygen ions into the substrate 100, and the electrode layer 141 may be formed by implanting P-type impurity ions into the substrate 100. The first select transistor layer 121 is used as a source select transistor, and the second select transistor layer 151 is used as a drain select transistor. The electrode layer 141 is used as a word line and is repeatedly stacked as many as the number of memory cells connected to the cell string. The electrode layer 141 and the spacer layer 131 may be formed to a thickness of 20 to 100 nm in consideration of ion implantation concentration and heat treatment. The diameter of the through hole may be formed to about 20 ~ 100nm. The blocking layer 190 may include an oxide film such as alumina to prevent charges trapped in the charge trap layer 200 from moving to the electrode layer 141 used as a word line. The charge trap layer 200 may include a nitride film, and the tunneling layer 210 may include an oxide film. The channel layer 220 shares the first selection transistor layer 121, the electrode layer 141 repeatedly stacked by the separation layer 131, and the second selection transistor layer 151 sequentially formed in the semiconductor substrate 100. And a bit line (not shown).

In the vertical nonvolatile memory device having such a structure, an erase operation of electrons trapped in the cell transistor is performed by hot carriers generated in the selection transistor. For example, when a high positive voltage is applied to the electrode layer used as the word line, the program operation is trapped at the trap site in the charge trap layer by the potential difference with the channel layer. On the other hand, in the erase operation, when a predetermined bias is formed between the select transistor and the word line by applying a predetermined voltage to the word line and the select transistor, an inversion layer is formed in the select transistor, and the channel layer is dipped. Hot hole is formed by breaking the pair of electron holes formed in the depletion region. At this time, the generated hot holes are removed by recombining with the electrons trapped in the charge trap layer of the word line while moving in the source direction.

As described above, the vertical nonvolatile memory device according to the present invention performs an ion implantation process in a substrate, whereby the selection transistors and word lines are arranged in a vertical direction by being separated by a spacer layer, and penetrating the selection transistors and word lines. The channel layer is arranged. Therefore, the memory device can be manufactured easily by simplifying the complicated process flow of the nonvolatile memory device, and the hot hole erase operation can be applied to greatly increase the program and erase window.

A method of manufacturing a vertical nonvolatile memory device having such a structure is as follows.

Referring to FIG. 2, a passivation film 110 is formed on the semiconductor substrate 100. The passivation film 110 may be formed including an oxide film. The passivation film 110 serves as a protective film to protect the surface of the semiconductor substrate 100 in the ion implantation process to be performed later to prevent damage to the semiconductor substrate.

Referring to FIG. 3, the first N-type impurity region 120 is formed by implanting N-type impurity ions into the semiconductor substrate 100. The first N-type impurity region 120 may be formed by implanting N-type impurity ions, for example, arsenic ions.

In order to form a word line region used as a cell transistor, oxygen ions and P-type impurity ions are alternately implanted a plurality of times on the first N-type impurity region 120 to form a plurality of oxygen ion regions 130 and P-type ion regions. 140 are alternately formed. Subsequently, N-type impurity ions are implanted into the oxygen ion region 130 to form the second N-type impurity region 150.

The oxygen ion region 130 may be formed by implanting oxygen ions, and the P-type ion region 140 may be formed by implanting P-type impurity ions, for example, boron ions. In this case, the oxygen ion region 130 and the P-type ion region 130 are alternately formed, but are separated from the first N-type impurity region 120 and are separated from each other by the second N-type impurity region 150. It is preferable to form the oxygen ion region 130. The second N-type impurity region 150 may be formed by implanting N-type impurity ions, for example, arsenic ions. At this time, the first N-type impurity region 120 is later changed into a source select transistor layer by a thermal process and used as a source select transistor, and the second N-type impurity region 150 is a drain select transistor layer after a thermal process. Is used as the drain select transistor.

The ions implanted into the semiconductor substrate 100 vary in the ion implantation depth (RP) value depending on the ion implantation energy. Therefore, the impurity regions to be sequentially formed in the semiconductor substrate may be formed by controlling the ion implantation energy during ion implantation.

Referring to FIG. 4, a thermal process is performed to activate ions implanted into the semiconductor substrate 100. Then, the first and second N-type impurity regions 120 and 150 are converted into the first select transistor layer 121 and the second select transistor layer 151, and the oxygen ion region 130 and the P-type ion region 140 are changed. Is converted into the spacer layer 131 and the electrode layer 141. The separation layer 131 serves to insulate the electrode layers 141 stacked multiple times from the first selection transistor layer 121 and the second selection transistor layer 151 so as to be insulated from each other. The electrode layer 141 is used as a word line constituting a memory cell of a cell string, and is a layer for applying a bias of a predetermined size so that charge can be trapped in a charge trap layer to be formed. Program and erase operations may be performed according to a bias applied to the electrode layer 141.

Referring to FIG. 5, after the passivation layer 110 is removed, an electrode layer 141 and a second selection transistor layer (I) repeatedly stacked and separated by the first selection transistor layer 121 and the separation layer 131 may be formed. A hard mask oxide film 160 is formed on the semiconductor substrate 100 on which the 151 is formed, and a resist film pattern 170 for selectively exposing the semiconductor substrate 100 is formed. The resist film pattern 170 is disposed so that the semiconductor substrate in the region where the channel is to be formed is selectively exposed.

Referring to FIG. 6, a hard mask oxide layer 161 is exposed by etching the resist layer pattern 170 as an etch mask to form a hard mask oxide layer pattern 161. Next, a portion of the semiconductor substrate 100 exposed by the hard mask film oxide layer pattern 161, for example, the second selection transistor layer 151 and the electrode layer 141 which are repeatedly separated and separated by the spacer layer 131, are sequentially stacked. Etching to form a through hole 180 to expose the first selection transistor layer 121 in the semiconductor substrate 100. At this time, the radius of the through hole 180 is formed to about 20 to 50 nm. The etching process for forming the through hole 180 may perform a wet process and a dry process. The first selection transistor layer 121 may be used as an etching end point, and the etching process may be terminated when the surface of the first selection transistor layer 121 is exposed.

Referring to FIG. 7, after removing the resist film pattern 170 by performing a strip process, blocking is performed to prevent charge from moving to the electrode layer 141 used as a word line on the sidewall of the through hole 180. Form layer 190. In this case, the blocking layer 190 is selectively formed only on the sidewall of the through hole 180 such that the lower first selection transistor layer 121 is selectively exposed. The blocking layer 190 may include an oxide film such as alumina, and may be formed to have a thickness of 8 to 15 nm.

Specifically, a blocking material film is formed on the semiconductor substrate 100 on which the through hole 180 is formed, and a spacer etch process is performed to form a top surface of the hard mask oxide layer pattern 161 and a bottom surface of the through hole 180. The blocking material film is etched. Then, the blocking material film on the bottom surface of the through hole 180 is etched to expose the first selection transistor layer 121, and the blocking layer 190 is selectively formed only on the sidewall of the through hole 180. The spacer etching process may be performed by an anisotropic etching process.

Referring to FIG. 8, the charge trap layer 200 is formed on the sidewall of the through hole 180 where the blocking layer 190 is formed. Specifically, a charge trap material film is formed on the semiconductor substrate 100 on which the blocking layer 190 is formed, and a spacer etching process is performed to form a charge trap formed on the top surface of the hard mask oxide pattern 161 and on the bottom surface of the through hole 180. Etch the material film. Then, the charge trap material layer on the bottom surface of the through hole 180 is etched to expose the first select transistor layer 121, and the charge trap layer 200 is formed only on the blocking layer 190 formed on the sidewall of the through hole 180. Is formed. The charge trap layer 200 may include a nitride film and may be formed to have a thickness of 3 to 10 nm. The charge trap layer 200 is used as a charge storage layer for storing charges passing through the tunneling layer 190 from the channel layer to be formed later, and the charges stored in the charge trap layer 200 are trapped in the charge trap layer 200. It is captured by the site and cannot be moved.

Referring to FIG. 9, the tunneling layer 210 is formed on the sidewall of the through hole 180 where the charge trap layer 200 is formed. Specifically, the tunneling material layer is formed on the semiconductor substrate 100 on which the charge trap layer 200 is formed, and the spacer etching process is performed to form the tunneling material on the top surface of the hard mask oxide layer pattern 161 and the bottom surface of the through hole 180. Etch the membrane. Then, the charge trap material layer on the bottom surface of the through hole 180 is etched to expose the first select transistor layer 121, and the tunneling layer 210 is formed only on the charge trap layer 200 formed on the sidewall of the through hole 180. Is formed. The tunneling layer 210 may include an oxide film and may have a thickness of 2 to 8 nm.

Referring to FIG. 10, the channel layer 220 filling the through hole 180 where the first selection transistor layer 121 is exposed is formed. The channel layer 220 may include a polysilicon layer doped with impurities. The channel layer 220 is used as a channel region in which the electrode layer 141 and the second selection transistor layer 151, which are separated by the first selection transistor layer 121 and the separation layer 131 and are repeatedly stacked, are shared.

Referring to FIG. 11, a planarization process is performed on the channel layer 220 to expose an upper surface of the second select transistor layer 151, and an oxide layer may be formed on the second select transistor layer 151 and the channel layer 220. 230 to form a channel layer 220 to be separated.

In this way, the ion implantation process is performed in the semiconductor substrate to sequentially stack the first selective transistor and the electrode layer which are repeatedly stacked on the separation layer, and the second selection transistor is sequentially stacked on the electrode layer, and repeatedly stacked by the first selection transistor and the separation layer. The electrode layer and the channel layer penetrating the second selection transistor in a vertical direction may be formed to form a vertical nonvolatile memory device that shares the channel region in the vertical direction. Therefore, the memory device can be easily manufactured by simplifying the complicated process flow of the nonvolatile memory device, and the hot hole erase operation can be applied to greatly increase the program and erase window.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

1 is a view illustrating a vertical flash memory device according to the present invention.

2 to 10 are views illustrating a method of manufacturing a vertical flash memory device according to the present invention.

Claims (14)

Board; A first select transistor layer formed in the substrate; An electrode layer which is repeatedly formed by being implanted with impurity ions isolated from the separation layer formed by implanting oxygen ions on the first selection transistor layer; A second selective transistor layer formed on the electrode layer by isolation from the spacer layer; A blocking layer, a charge trap layer, and a tunneling layer formed on sidewalls of the through-holes penetrating through the first selection transistor layer, the separation layer, and the electrode layer, and selectively exposing the first selection transistor layer; And A vertical layer including a channel layer formed in the through-hole in which the blocking layer, the charge trap layer, and the tunneling layer are formed, and sharing the channel in a direction perpendicular to the first selection transistor layer, the electrode layer, and the second selection transistor layer formed in the substrate; Type nonvolatile memory device. The method of claim 1, And a hard mask oxide layer formed on the substrate on which the channel layer is formed to separate the channel layer. The method of claim 1, And the first selection transistor layer and the second selection transistor layer are formed of regions implanted with N-type impurity ions, and the electrode layer is composed of regions implanted with P-type impurity ions. The method of claim 1, And the channel layer comprises a polysilicon layer. Implanting impurity ions into the substrate to form a first selection transistor layer; Repeatedly forming an electrode layer isolated by the separation layer by alternately implanting oxygen ions and impurity ions on the first selection transistor layer; Implanting impurity ions to be isolated from the electrode layer to form a second select transistor layer; Selectively etching the electrode layers separated by the second selection transistor layer and the separation layer to form a through hole exposing the first selection transistor layer; Sequentially forming a blocking layer, a charge trap layer, and a tunneling layer on sidewalls of the through hole; And Filling a through hole in which the blocking layer, the charge trap layer, and the terminating layer are formed to form a channel layer sharing a channel in a direction perpendicular to the first selection transistor layer, the electrode layer, and the second selection transistor layer; Method of manufacturing a nonvolatile memory device. The method of claim 5, The forming of the first selection transistor layer and the second selection transistor layer may be performed by implanting N-type impurity ions. The method of claim 5, And the electrode layer is formed by implanting P-type impurity ions. The method of claim 5, And forming a thermal process for activating ions implanted in the substrate after forming the second select transistor layer. The method of claim 5, Forming the blocking layer, the charge trap layer and the tunneling layer, Forming a blocking material film on the substrate on which the through hole is formed; Performing a spacer etching process on the blocking material film to remove the blocking material film formed on the substrate and the bottom of the through hole to form a blocking layer on the sidewall of the through hole; Forming a charge trap material film on the substrate on which the blocking layer is formed; Forming a charge trap layer on the blocking layer by performing a spacer etching process on the charge trap material layer to remove the charge trap material layer formed on the substrate and at the bottom of the through hole; Forming a tunneling material film on the substrate on which the charge trap layer is formed; And And forming a tunneling layer on the charge trap layer by removing the tunneling material layer formed on the substrate and the bottom of the through hole by performing a spacer etching process on the tunneling material layer. 10. The method of claim 9, The blocking material layer may include an alumina layer or an oxide layer. 10. The method of claim 9, And the charge trap material film is formed of a nitride film. 10. The method of claim 9, The tunneling material layer may include an oxide layer. The method of claim 5, And the channel layer comprises a polysilicon layer. The method of claim 5, After forming the channel layer, And forming a hard mask oxide layer separating the channel layer on the substrate on which the channel layer is formed.

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