KR20100123269A - LCD Display - Google Patents

Abstract

The present invention relates to a liquid crystal display device, comprising: a liquid crystal display panel; A plurality of source drive ICs converting digital video data into a data voltage in response to a data control signal and supplying the digital voltage to data lines of the liquid crystal display panel; A gate driving circuit sequentially supplying gate pulses to gate lines of the liquid crystal display panel in response to a gate control signal; A printed circuit board connected to the source drive ICs; And a timing controller mounted on the printed circuit board to generate the data control signal and the gate control signal.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device.

The liquid crystal display of the active matrix driving method displays a moving image using a thin film transistor (hereinafter referred to as TFT) as a switching element. The liquid crystal display device can be miniaturized compared to a cathode ray tube (CRT), which is applied to a display device in a portable information device, an office device, a computer, and a TV, and is rapidly replacing a cathode ray tube.

The liquid crystal display includes a liquid crystal display panel, a backlight unit for irradiating light to the liquid crystal display panel, a source drive integrated circuit (IC) for supplying data voltages to data lines of the liquid crystal display panel, and a gate line of the liquid crystal display panel. Gate drive ICs for supplying gate pulses (or scan pulses) to the light sources (or scan lines), control circuits for controlling the ICs, light source driving circuits for driving the light source of the backlight unit, and driving of the liquid crystal display panel And a DC-DC conversion circuit for generating voltages and voltages required for driving the driving circuit and the control circuit. A liquid crystal display panel, a backlight unit, and printed circuit boards (PCBs) on which the driving circuits and the control circuits are mounted are liquid crystal modules using case members in a module assembly process of the liquid crystal display device. crystal module (LCM). The PCB of the liquid crystal module is connected to the system board by a set maker.

In order to eliminate the PCB of the liquid crystal module or to reduce the circuit components mounted on the PCB, research is being conducted into the system integration development of adding a control circuit for controlling the liquid crystal module in the system board manufactured by the set maker. However, when the driving method of the liquid crystal module is changed, an expensive system board must be changed accordingly. Changes to these system boards will incur a lot of development time and costs. Accordingly, there is a demand for a method capable of coping with a liquid crystal module without changing the system board when the circuit and PCB of the liquid crystal module are reduced in response to the system integration environment and the driving method of the liquid crystal module is changed.

An object of the present invention is to solve the problems of the prior art to provide a liquid crystal display device to minimize the circuit and PCB of the liquid crystal module and to easily change the driving method of the liquid crystal module to be suitable for system integration.

In order to achieve the above object, the liquid crystal display device according to an embodiment of the present invention comprises a liquid crystal display panel; A plurality of source drive ICs converting digital video data into a data voltage in response to a data control signal and supplying the digital voltage to data lines of the liquid crystal display panel; A gate driving circuit sequentially supplying gate pulses to gate lines of the liquid crystal display panel in response to a gate control signal; A printed circuit board connected to the source drive ICs; And a timing controller mounted on the printed circuit board to generate the data control signal and the gate control signal.

The digital video data is generated from an external system board connected through a connector of the printed circuit board and transmitted directly from the external system board to the source drive ICs.

The present invention incorporates a data processing and data transmission circuit portion in an external system board, and a timing controller including only a circuit for generating a data control signal and a gate control signal on a PCB of the liquid crystal module. As a result, the present invention can cope with a change in the driving method of the liquid crystal module in the liquid crystal module by implementing a circuit arrangement advantageous for system integration and changing only the output of the timing controller without having to redesign the system board.

A method of manufacturing a liquid crystal module according to an embodiment of the present invention includes a substrate cleaning, a substrate patterning process, an alignment film forming / rubbing process, a substrate bonding and liquid crystal dropping process, a driving circuit mounting process, a module assembly process, and the like of the liquid crystal display panel. .

The substrate cleaning process removes contaminants on the upper and lower glass substrate surfaces of the liquid crystal display panel with the cleaning liquid. The substrate patterning process is to form and pattern various thin film materials such as signal wiring, thin film transistor (TFT), and pixel electrode including data lines and gate lines on the lower glass substrate, and a black matrix on the upper glass substrate. And forming and patterning various thin film materials such as color filters and common electrodes. In the alignment film forming / rubbing process, an alignment film is coated on glass substrates and the alignment film is rubbed or rubbed with a rubbing cloth. Through such a series of processes, the lower glass substrate of the liquid crystal display panel includes data lines to which a video data voltage is supplied, gate lines and data lines that intersect the data lines and are sequentially supplied with scan signals, that is, gate pulses. A pixel array including TFTs formed at intersections of gate lines, pixel electrodes of a liquid crystal cell connected to 1: 1 with TFTs, a storage capacitor, and the like are formed. The shift register of the gate driving circuit that generates the scan signal may be formed simultaneously with the pixel and the TFT array in the substrate patterning process. A black matrix, a color filter, and a common electrode are formed on the upper glass substrate of the liquid crystal display panel. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. The driving method is formed on the lower glass substrate together with the pixel electrode. A polarizing plate and a polarizing plate protective film are attached to each of the upper and lower glass substrates.

In the substrate bonding and liquid crystal dropping process, a sealant is drawn on one of the upper and lower glass substrates of the liquid crystal display panel and the liquid crystal is dropped onto the other substrate in the vacuum chamber. For example, when the liquid crystal is dropped on the lower glass substrate, an ultraviolet curable sealant is formed on the upper glass substrate in the vacuum chamber, the upper glass substrate on which the sealant is formed is inverted and fixed to the upper stage, and the liquid crystal is dropped. The lower glass substrate is fixed to the lower stage. Subsequently, in the substrate bonding and liquid crystal dropping process, after the upper glass substrate and the lower glass substrate are aligned, the pressure is applied to any one of the upper and lower glass substrates while the vacuum pump is driven to adjust the pressure of the vacuum chamber to a predetermined vacuum pressure. The upper glass substrate and the lower glass substrate are attached to each other by the addition. At this time, the cell gap of the liquid crystal layer is set larger than the cell gap of the design value. Subsequently, when nitrogen (N ₂ ) is introduced into the vacuum chamber to adjust the pressure of the vacuum chamber to atmospheric pressure, the cell gap of the liquid crystal display panel is adjusted to the cell gap of the designed value by the pressure difference between the bonded glass substrates and the vacuum chamber. When the ultraviolet light source is irradiated to the ultraviolet curable sealant through the upper glass substrate or the lower glass substrate of the liquid crystal display panel with the cell gap adjusted to the designed value, the sealant is cured.

The driving circuit mounting process mounts the source drive ICs on the lower glass substrate of the liquid crystal panel using a chip on glass (COG) process or a tape automated bonding (TAB) process. Source drive ICs are directly bonded to the lower glass substrate of the liquid crystal display panel in the COG process and connected to the data lines. In the TAB process, a tape carrier package (TCP) in which a source drive IC is mounted is bonded to a lower glass substrate of a liquid crystal display panel and connected to data lines. The source drive ICs are connected to the PCB via TCP or a flexible printed circuit board as shown in FIGS. 2 to 10. The flexible circuit board may be selected from a flexible printed circuit board (FPC) and a flexible flat cable (FFC). 2 and 7, the gate drive ICs may be directly formed on the lower glass substrate of the liquid crystal display panel and connected to the gate lines through a gate in panel (GIP) process as shown in FIGS. 2 and 7. In the TAB process, gate drive ICs may be attached to the lower glass substrate and connected to the gate lines.

In the module assembly process, the light source of the backlight unit is connected to the light source driving circuit, and the backlight unit and the liquid crystal display panel are assembled into the liquid crystal module using case members such as a guide panel, a bottom cover, and a top case.

The manufacturing method of the liquid crystal display according to the exemplary embodiment of the present invention may further include an inspection process and a repayment process.

The inspection process includes inspection of integrated circuits, signal wiring of data lines and gate lines formed on the lower glass substrate, electrical inspection for detecting defects of TFTs and pixel electrodes, electrical inspection performed after substrate bonding and liquid crystal dropping, and liquid crystal modules. Lighting of the backlight unit to detect a failure of the liquid crystal module. The repair process repairs signal wiring defects and TFT defects that are determined to be repairable by the inspection process.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 1 to 10.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10, a backlight unit 16 disposed below the liquid crystal display panel 10, and data lines of the liquid crystal display panel 10. Data driving circuit 12 connected to gates D1 to Dm, gate driving circuit 13 connected to gate lines G1 to Gn of liquid crystal display panel 10, data driving circuit 12 and gate driving circuit A timing controller 11 for controlling the furnace 13 and a DC-DC converter 15 for generating a driving voltage of the liquid crystal display panel 10 are provided.

The liquid crystal display panel 10 includes an upper glass substrate and a lower glass substrate facing each other with a liquid crystal layer interposed therebetween. The liquid crystal display panel 10 includes a pixel array for displaying video data. In the lower glass substrate, the TFT array includes TFTs formed at intersections of the data lines D1 to Dm and the gate lines G1 to Gn, and a pixel electrode connected to the TFTs. Each of the liquid crystal cells of the pixel array is driven by the voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied to transmit light incident from the backlight unit. Adjust the amount to display an image of the video data.

A black matrix, a color filter, and a common electrode are formed on the upper glass substrate of the liquid crystal display panel 10. The common electrode 2 is formed on the upper glass substrate in the vertical electric field driving method such as TN mode and VA mode, and on the lower glass substrate together with the pixel electrode 1 in the horizontal electric field driving method such as IPS mode and FFS mode. Is formed.

A polarizing plate is attached to each of the upper and lower glass substrates of the liquid crystal display panel 10, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The liquid crystal mode of the liquid crystal display panel 10 applicable to the present invention may be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. In addition, the liquid crystal display of the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display. In the transmissive liquid crystal display device and the transflective liquid crystal display device, the backlight unit 16 is required. The backlight unit 16 may be implemented as a direct type backlight unit or an edge type backlight unit.

The data driver circuit 12 includes a plurality of source drive ICs. Each of the source drive ICs samples, latches, and converts the digital video data RGB input from the system board 14 in response to the data control signal SDC from the timing controller 11 and converts the data into data of a parallel data system. Each of the source drive ICs converts digital video data (RGB) converted to a parallel data transmission scheme using analog / gamma reference voltages V _GMAO1 to V _GMAO10 from the DC-DC converter 15. It converts to a compensation voltage to generate a positive / negative analog video data voltage to be charged in the liquid crystal cells. Each of the source drive ICs supplies the data voltages to the data lines D1 to Dm while inverting the polarity of the positive / negative analog video data voltage under the control of the timing controller 11. Each of the source drive ICs may be connected to the data lines D1 to Dm by a COG process or a TAB process.

The gate driving circuit 13 includes a plurality of gate drive ICs. The gate drive IC sequentially supplies gate pulses (or scan pulses) to the gate lines, including a shift register that sequentially shifts the gate driving voltage in response to the gate control signal GDC from the timing controller 11. . Gate drive ICs may be connected to the gate lines of the lower glass substrate by the TAB process or directly formed on the lower glass substrate by the GIP process.

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal Data Enable, DE, and a dot clock CLK from the system board 14. The timing controller 11 uses a timing signal (Vsync, Hsync, DE, CLK) to control a data control signal (SDC) for controlling the operation timing of the source drive ICs and a gate control for controlling the operation timing of the gate drive ICs. Generate signal GDC. The timing controller 11 is connected to a gate control signal so that digital video data input at a frame frequency of 60 Hz can be reproduced in a pixel array of the liquid crystal display panel 10 at a frame frequency of 60 x i (i is a positive integer) Hz. The frequency of the data control signal can be multiplied by 60 x i Hz.

The data control signal SDC includes a source start pulse (SSP), a source sampling clock (SSC), a source output enable signal (SOE), a polarity control signal (POL), and the like. It includes. The source start pulse SSP controls the data sampling start time of the data driving circuit 12. The source sampling clock SSC is a clock signal that controls the sampling operation of data in the source drive ICs based on the rising or falling edge. If the digital video data (RGB) input to the source drive ICs is transmitted using the mini Low Voltage Differential Signaling (LVDS) interface specification, then the source start ICs (SSP) and the source sampling clock (SSC) are input to the source drive ICs. There is no need to do it. The polarity control signal POL inverts the polarity of the data voltage output from the data driving circuit 12 in a period of N (N is a positive integer) horizontal period. The source output enable signal SOE controls the output timing of the data driver circuit. Each of the source drive ICs has a charge share voltage or a common voltage Vcom in response to a pulse of the source output enable signal SOE when the polarity of the data voltage supplied to the data lines D1 to Dm is changed. ) Is supplied to the data lines D1 to Dm, and a data voltage is supplied to the data lines during the low logic period of the source output enable signal SOE. The charge share voltage is an average voltage of neighboring data lines to which data voltages having opposite polarities are supplied.

The gate control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP controls the timing of the first gate pulse. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate driving circuit 13.

The system board 14 includes a mini LVDS transmitter circuit converting digital video data input from a broadcast receiver circuit or an external video source into a signal of a mini LVDS interface standard and transmitting the signal to the source drive ICs. In addition, the system board 14 transmits timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a dot clock CLK through a LVDS interface or a TMDS interface transmission circuit. (11). The system board 14 includes a graphics processing circuit such as a scaler that interpolates the resolution of the RGB video data input from the broadcast receiving circuit or an external video source according to the resolution of the liquid crystal display panel and performs signal interpolation, and a DC-DC converter 15. It includes a power supply circuit for generating a voltage (Vin) to be supplied to.

The DC-DC converter 15 adjusts the voltage Vin input from the power supply of the system board 14 to generate driving voltages of the liquid crystal display panel 10. The driving voltages of the liquid crystal display panel 10 include a high potential power supply voltage Vdd between 15 V and 20 V, a logic power supply voltage Vcc of about 3.3 V, a gate high voltage V _{GH of} 15 V or more, and a gate low of −3 V or less. voltage (V _GL), 7V ~ common voltage (Vcom), the positive / negative polarity of the gamma reference voltages (V _GMA1 ~V _GMA10), core power voltage (core power voltage) between about 1.2V ~ 1.8V between 8V It includes.

The liquid crystal module of the present invention is manufactured by a module maker, and the liquid crystal display panel 10, the backlight unit 16, the timing controller 11, the data driving circuit 12, the gate driving circuit 13 and the direct current- are shown in FIG. DC converter 15 is included. The timing controller 11, the data driving circuit 12, and the DC-DC converter 15 are mounted on the PCB of the liquid crystal module shown in FIGS. 2 to 10. The DC-DC converter 15 is embedded in the system board 14 manufactured by the set maker, and may be omitted on the PCB of the liquid crystal module.

Conventional timing controllers include data processing circuits such as a memory for storing data, a data alignment circuit, and an interface circuit for transmitting data, together with a logic circuit for generating a data control signal SDC and a gate control signal GDC. Included. In contrast, in the present invention, the data processing circuit is mounted in the system board 14 so as to be suitable for system integration, whereas the timing of the liquid crystal module is based only on a logic circuit that generates the data control signal SDC and the gate control signal GDC. The controller 11 is configured. The driving method of the liquid crystal module may vary according to the change of the pixel array structure of the liquid crystal display panel or the data input to the source drive ICs. The module maker can change the driving method of the liquid crystal module only by changing the timing controller of the liquid crystal module. Therefore, when a change in the driving method of the liquid crystal module is required, the present invention can change the driving method of the liquid crystal module by changing only the output of the timing controller composed of the minimum logic circuit without redesigning the system board 14.

2 and 3 illustrate a liquid crystal module according to a first embodiment of the present invention.

2 and 3, the liquid crystal module of the present invention may be connected to the data lines of the liquid crystal display panel 10, the backlight unit 16 disposed below the liquid crystal display panel 10, and the liquid crystal display panel 10. The first and second PCBs 31A and 31B connected to the source drive ICs SD_IC, the gate driving circuit 13 connected to the gate lines of the liquid crystal display panel 10, and the source drive ICs SD_IC. Equipped. The first and second PCBs 31A and 31B may be disposed on the side of the liquid crystal module or the back of the liquid crystal module.

As the resolution of the LCD increases and the area becomes larger, the LCD 10 increases, and the number of data lines and source drive ICs SD_IC in the pixel array increase. As a result, as the resolution of the liquid crystal display increases and the area becomes larger, the PCB connected to the source drive ICs also increases. PCB sizes that can be processed by automated mounting devices such as Surface Mount Technology (SMT) equipment are fixed. Therefore, when a PCB larger than the PCB size that can be handled by an automated mounting apparatus such as surface mount technology (SMT) equipment is required, it is desirable to divide the PCB as shown in FIGS. 2 and 3 so as not to develop a new SMT equipment. .

The first PCB 31A is connected to the system board 14 through the first connector 32A, and is connected to the source drive ICs SD_IC of the first group. The timing controller 11 is mounted on the first PCB 31A. The first group of source drive ICs SD_IC are connected to the first PCB 31A through TCP or a flexible circuit board and to data lines existing in the left half of the pixel array.

The second PCB 31B is connected to the system board 14 through the first connector 32B, and is connected to the source drive ICs SD_IC of the second group. The second group of source drive ICs SD_IC are connected to the second PCB 31B through TCP or a flexible circuit board and to data lines existing in the right half of the pixel array.

The first PCB 31A is connected to the second PCB 31B through the connectors 33A and 33B and the FFC as shown in FIGS. 4A and 4B. The first PCB 31A may be connected to the second PCB 31B via LOG (Line On Glass) wires formed on the lower glass substrate of the liquid crystal display panel 10.

4A and 4B, the timing controller 11 is mounted on the first PCB 31A and is a timing signal input from the system board 14 through the first connector 32A of the first PCB 31A. Generate a data control signal SDC for controlling the source drive ICs SD_IC and a gate control signal GDC for controlling the gate driving circuit 13 based on the fields Vsync, Hsync, DE, and CLK. . The data control signal SDC is supplied to the source drive ICs SD_IC connected to the first PCB 31A through data control signal bus lines formed on the first PCB 31A. The data control signal SDC includes data control signal bus wires formed on the first PCB 31A, the second connector 33A of the first PCB 31A, the FFC, and the second connector of the second PCB 31B ( 33B) and data control signal bus lines formed on the second PCB 31B are transferred to the second PCB 31B and supplied to the source drive ICs SD_IC connected to the second PCB 31B. The data control signal SDC includes data control signal bus wires formed on the first PCB 31A, LOG wires for transferring data control signals formed on the lower glass substrate of the liquid crystal display panel 10, and the second PCB 31B. ) May be transferred to the second PCB 31B via the data control signal bus lines formed on the N-th bus and supplied to the source drive ICs SD_IC connected to the second PCB 31B. The carry signal of the sampling clock generated from the last source drive IC which samples data last among the first group of source drive ICs is a carry transfer wiring formed on the first PCB 31A, the second of the first PCB 31A. Data is first received from the second group of source drive ICs via the connector 33A, the FFC, the second connector 33B of the second PCB 31B, and the carry transfer wiring formed on the second PCB 31B. Supply to the first source drive IC to sample. The gate control signal GDC includes gate control signal bus wires formed on the first PCB 31A, TCP wires on which the source drive IC is mounted, and LOG wires for gate control signal transfer formed on the liquid crystal display panel 10. These are supplied to the gate driving circuit 13 through.

The first group of source drive ICs SD_IC receive the digital video data RGB _LEFT input from the system board 14 from the timing controller 11 via the first connector 32A of the first PCB 31A. To a positive / negative analog data voltage in accordance with the data control signal SDC. The positive / negative analog data voltages output from the first group of source drive ICs SD_IC are supplied to data lines existing in the left half of the pixel array.

The second group of source drive ICs SD_IC receive the digital video data RGB _RIGHT input from the system board 14 via the first connector 32B of the second PCB 31B to the first and second PCBs. Conversion is performed to the positive / negative analog data voltage in accordance with the data control signal SDC from the timing controller 11 input via the 31A and 31B. The positive / negative analog data voltages output from the second group of source drive ICs SD_IC are supplied to data lines existing in the right half of the pixel array.

When the driving method of the liquid crystal module shown in FIGS. 2 to 4B is necessary, only the data control signal SDC and the gate control signal GDC output from the timing controller 11 are changed to cope with the change of the driving method. Can be. FIG. 5 is an example of timing control signals Vsync, Hsync, and DE input to the timing controller 11, and FIG. 6 illustrates a data control signal SDC and a gate output from the timing controller 11 in a mini LVDS interface method. An example of the control signal GDC is shown.

7 and 8 illustrate a liquid crystal module according to a second embodiment of the present invention.

Referring to FIGS. 7 and 8, the liquid crystal module of the present invention may be applied to the data lines of the liquid crystal display panel 10, the backlight unit 16 disposed below the liquid crystal display panel 10, and the liquid crystal display panel 10. The first and second PCBs 31A and 31B connected to the source drive ICs SD_IC, the gate driving circuit 13 connected to the gate lines of the liquid crystal display panel 10, and the source drive ICs SD_IC. Equipped. The first and second PCBs 31A and 31B may be disposed on the side surface of the liquid crystal module or the rear surface of the liquid crystal module.

The first PCB 31A is connected to the system board 14 through the first connector 32A, and is connected to the source drive ICs SD_IC of the first group. The first timing controller 11A is mounted on the first PCB 31A. The first group of source drive ICs SD_IC are connected to the first PCB 31A through TCP or a flexible circuit board and to data lines existing in the left half of the pixel array.

The second PCB 31B is connected to the system board 14 through the first connector 32B, and is connected to the source drive ICs SD_IC of the second group. The second timing controller 11B is mounted on the second PCB 31B. The second group of source drive ICs SD_IC are connected to the second PCB 31B through TCP or a flexible circuit board and to data lines existing in the right half of the pixel array.

FIG. 9 is a plan view showing in detail the first PCB 31A shown in FIGS. 7 and 8. FIG. 10 is a plan view showing in detail the second PCB 31B shown in FIGS. 7 and 8.

Referring to FIG. 9, the first timing controller 11A is mounted on the first PCB 31A to receive timing signals input from the system board 14 through the first connector 32A of the first PCB 31A. The first data control signal SD _LEFT for controlling the first group of source drive ICs SD_IC and the gate control signal for controlling the gate driving circuit 13 based on (Vsync, Hsync, DE, CLK). (GDC) occurs. It is supplied to the first data control signal (SDC _LEFT) is the first PCB (31A) of the source drive IC of the first group are connected to claim 1 PCB (31A) via a data bus control signal wiring formed on the (SD_IC). The gate control signal GDC includes gate control signal bus wires formed on the first PCB 31A, TCP wires on which the source drive IC is mounted, and LOG wires for gate control signal transfer formed on the liquid crystal display panel 10. It is supplied to the gate driving circuit 13 through. The first group of source drive ICs SD_IC receive the digital video data RGB _LEFT input from the system board 14 via the first connector 32A of the first PCB 31A to the first timing controller 11A. Is converted into a positive / negative analog data voltage in accordance with the first data control signal SD _LEFT . The positive / negative analog data voltages output from the first group of source drive ICs SD_IC are supplied to data lines existing in the left half of the pixel array.

Referring to FIG. 10, the second timing controller 11B is mounted on the second PCB 31B and timing signals input from the system board 14 through the first connector 32B of the second PCB 31B. The second data control signal SD _RIGHT is generated to control the second group of source drive ICs SD_IC based on Vsync, Hsync, DE, and CLK. A second data control signal (SDC _RIGHT) is supplied to the second PCB (31B) of the source drive IC of the second group connected to the second PCB (31B) via a data bus, a control signal wiring formed on the (SD_IC). The second group of source drive ICs SD_IC receive the digital video data RGB _RIGHT input from the system board 14 via the first connector 32B of the second PCB 31B to the second timing controller 11B. Is converted into a positive / negative analog data voltage according to the second data control signal SD _RIGHT . The positive / negative analog data voltages output from the second group of source drive ICs SD_IC are supplied to data lines existing in the right half of the pixel array.

When the driving method of the liquid crystal module illustrated in FIGS. 7 to 10 is required, the data control signals SD _{LEFT and} SDC _RIGHT and the gate control signal output from the first and second timing controllers 11A and 11B may be changed. Only the GDC) can be changed to cope with a change in the driving method.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a front perspective view of a liquid crystal module according to a first embodiment of the present invention.

3 is a rear perspective view of the liquid crystal module according to the first embodiment of the present invention.

4A is a plan view showing in detail the first PCB shown in FIGS. 2 and 3.

4B is a plan view showing in detail the second PCB shown in FIGS. 2 and 3.

5 is a waveform diagram illustrating input waveforms of the timing controllers illustrated in FIGS. 4A, 9, and 10.

6 is a waveform diagram illustrating output waveforms of the timing controllers illustrated in FIGS. 4A, 9, and 10.

7 is a front perspective view of a liquid crystal module according to a second embodiment of the present invention.

8 is a rear perspective view of the liquid crystal module according to the second embodiment of the present invention.

FIG. 9 is a plan view showing in detail the first PCB 31A shown in FIGS. 7 and 8.

FIG. 10 is a plan view showing in detail the second PCB 31B shown in FIGS. 7 and 8.

Description of the Related Art

10: LCD panel 11, 11A, 11B: timing controller

12: data driving circuit 13: gate driving circuit

15 DC-DC converter 31A, 31B: PCB

32A, 32B, 33A, 33B: Connector

SD_IC: Source Drive IC

Claims (7)

A liquid crystal display panel; A plurality of source drive ICs converting digital video data into a data voltage in response to a data control signal and supplying the digital voltage to data lines of the liquid crystal display panel; A gate driving circuit sequentially supplying gate pulses to gate lines of the liquid crystal display panel in response to a gate control signal; A printed circuit board connected to the source drive ICs; And A timing controller mounted on the printed circuit board to generate the data control signal and the gate control signal; And the digital video data is generated from an external system board connected through a connector of the printed circuit board and transmitted directly from the external system board to the source drive ICs. The method of claim 1, The external system board, Generate a timing signal including a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock, input the timing signal to the timing controller through the connector, And the timing controller generates the data control signal and the gate control signal based on the timing signal. The method of claim 2, The source drive ICs, A first group of source drive ICs connected to data lines on a left half of the liquid crystal display panel; And And a second group of source drive ICs connected to data lines on the right half of the liquid crystal display panel. The method of claim 3, wherein The printed circuit board, A first printed circuit board mounted with the timing controller and connected to the first group of source drive ICs; And And a second printed circuit board connected to the second group of source drive ICs. The method of claim 3, wherein The first printed circuit board and the second printed circuit board is connected through a second connector and a flexible circuit board, The data control signal is supplied to the source drive ICs of the first group through data control signal bus lines formed on the first printed circuit board, and the first printed circuit board, the second connector, and the flexible circuit. And a plurality of source drive ICs of the second group through data control signal bus lines formed on a substrate and the second printed circuit board. The method of claim 4, wherein The timing controller, A first timing controller mounted on the first printed circuit board to generate a first data control signal and the gate control signal for controlling the first group of source drive ICs; And And a second timing controller mounted on the second printed circuit board to generate a second data control signal for controlling the second group of source drive ICs. The method of claim 6, The first timing controller generates the first data control signal and the gate control signal based on the timing signal, And the second timing controller generates the second data control signal based on the timing signal.

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