KR20110008829A - Nonvolatile Memory Device And Its Program Method - Google Patents

Abstract

The nonvolatile memory device provided herein includes a plurality of memory blocks each formed in wells; A bias block configured to bias a well of a selected memory block of the plurality of memory blocks; And a control logic block that controls the bias block to precharge doped regions of the selected memory block to the junction voltage before word line voltages are applied to the selected memory block in a program operation.

Description

Non-volatile memory device and its program method {NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF}

The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile memory device.

As a nonvolatile memory device, a flash memory device is a kind of EEPROM in which a plurality of memory areas are erased or programmed in one program operation. A typical EEPROM allows only one memory area to be erased or programmable at a time, which allows the flash memory device to operate at a faster and more efficient speed when systems using the flash memory device read and write to other memory areas at the same time. It means that there is. All forms of flash memory and EEPROM are worn out after a certain number of erase operations due to degradation of the charge storage means used to store the data or wear of the insulating film surrounding the charge storage means.

Flash memory devices store information on the silicon chip in a manner that does not require a power source to maintain the information stored on the silicon chip. This means that if the power to the chip is interrupted, the information is maintained without consuming power. In addition, flash memory devices provide physical shock resistance and fast read access times. Because of these features, flash memory devices are commonly used as storage devices for devices powered by batteries.

It is an object of the present invention to provide a nonvolatile memory device and a program method thereof which can improve reliability.

One feature of the invention is a plurality of memory blocks formed in each well; A bias block configured to bias a well of a selected memory block of the plurality of memory blocks; And a control logic block controlling the bias block to precharge doped regions of the selected memory block to the junction voltage before word line voltages are applied to the selected memory block during a program operation. will be.

In an exemplary embodiment, when the word line voltages are applied to the selected memory block, junction voltages of doped regions of the selected memory block are boosted by the word line voltages, and the boosted junction voltages are selected by the selected line. Applied to the channel voltages of the strings belonging to the memory block.

In an exemplary embodiment, the doped regions are source / drain regions of memory cells belonging to the selected memory block.

In an exemplary embodiment, each of the plurality of memory blocks includes first bit lines, and the first bit lines of each of the plurality of memory blocks are through switch blocks respectively corresponding to the plurality of memory blocks. Connected to the second bit lines, the switch blocks are formed in separate wells, respectively.

Another aspect of the present invention is to provide a program method of a nonvolatile memory device including a plurality of memory blocks. The program method precharges doped regions belonging to a selected memory block among the plurality of memory blocks with a junction voltage, and selects a bit line program voltage and a bit line program prohibition voltage for each of the bit lines of the selected memory block according to data to be programmed. And driving one of the word lines of the selected memory block with a pass voltage, and driving the selected word line of the word lines with a program voltage, wherein the plurality of memory blocks are formed in separate wells, respectively.

In an exemplary embodiment, when the pass voltage and the program voltage are applied to the selected memory block, the junction voltages of the doped regions of the selected memory block are boosted by the pass voltage and the program voltage and boosted. Junction voltages are applied to channel voltages of strings belonging to the selected memory block.

In an exemplary embodiment, the doped regions are source / drain regions of memory cells belonging to the selected memory block.

Another feature of the present invention is a nonvolatile memory device; And a controller configured to control the nonvolatile memory device, the nonvolatile memory device comprising a plurality of memory blocks formed in wells, respectively; A bias block configured to bias a well of a selected memory block of the plurality of memory blocks; And a control logic block for controlling the bias block to precharge the doped regions of the selected memory block to the junction voltage before word line voltages are applied to the selected memory block during a program operation.

According to the present invention, it is possible to reduce the stress applied to the program inhibited memory cell by reducing the voltage difference between the program voltage and the channel voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view schematically illustrating a cross section taken along a dotted line A-A 'of FIG. 1.

Referring to FIG. 1, the nonvolatile memory device 1000 of the present invention may include a memory cell array 100, a row decoder block 200, a read / write block 300, a bias block 400, and an input / output interface block 500. And a control logic block 600.

The memory cell array 100 stores data and may include memory cells arranged in rows and columns. The memory cells may constitute a plurality of memory blocks BLK0 to BLKn. Each of the memory cells will store 1-bit data or M-bit data (M is an integer of 2 or greater). Each of the memory cells may be comprised of a memory cell having a charge storage layer such as a floating gate or charge trap layer, a memory cell having a resistive variable element such as a PRAM cell, an FRAM cell, or an MRAM cell, and the like. However, it will be understood that the memory cell structure is not limited to that disclosed herein. The memory blocks BLK1 to BLKn constituting the memory cell array 100 are not formed in a single well but separately formed in corresponding wells. In other words, as shown in FIG. 2, the memory block BLK1 is formed in the corresponding independent well, the memory block BLK2 is formed in the corresponding independent well, and the memory block BLKn is located in the corresponding independent well. Is formed. Since the memory blocks BLK1 to BLKn are formed in independent wells, it may be possible to independently control the driving of the wells of the memory blocks BLK1 to BLKn.

In an exemplary embodiment, the wells will be P type wells. Wells will be formed in an N-type well formed in a semiconductor substrate. That is, the memory cell array 100 will have a triple-well structure. However, it will be appreciated that the well structure of the memory cell array 100 is not limited to that disclosed herein.

1, the row select block 200 operates in response to the control of the control logic block 600, and selects the memory blocks BLK0 to BLKn of the memory cell array 100. The row select block 200 may control the driving of the rows, that is, word lines, of the memory block selected according to the operation mode. The read / write block 300 operates under the control of the control logic block 600 and may be configured to read / write data to / from the memory cell array 100. For example, read / write block 300 will operate as a sense amplifier circuit configured to read data from memory cell array 100 during a read / verify read operation. The read / write block 300 may operate as a write driving circuit configured to write data to the memory cell array 100 during a write operation (or a program operation). The bias block 400 operates in response to the control of the control logic block 600 and will generate the voltages required for each operation (eg, word line voltages, well voltages, bit line voltages, etc.). . The input / output interface block 500 operates in response to the control of the control logic block 600, and performs signal paths between an external (eg, memory controller / host processing unit) and components of the nonvolatile memory device 1000. Will provide.

According to the present invention, the control logic block 600 will control the bias block 400 to precharge the doped regions of the selected memory block to the junction voltage before the word line voltages are applied to the selected memory block in the program operation.

FIG. 3 is a circuit diagram schematically illustrating one of the memory blocks shown in FIG. 1. Only one memory block BLK1 is shown in FIG. 3. However, the remaining memory blocks BLK2 to BLKn constituting the memory cell array 100 may also be configured in substantially the same manner as shown in FIG. 3. The memory block BLK1 may include strings 101 corresponding to the bit lines BL1 to BLm, respectively. As illustrated in FIG. 2, the memory block BLK1, that is, the strings 101 may be formed in an independent well. The strings 101 will be configured identically to each other.

Each string 101 may include a string select transistor SST, a ground select transistor GST, and memory cells MC1 to MC32 connected in series between the select transistors SST and GST. The string select transistors SST of the strings 101 are commonly controlled through the string select line SSL, and the ground select transistors GST of the strings 101 are common through the ground select line GSL. Will be controlled. Memory cells belonging to each row will be controlled in common through corresponding word lines. For example, the memory cells MC1 belonging to the first row are commonly controlled through the word line WL1, and the memory cells MC2 belonging to the second row are commonly controlled through the word line WL2. Memory cells MC32 belonging to the last row may be commonly controlled through the word line WL32.

Although only an example in which only 32 word lines WL1 to WL32 are arranged in the memory block BLK1 is shown in FIG. 3, it will be understood that the present invention is not limited to the one disclosed herein. For example, the memory block BLK1 may be configured to include 16 word lines, 64 word lines, or 128 word lines.

In an exemplary embodiment, the bit lines BL1 to BLm may be arranged to be shared by the memory blocks BLK1 to BLKn. The bit lines BL1 to BLm may be connected to the read / write block 300. However, it will be understood that the arrangement of the bit lines BL1 to BLm is not limited to that disclosed herein. For example, the bit lines BL1 to BLm may be arranged in each memory block and connected to the read / write block 300 through the global bit lines. That is, the memory cell array 100 may be configured to have a hierarchical bit line structure.

4 is a flowchart illustrating a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating a voltage change of a cell junction according to the program method of the present invention.

Prior to performing the program operation, in operation S100, data to be stored in the memory cell array 100 may be loaded into the read / write block 300 through the input / output interface block 500 under the control of the control logic block 600. will be. It will be appreciated that non-volatile memory device 1000 is provided with address information for selecting memory blocks, word lines, and the like prior to loading of data. Once the data to be stored in the memory cell array 100 is loaded in the read / write block 300, the row select block 200 is in response to the address information under the control of the control logic block 600. BLKn) (for example, BLK1). When the memory block BLK1 is selected, in step S120, the control logic block 600 causes a given voltage (hereinafter referred to as a “junction precharge voltage”) to be supplied to a well of the selected memory block (eg, BLK1). The bias block 400 will be controlled. According to this bias condition, since the PN junctions (or junction diodes) are formed by the doped regions 102 used for the well and the source / drain, the junction supplied to the well as shown in FIG. 5. The precharge voltage will be transferred to the doped regions 102 used as the source / drain of the cell.

In an exemplary embodiment, the voltages of the doped regions 102 are referred to as junction voltages V _JC as the source / drain voltages of each memory cell. The junction precharge voltage is supplied to the wells of the selected memory block BLK1, while the junction precharge voltage is not supplied to the wells of the unselected memory blocks BLK2 to BLKn. As mentioned above, since the memory blocks BLK1 to BLKn are formed in independent wells, it is possible to supply the junction precharge voltage only to the wells of the selected memory block BLK1 independently.

In operation S140, the junction precharge voltage supplied to the well may be discharged through the bias block 140 under the control of the control logic block 160. Although the junction precharge voltage is discharged from the well, the voltages of the doped regions 102 will remain because the PN junctions (or junction diodes) are reverse biased.

Doped regions (or source / drain regions) of the memory cells belonging to the selected memory block BLK1 through the above-described steps S120 and S140 may be precharged to the junction voltage V _JC . Here, the junction voltage V _JC of each doped region 102 will be determined by the junction precharge voltage. For example, the higher the junction precharge voltage, the higher the junction voltage V _JC will be. In contrast, the lower the junction precharge voltage, the lower the junction voltage V _JC will be.

After the junction precharge voltage is discharged from the well of the selected memory block, in step S160, the memory cells will be programmed according to the loaded data. More specifically, first, the well of the selected memory block BLK1 will be biased with the well voltage for the program operation. Next, the bit lines BL1 to BLm are formed by the read / write block 130 according to the loaded data while the string select transistors SST of the selected memory block BLK1 are turned on. Each of the program voltage and the bit line program inhibit voltage will be driven. Here, the bit line program voltage is applied to the string of the selected memory cell when the selected memory cell is the memory cell to be programmed, and the bit line program inhibit voltage is applied to the string of the selected memory cell when the selected memory cell is the memory cell to be program inhibited. .

With this bias condition, as is well known, each of the string select transistors SST will be selectively shut off according to the bit line voltage. For example, the string select transistor SST may be turned on when the bit line program voltage is applied to the bit line and shut off when the bit line program inhibit voltage is applied to the bit line. When the string select transistor SST is shut off, the string (or string channel) including the shut off string select transistor SST will be floated.

Next, the word lines WL1 to WL32 of the selected memory block BLK1 may be driven with a pass voltage by the row decoder block 110 under the control of the control logic block 160. When the pass voltage is supplied to the word lines WL1 to WL32, the memory cells of the selected memory block will be turned on. In the case of the strings 101 connected with the bit lines having the bit line program voltage, the junction voltages V _JC will be discharged to the bit lines when the pass voltage is supplied to the word lines WL1 to WL32. In contrast, in the case of the floated strings 101, the junction voltages V _JC are boosted primarily through parasitic capacitors (see FIG. 5) when the pass voltage is supplied to the word lines WL1 to WL32. Will be. Here, the boost due to the pass voltage will be determined by the voltage difference between the junction voltage V _JC and the floating gate (or control gate). For example, the boost due to the pass voltage will be small when the voltage difference between the junction voltage V _JC and the floating gate (or control gate) is small. In contrast, the boost due to the pass voltage will be large when the voltage difference between the junction voltage V _JC and the floating gate (or control gate) is large.

In addition to boosting the junction voltages V _JC , the channel voltages of the floated strings will also be high. The channel voltages of the floated strings will be affected by the junction voltages V _JC because the memory cells are turned on. That is, the junction voltages V _JC are added to the channel voltages, and as a result the channel voltages will be higher than the voltage determined by self boosting.

After the word lines WL1 to WL32 of the selected memory block are driven with the pass voltage, the program voltage will be supplied to the selected word line. At this time, unselected word lines will continue to be biased with a pass voltage. The channel voltage of the memory cell belonging to the floated string and connected to the selected word line, that is, the program inhibited memory cell, will be boosted by the program voltage. Similarly, when the program voltage is applied to the selected word line, the junction voltages V _JC of the program inhibited memory cell will also be boosted secondary through parasitic capacitors (see FIG. 5). The boosted junction voltages (eg, V _JC + α) will affect the channel voltage. That is, the junction voltages V _JC are added to the channel voltage, and as a result, the channel voltage will be higher than the voltage determined by the self boosting caused by the program voltage.

In an exemplary embodiment, although the boost of the junction voltage is affected by the pass voltage, the boost of the junction voltage will be determined primarily by the program voltage.

According to the foregoing description, it is possible to increase the channel voltages of the memory cells belonging to the floated strings by setting / precharging the doped regions 102 to the junction voltage V _JC . In particular, in the case of a program inhibited memory cell connected to the selected word line, when the doped regions 102 are precharged to the junction voltage V _JC , the voltage difference between the program voltage and the channel voltage is determined by the doped regions 102 being the junction voltage. When not precharged to (V _JC ) it will decrease compared to the voltage difference between the program voltage and the channel voltage. This means that stress (eg, program voltage stress) on the program inhibited memory cell connected to the selected word line is reduced. As the stress on the program inhibited memory cell is reduced, it is possible to prevent unwanted charges from being injected into the program prohibited memory cell. As design rules (or cell sizes) are reduced, undesired injection of charge into memory cells that are program inhibited by the program voltage may become serious. The above-described program method may improve the reliability of memory cells (or nonvolatile memory devices) by reducing program voltage stress.

FIG. 6 is a block diagram schematically illustrating a nonvolatile memory device according to another exemplary embodiment of the present invention, and FIG. 7 is a schematic block diagram illustrating a cross section taken along a dotted line B-B ′ of FIG. 6. Referring to FIG. 6, the nonvolatile memory device 2000 may include a memory cell array 2100, a row decoder block 2200, and a read / write block 2300. Although not shown in the drawings, the nonvolatile memory device 2000 may further include a bias block, an input / output interface block, and a control logic block shown in FIG. 1.

The memory cell array 2100 may include a plurality of memory blocks BLK1 to BLKn and a plurality of switch blocks SW1 to SWn. The plurality of memory blocks BLK1 to BLKn may correspond to the plurality of switch blocks SW1 to SWn, respectively. As illustrated in FIG. 7, memory blocks BLK1 to BLKn may be formed in independent wells, respectively. Similarly, as shown in FIG. 7, the switch blocks SW1 to SWn may be formed in separate wells, respectively. As described above, wells for memory blocks and switch blocks will be formed in an N-type well formed in a semiconductor substrate. In the memory cell array 2100, a plurality of global bit lines GBL1 to GBLm connected to the read / write block 2300 may be arranged. Each of the memory blocks BLK1 to BLKn may include a plurality of bit lines (hereinafter, referred to as local bit lines). Local bit lines of each of the memory blocks BLK1 to BLKn may be connected to the global bit lines GBL1 to GBLm through corresponding switch blocks SW1 to SWn. For example, the local bit lines LBL1e and LBL1o of the memory block BLK1 may be selectively connected to the global bit line GBL1 through the switch block SW1. The row decoder block 2200 may control the selection and driving of the memory blocks BLK1 to BLKn and the switch blocks SW1 to SWn. This will be explained in detail later.

FIG. 8 is a block diagram illustrating a portion of a memory cell array and a row decoder block illustrated in FIG. 6. In FIG. 8, only one memory block BLK1 and a switch block SW1 are shown. However, the remaining memory blocks BLK2 to BLKn and the remaining switch blocks SW2 to SWn may also be configured in substantially the same manner as shown in FIG. 8.

The memory block BLK1 is substantially the same as that described in FIG. 3, and a description thereof will therefore be omitted. The memory block BLK1 includes bit lines, that is, local bit lines LBL1e and LBL1o to LBLxe and LBLxo, and the local bit lines LBL1e and LBL1o to LBLxe and LBLxo are configured in pairs. will be. The switch block SW1 may include switches 2110 to 2120 respectively corresponding to local bit line pairs. The switch 2110 may be composed of two NMOS transistors N1 and N2. The NMOS transistor N1 connects the local bit line LBL1e to the global bit line GBL1 in response to the switch control signal SCTRL1, and the NMOS transistor N2 responds to the switch control signal SCTRL2. Will connect the line LBL1o to the global bit line GBL1. That is, one of the pair of local bit lines LBL1e and LBL1o may be connected to the global bit line GBL1 through the switch 2110. The switch control signals SCTRL1 and SCTRL2 may be generated by the decoding and driving circuit 2220 of the row decoder block 2200.

The row decoder block 2200 may include a first decoding and driving circuit 2210 configured to control the selection and driving of the memory block BLK1 and a second decoding and driving circuit configured to control the selection and driving of the switch block SW1. 2220). In particular, the second decoding and driving circuit 2220 may switch switch signals SCTRL1 and SCTRL2 in response to address information for selecting a memory block BLK1 and address information for selecting one of a pair of bit lines. ) Will be activated. The second decoder and driver circuit 2200 may deactivate the switch control signals SCTRL1 and SCTRL2 so that the local bit lines and the global bit lines are electrically separated during the erase operation. Each of the remaining memory blocks BLK2 to BLKn is driven through a first and decoding and driving circuit 2210 configured in the same manner as shown in FIG. 8, and each of the remaining switch blocks SW2 to SWn is shown in FIG. 8. Drive through a second and decoding and driving circuit 2220 configured identically to the above.

As described in FIG. 1, the nonvolatile memory device 2000 according to another embodiment of the present invention may junction the doped regions 102 of the selected memory block before the pass voltage and the program voltage are supplied to the word lines. Precharging / setting to voltage will be performed. The nonvolatile memory device 2000 according to another embodiment of the present invention is substantially the same as that described in FIG. 1 except that the local bit lines are connected to the global bit lines through a switch block corresponding to the selected memory block. The same, and a description thereof will therefore be omitted. The nonvolatile memory device 2000 according to another embodiment of the present invention may have substantially the same effect as that shown in FIG. 1. That is, the reliability of memory cells (or nonvolatile memory devices) may be improved by reducing program voltage stress.

It is possible to minimize the loading of global bit lines by connecting the local bit lines of the selected memory block to the global bit lines through the switch block. Minimizing bit line loading means improved read speed. In addition, by minimizing the bit line loading, it is possible to exclude the adoption of the mat structure when designing a large capacity chip. The matte structure results in the addition of components such as row decoder blocks, read / write blocks, bias blocks, and the like. Therefore, it is possible to reduce the chip size in the design of a large capacity chip by excluding the adoption of the mat structure. By forming the memory blocks in separate wells, an increase in ISPP time (or program time) during program operation can be suppressed. This is because only independent wells of the selected memory block are biased to the well voltage during the program operation. In addition, by increasing the distance between the global bit lines through the switch blocks it is possible to minimize the increase in the coupling capacitance.

The program operation will be performed using a bias condition suitable for generating F-N tunneling. For example, F-N tunneling will be caused by the voltage difference between the well voltage and the control gate voltage (ie, word line voltage). Such voltage difference can be made variously. For example, it is possible to generate F-N tunneling by applying a word line voltage (ie, a program voltage) of 0 V to the well and approximately 15 V to the control gate. In this case, the bit lines will be driven to 0V or the supply voltage, depending on the program data. Or FN by applying a negative voltage (e.g., -5V) to the well (including the well of the memory block and the well of the switch block) and a word line voltage of approximately 10V (i.e., program voltage) to the control gate. It is possible to generate tunneling. In this case, the bit lines will be driven to 0V or negative voltage (eg -5V) depending on the program data. It will be appreciated that the program method according to the invention is not limited to the bias conditions disclosed herein (the bias conditions for F-N tunneling).

FIG. 9 is a block diagram schematically showing a memory system including a nonvolatile memory device according to the present invention, and FIG. 10 is a block diagram schematically showing the controller shown in FIG. 9.

Referring to FIG. 9, the memory system 3000 may be a collector circuit card such as a smart card, a memory card, or the like. The memory system 3000 may include a controller 3100 and a nonvolatile memory device 3200. The nonvolatile memory device 3200 may be substantially the same as that shown in FIG. 1 or 6. The nonvolatile memory device 3200 will store data using the program method according to the present invention. The controller 3100 may include a CPU 3110, a ROM 3120, a RAM 3130, and an input / output interface 3140, as shown in FIG. 10. Depending on the field in which the integrated circuit card 3000 is applied, the controller 3100 may further include components capable of performing an encryption / decryption function, an error correction function, a security function, and the like.

11 is a block diagram schematically illustrating a computing system including a nonvolatile memory device according to the present invention.

Referring to FIG. 11, the computing system 4000 may include a microprocessor 4100, a user interface 4200, a modem 4300 such as a baseband chipset, and a controller 4400 electrically connected to the bus 4001. And a storage medium 4500. The storage medium 4500 will be comprised of a nonvolatile memory device in accordance with the present invention. The storage medium 4500 may store, via the controller 4400, N-bit data (N is an integer greater than or equal to 1) processed / to be processed by the microprocessor 4100. If the computing system 4000 is a mobile device, a battery 4600 for supplying an operating voltage of the computing system will be further provided. Although not shown in the drawings, the computing system according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. Self-explanatory to those who have learned. The controller 4400 and the storage medium 4500 may be embodied as a memory card, an SSD, or the like.

Storage media and / or controllers may be mounted using various forms of packages. For example, storage media and / or controllers may include Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), and the like can be implemented using packages.

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is believed that the present invention includes modifications and variations of this invention provided they come within the scope of the following claims and their equivalents.

1 is a block diagram schematically illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view schematically illustrating a cross section cut along a dotted line A-A 'of FIG. 1.

FIG. 3 is a circuit diagram schematically illustrating one of the memory blocks shown in FIG. 1.

4 is a flowchart illustrating a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

5 is a diagram illustrating a voltage change of a cell junction according to the program method of the present invention.

6 is a block diagram schematically illustrating a nonvolatile memory device according to another embodiment of the present invention.

FIG. 7 is a schematic block diagram illustrating a cross section taken along a dotted line B-B ′ of FIG. 6.

FIG. 8 is a block diagram illustrating a portion of a memory cell array and a row decoder block illustrated in FIG. 6.

9 is a block diagram schematically illustrating a memory system including a nonvolatile memory device according to the present invention.

FIG. 10 is a block diagram schematically illustrating the controller shown in FIG. 9.

11 is a block diagram schematically illustrating a computing system including a nonvolatile memory device according to the present invention.

Claims (10)

A plurality of memory blocks each formed in the wells; A bias block configured to bias a well of a selected memory block of the plurality of memory blocks; And And a control logic block controlling the bias block to precharge doped regions of the selected memory block to the junction voltage before word line voltages are applied to the selected memory block in a program operation. The method of claim 1, When the word line voltages are applied to the selected memory block, junction voltages of doped regions of the selected memory block are boosted by the word line voltages, and the boosted junction voltages are channels of strings belonging to the selected memory block. Nonvolatile memory device applied to voltages. The method of claim 2, And the doped regions are source / drain regions of memory cells belonging to the selected memory block. The method of claim 1, Each of the plurality of memory blocks includes first bit lines, and the first bit lines of each of the plurality of memory blocks are connected to second bit lines through switch blocks respectively corresponding to the plurality of memory blocks. Nonvolatile memory device. The method of claim 4, wherein And the switch blocks are formed in separate wells, respectively. In the method of programming a nonvolatile memory device comprising a plurality of memory blocks: Precharges the doped regions belonging to the selected memory block among the plurality of memory blocks with a junction voltage, Driving each of the bit lines of the selected memory block to one of a bit line program voltage and a bit line program prohibition voltage according to the data to be programmed, Driving word lines of the selected memory block with a pass voltage, Driving a selected one of the word lines to a program voltage; And the plurality of memory blocks are formed in independent wells, respectively. The method of claim 6, When the pass voltage and the program voltage are applied to the selected memory block, the junction voltages of the doped regions of the selected memory block are boosted by the pass voltage and the program voltage, and the boosted junction voltages are boosted by the selected memory block. And the channel voltages of the strings belonging to The method of claim 7, wherein And the doped regions are source / drain regions of memory cells belonging to the selected memory block. A nonvolatile memory device; And A controller configured to control the nonvolatile memory device, The nonvolatile memory device A plurality of memory blocks each formed in the wells; A bias block configured to bias a well of a selected memory block of the plurality of memory blocks; And And a control logic block controlling the bias block to precharge doped regions of the selected memory block to the junction voltage before word line voltages are applied to the selected memory block during a program operation. The method of claim 9, And the nonvolatile memory device and the controller constitute an integrated circuit card.

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