KR20110077175A - Flash memory device and its formation method - Google Patents

Abstract

A method of forming a flash memory device according to an embodiment of the present invention includes a control transistor including a tunnel oxide film, a floating gate, a dielectric film, and a control gate, and a tunnel oxide film, a floating gate, a dielectric film, and a select gate on a semiconductor substrate on which p wells are formed. Forming a select transistor, performing an impurity ion implantation process on the semiconductor substrate exposed by the control transistor and the select transistor to form an n-type source / drain region and an n-type junction region, and p for the drain region Performing a type impurity ion implantation process to form a drain region of a pnp structure.

As described above, the present invention can increase the efficiency of programming because the drain region is formed in the pnp structure, and the hole is induced in the pnp structure as well as the conventional BTBT thermal hole injection in the programming process. Rather, it has the effect of increasing programming speed.

Nonvolatile Memory, Flash, Flash, Select, Select, Drain, Control Gate

Description

Flash memory device and formation method thereof {NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a flash memory device and a method of forming the same, which can increase programming efficiency as well as increase programming speed.

In general, semiconductor memory is classified into volatile memory and non-volatile memory. Most of volatile memory is occupied by RAM such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), and data can be entered and stored when power is applied, but data cannot be saved because of volatilization when power is removed. There is this. On the other hand, nonvolatile memory, which occupies most of ROM (Read Only Memory), is characterized in that data is preserved even when power is not applied.

A typical memory device of such a nonvolatile memory device is an EEPROM, and the EEPROM is a nonvolatile memory device that can be electrically rewritten, and a structure using a floating gate cell has been widely used.

There are two types of EEPROM cells, a flash type comprising one cell with one transistor and a Protox type having two cells with one transistor. Among them, since the flash type cell is composed of one transistor, the unit cell size has an advantage of being small, while the reliability thereof is considerably lower than that of the Flotox type cell.

Hereinafter, an EEPROM type flash memory will be described with reference to the accompanying drawings.

As shown in FIG. 1, in the conventional EEPROM type flash memory cell, a thin gate insulating film 102 is formed in a predetermined portion of an active region on a semiconductor substrate 100, and a predetermined portion of the flash memory cell is formed on a predetermined portion of the gate insulating film 102. A control transistor I having a " floating gate 104 / interlayer insulating film 106 / control gate 108 " stacked structure is formed, and the select transistor II is formed on the gate insulating film 102 on one side of the control transistor I. The select gate 110 is formed to act. In the semiconductor substrate 100 under the gate insulating layer 102, a junction region 112 having a structure extending in a long manner so as to overlap a predetermined portion with the sense transistor I and the select transistor II is formed, and the junction region 112 is formed. The source region 114 is formed inside the semiconductor substrate 100 at a predetermined distance from one side of the c) so as to overlap a predetermined portion with the sense gate 110, and a predetermined interval with respect to the other side of the junction region 104. The drain region 116 is formed in the semiconductor substrate 100 at a spaced apart point so as to overlap a predetermined portion with the select transistor II.

The EPPROM cell having the above configuration may perform a programming operation by injecting a hole into the floating gate 108 and an erase operation by injecting electrons by junction tunneling.

That is, the programming operation is performed by a band to band tunneling (BTBT) method, which is a semiconductor substrate 100, a select gate 110, and a source region 114. ) Is grounded, and a positive drain voltage, such as 5V, is applied to the N-doped drain region 116 to produce band-to-band tunneling electrons and holes, and the holes thus formed are subjected to a strong negative gate voltage in the lateral direction. As a result, the thermal holes are injected into the floating gate 108.

However, the method of injecting and programming a hole as described above has a disadvantage in that it is more difficult than programming by injecting electrons. That is, as shown in FIG. 2, when a 2 poly EEPROM type embedded flash is manufactured by a conventional N-type flash cell manufacturing process and programmed under a BTBT type program condition, a program voltage of 2 V or less is used. Since a program speed of several msec is generated to reach, there is a problem in that it becomes vulnerable to program interruption and thus cannot function as a memory device.

In order to solve the above problems, the present invention is not only to increase the efficiency of programming but also to increase the programming speed since the hole is induced in the floating gate of the control transistor induced in the pnp structure of the drain region. A flash memory device capable of forming the same and a method of forming the same are provided.

The object of the present invention is not limited to the above-mentioned object, and other objects which are not mentioned will be clearly understood by those skilled in the art from the following description.

A method of forming a flash memory device according to an exemplary embodiment of the present invention may include a control transistor including a tunnel oxide film, a floating gate, a dielectric film, and a control gate on a semiconductor substrate on which p wells are formed, and the tunnel oxide film, floating gate, dielectric film, and select gate. Forming a select transistor comprising: forming an n-type source / drain region and an n-type junction region by performing an impurity ion implantation process on the semiconductor substrate exposed by the control transistor and the select transistor; Performing a p-type impurity ion implantation process on the region to form a drain region of the pnp structure.

In the method of forming a flash memory device according to an embodiment of the present disclosure, the forming of the n-type source / drain region and the n-type junction region may include forming an oxide film for a spacer on the semiconductor substrate on which the control transistor and the select transistor are formed. Forming a low concentration junction region by performing a low concentration impurity ion implantation process on the semiconductor substrate exposed by the control transistor and the select transistor; Forming a spacer comprising the spacer oxide film and the spacer insulating film on sidewalls of the control transistor and the select transistor by forming a front surface etch, and an n-type impurity ion implantation process using the spacer as an ion implantation mask.And forming the source / drain regions and the junction regions.

In the method of forming a flash memory device according to an embodiment of the present disclosure, forming the drain region of the pnp structure may include forming a photoresist pattern in which only the drain region is opened, and forming an ion implantation mask in the photoresist pattern. Forming a drain region of the pnp structure by implanting p-type impurity ions into the drain region through a p-type impurity ion implantation process; and removing the photoresist pattern.

In another aspect, a flash memory device may include a semiconductor substrate having a p well, a control transistor and a select transistor formed on the semiconductor substrate, and a portion of the control transistor and the select transistor overlapping each other. A junction region formed therein, an n-type source region formed inside the semiconductor substrate to overlap a predetermined portion of the select transistor, and a drain region having a pnp structure formed inside the semiconductor substrate so that a predetermined portion of the control transistor overlaps. .

According to the present invention, since the drain region is formed into a pnp structure, not only the conventional BTBT thermal hole injection is performed in the programming process, but also the hole derived from the pnp structure is injected into the floating gate of the control transistor, thereby increasing programming efficiency as well as programming speed. There is an effect that can increase.

The objects and effects of the present invention and the technical configurations for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intentions or customs of the user, the operator, and the like.

The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The present embodiments are merely provided to complete the disclosure of the present invention and to fully inform the scope of the invention to those skilled in the art, and the present invention is defined by the scope of the claims. It will be. Therefore, the definition should be based on the contents throughout this specification.

In the embodiment of the present invention, since the drain region is formed in the pnp structure, not only the conventional BTBT thermal hole injection but also the hole induced in the pnp structure are injected into the floating gate of the control transistor, thereby increasing the programming efficiency. Instead, a flash memory device that can increase programming speed and a method of forming the same will be described.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3A to 3D are cross-sectional views illustrating a process of manufacturing an EEPROM type flash memory device according to an exemplary embodiment of the present invention.

As shown in FIG. 3A, after forming a predetermined screen oxide film (not shown), a well ion implantation process using the screen oxide film as a mask is performed to each well region (not shown) in the semiconductor substrate 300. ), For example p wells. In this case, the screen oxide layer prevents the exposed upper surface of the substrate 300 from being damaged during the diffusion process (or ion implantation process) for forming the well region.

Then, an oxide process is performed to form the tunnel oxide film 302 on the semiconductor substrate 300. At this time, the oxidation process may be a wet oxidation or dry oxidation process. Preferably, it is formed by a thermal oxidation process. In particular, the tunnel oxide film 302 may be formed of an oxynitride film containing a nitrogen component in order not to deteriorate easily during operation of the memory device.

Subsequently, a floating silicon polysilicon film 304 (hereinafter referred to as a first polysilicon film) is deposited on the tunnel oxide film 302. In this case, the first polysilicon layer 304 is formed by a low pressure chemical vapor deposition (LPCVD) method using a doped or undoped polysilicon layer. For example, in the case of a doped polysilicon film, it is formed using SiH2 and PH3 or Si2H6 and PH3 gas. On the other hand, in the case of the undoped polysilicon film, impurities are added to the doped polysilicon film during the subsequent LDD ion implantation process or the source / drain ion implantation process.

Then, a first dielectric film (formed of IPD; Inter Poly Dielectric, 306) is deposited on the first polysilicon film 304. At this time, the first dielectric film 306 is formed in an ONO (Oxide / Nitride / Oxide) structure.

Thereafter, a hard mask 308 is formed on the first dielectric layer 306. In this case, the hard mask 308 may be formed of a single film of any one of an oxide film, a nitride film, and an oxynitride film, or may be formed of a laminated film in which they are stacked.

Thereafter, a photoresist (not shown) is applied on the hard mask 308, and then a photoresist pattern is formed by performing an exposure and development process using a photomask (not shown). In this case, the photoresist pattern is formed such that a part of the hard mask 308 is opened.

Next, an etching process using a photoresist pattern as a mask is performed to sequentially etch the hard mask 308, the first dielectric film 306, the first polysilicon film 304, and the tunnel oxide film 302. As a result, a plurality of EEPROM cell control gates T1 and select gates T2 are formed on the semiconductor substrate 100.

Next, as shown in FIG. 3D, a low-concentration LDD (Lightly) is formed after forming the spacer oxide film 310, for example, a TEOS film, on the semiconductor substrate 300 on which the control transistor T1 and the select transistor T2 are formed. Doped Drain) Ion implantation process 312 is performed to form low concentration junction regions 314a and 314b.

Here, the low-concentration junction regions 314a and 314b are formed in an n-type, i.e., an ion implantation process using impurity ions of any one of Asenic, Phosphorus, and Indium as a Group 5 material. Conduct.

In the embodiment of the present invention, the p wells are formed in the semiconductor substrate 300, and the low concentration junction regions 314a and 314b have been described as an example, but the N wells are formed in the semiconductor substrate 300. The low concentration junction regions 314a and 314b can then be formed in a p-type. In the case of forming the p-type, impurity ions of any one of boron, BF2 and antimony are used as the Group 3 material.

3B, the insulating film 316 for the spacer is formed on the semiconductor substrate 300 on which the low concentration junction regions 314a and 314b are formed, and then the control transistor T1 is selected through the front surface etching process. The spacer 318 in which the spacer oxide film 308 and the spacer insulating film 316 are sequentially formed is formed on sidewalls of each of the transistors T2. On the other hand, the spacer is filled between the control transistor T1 and the select transistor T2. Then, a high concentration source / drain ion implantation process using a spacer as a mask is performed to respectively source / drain regions 320a and 320b and junction regions 320c which are high concentration junction regions in the semiconductor substrate 300 exposed to both sides of the spacer. ). Here, the source / drain regions 320a and 320b and the junction region 320c are n-type.

Then, as shown in FIG. 3C, after the photoresist is not shown, the photoresist pattern 322 is formed by performing an exposure and development process using a photomask. In this case, the photoresist pattern 322 has a structure in which the drain region 320b is opened.

Thereafter, an ion implantation process using the photoresist pattern 322 as an ion implantation mask is performed to implant p-type impurity ions into a portion of the drain region 320b. As the P-type impurity ions, any one of boron, BF2, and antimony is used. Then, as shown in FIG. 3D, the photoresist pattern 322 is stripped off.

According to an exemplary embodiment of the present invention, the drain region 320b has a pnp structure, that is, a bipolar transistor structure, so that the current is increased compared to the conventional pn structure, thereby reducing the access time.

A programming process of an EEPROM type flash memory having the above structure will be described below.

First, the semiconductor substrate 300, the select transistor T2, and the source region 320a are all grounded, and a positive drain voltage, for example, 5V, is applied to the drain region 320b of the pnp structure and the band-to-band tunneling electrons. Holes are generated, and the holes are thermally injected by the strong negative gate voltage in the lateral direction and injected into the floating gate 304 of the control transistor T1. At this time, the electrons remaining in the drain region 320b move to the drain contact (not shown) to induce holes in the p-doped drain region 320b, and the induced holes are opened by a strong negative gate voltage in the lateral direction. Holes are injected into the floating gate 304 of the control transistor T1.

According to the embodiment of the present invention, not only the conventional BTBT thermal hole injection but also the floating gate 304 of the hole control transistor T1 derived from the pnp structure may be increased in the programming process, thereby increasing the programming efficiency. But you can increase the programming speed.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. For example, those skilled in the art can change the material, size, etc. of each component according to the application field, or combine or replace the disclosed embodiments in a form that is not clearly disclosed in the embodiments of the present invention, but this also It does not depart from the scope of the invention. Therefore, the above-described embodiments are to be considered in all respects as illustrative and not restrictive, and such modified embodiments should be included in the technical spirit described in the claims of the present invention.

As shown in FIG. 1, a cross-sectional view of a flash memory cell of a conventional EEPROM type is shown.

2 is a graph showing a conventional flash memory operation speed,

3A to 3D are cross-sectional views illustrating a process of manufacturing an EEPROM type flash memory device according to an exemplary embodiment of the present invention.

Claims (4)

forming a control transistor comprising a tunnel oxide film, a floating gate, a dielectric film, and a control gate, and a select transistor including the tunnel oxide film, a floating gate, a dielectric film, and a select gate on a p-well formed semiconductor substrate; Performing an impurity ion implantation process on the semiconductor substrate exposed by the control transistor and the select transistor to form an n-type source / drain region and an n-type junction region; Performing a p-type impurity ion implantation process on the drain region to form a drain region having a pnp structure; Flash memory device manufacturing method. The method of claim 1, Forming the n-type source / drain region and n-type junction region, Forming an oxide film for a spacer on the semiconductor substrate on which the control transistor and the select transistor are formed; Performing a low concentration impurity ion implantation process on the semiconductor substrate exposed by the control transistor and the select transistor to form a low concentration junction region; A spacer insulating layer is formed on the semiconductor substrate on which the low concentration junction region and the junction region are formed, and then an entire surface is etched to form a spacer including the spacer oxide layer and the spacer insulating layer on sidewalls of the control transistor and the select transistor. To do that, Performing an n-type impurity ion implantation process using the spacer as an ion implantation mask to form the source / drain region and the junction region; Flash memory device manufacturing method. The method of claim 1, Forming the drain region of the pnp structure, Forming a photoresist pattern in which only the drain region is opened; Forming a drain region of the pnp structure by implanting p-type impurity ions into the drain region through a p-type impurity ion implantation process using the photoresist pattern as an ion implantation mask; Removing the photoresist pattern Flash memory device manufacturing method. a semiconductor substrate having a p well formed therein; A control transistor and a select transistor formed on the semiconductor substrate; A junction region formed inside the semiconductor substrate to overlap a predetermined portion of the control transistor and the select transistor; An n-type source region formed in the semiconductor substrate so as to overlap a predetermined portion of the select transistor; And a drain region having a pnp structure formed inside the semiconductor substrate such that a predetermined portion of the control transistor overlaps. Flash memory device.

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