KR20110078949A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming an N type well in a predetermined region of an epitaxial layer (P-EPI) formed in a semiconductor substrate, and forming a drift region on the surface of the semiconductor substrate in the N type well. Forming a P-type body region spaced apart from the drift region by a predetermined distance in the epitaxial layer, forming an N-buried layer (NBL) region at a predetermined position under the N-type well, Forming a device isolation region on the surface, forming a gate pattern on a portion of the N-type well and the epitaxial layer, and forming a source region and a drain region in the P-type body region and the drift region, respectively. It is characterized by.

N-buried layer (NBL), low side LDMOS

Description

Semiconductor device and method for manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a Lateral Double-diffused Metal Oxide Semiconductor (LDMOS) semiconductor device and a manufacturing method thereof.

The commonly used power MOS field effect transistor (MOSFET) has a higher input impedance than the bipolar transistor, so the power gain is large, the gate driving circuit is very simple, and because it is a unipolar device, it is applied to the minority carriers while the device is turned off. There is no time delay caused by accumulation or recombination.

Therefore, applications in switching mode power supplies, lamp stabilization, motor drive circuits, and the like are gradually spreading. As such power MOSFETs, a DMOSFET structure using integrated planar diffusion technology is widely used, and a typical LDMOS transistor has been developed.

1 is a cross-sectional view showing an example of the structure of a conventional LDMOS transistor.

In FIG. 1, the drift region 105 is formed by implanting impurity ions, for example, phosphorus ions, onto a surface of a semiconductor substrate and performing a diffusion process at a high temperature for a long time.

Phosphorous ions on the surface of the semiconductor substrate are diffused into the bulk below the surface by a long diffusion process, wherein the concentration of impurity ions is maximized in the field oxide layer 130, which is the surface of the semiconductor substrate, toward the bulk. The concentration gradually decreases.

Therefore, when bias is applied to the gate electrode 110 and the drain region 120, most current flows along the surface of the semiconductor substrate because the resistance is the smallest in the surface of the semiconductor substrate and the resistance is large in the bulk region. Thus, an electric field is concentrated around the sidewall of the N + drain region.

It is not a big problem when a small current flows, but if a large current flows to this part, holes and electrons are suddenly generated by impact ionization, and thus the breakdown voltage characteristic against black down is not good.

Therefore, development of an LDMOS transistor having excellent breakdown voltage characteristics is required.

SUMMARY OF THE INVENTION The present invention provides a semiconductor device and a method of manufacturing the same that improve current characteristics and breakdown voltage characteristics.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming an N type well in a predetermined region of an epitaxial layer (P-EPI) formed in a semiconductor substrate, and forming a drift region on the surface of the semiconductor substrate in the N type well. Forming a P-type body region spaced apart from the drift region by a predetermined distance in the epitaxial layer, forming an N-buried layer (NBL) region at a predetermined position under the N-type well, Forming a device isolation region on the surface, forming a gate pattern on a portion of the N-type well and the epitaxial layer, and forming a source region and a drain region in the P-type body region and the drift region, respectively. It is characterized by.

According to the semiconductor device and the manufacturing method thereof according to the embodiment of the present invention, by forming an N-buried layer (NBL) region under the drift region to distribute the current flow path concentrated on the surface of the drift region, the current characteristics of the transistor and Withstand pressure characteristics can be improved.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, an epitaxial layer P-EPI is formed on the semiconductor substrate 200, and an N well region HVNWELL 205 is formed in the epitaxial layer P-EPI.

For example, after an epitaxial layer is grown on the semiconductor substrate 200, the epitaxial layer is lightly doped with boron as a p-type impurity.

In addition, a first mask (not shown) for forming an active region is formed on the semiconductor substrate 200 using photolithography, and an N-type impurity (eg, phosphorus (P) is formed using the formed first mask. phosphorus)) may be implanted into the epitaxial layer with high energy to form the N well region 205. In this case, additional impurity implantation may be performed to meet the threshold voltage of the cell, as necessary.

Next, impurity ions are implanted into a portion of the semiconductor substrate 200 to form the P-type body region 220 and the drift region 230 spaced by a predetermined interval.

First, an N-type impurity ion, for example, phosphorus ion, is implanted into the entire surface of the exposed semiconductor substrate 200 and then an impurity diffusion process is performed to form the drift region 230.

Subsequently, P-type impurity ions, for example boron (B) ions, are ion-implanted using a predetermined ion implantation mask (not shown) to form the P-type body region 220.

An N-type impurity control region N-ADJUST 232 may be formed on the surface of the semiconductor substrate between the drift region 230 and the P-type body region 220.

As shown in FIG. 2B, an N-buried layer (NBL) region is formed at a predetermined position under the N well region HVNWELL 205. The NBL region is formed by implanting an ion implantation mask (not shown) Phosphorous ions formed using a photolithography process.

One end of the NBL region 240 is located away from the P-type body region 220 in the lateral direction, and is positioned below the field insulating layer 210, and the other end is formed to be extended to the lower portion of the drain region to be described later. . In the longitudinal direction, it may be formed to be located under the bottom of the drain region.

As shown in FIG. 2C, field oxide films 252 and 254 are formed on a portion of the semiconductor substrate 200.

The field oxide films 252 and 254 form a silicon oxide film and a silicon nitride film pattern (not shown) on the semiconductor substrate 200, ion implantation of oxygen on the surface of the semiconductor substrate 200 exposed by the pattern, and thermal oxidation. A LOCOS type field oxide film can be formed.

Next, a gate insulating material such as silicon oxide and a gate electrode forming material such as polysilicon are deposited on the entire surface of the semiconductor substrate 200, and then the gate insulating layer 262 and the gate electrode 264 using a photolithography process. To form a gate pattern.

Next, N + type impurity ions are implanted into the exposed P-type body region 220 and the drift region 230 to form the source region 270 and the drain region 280 to a predetermined depth.

A source contact region 272 formed by implanting P + type impurity ions adjacent to the source region 270 may be additionally formed.

As described above, the semiconductor device manufacturing method of FIG. 2A to FIG. 2C further forms an NBL region 240 under the N well region 205 which is a drain region of a low side LDMOS. It can be secured.

In the above-described LDMOS transistor, when a bias is applied to the drain region 280, the depletion region extends from the drift region 230, thereby greatly expanding the depletion region, thereby injecting a strong electric field formed in the edge portion of the gate electrode. This greatly improves the breakdown voltage.

2D is a graph showing the characteristics of a breakdown voltage of a conventional semiconductor device and a breakdown voltage of a semiconductor device of the present invention.

It can be seen that the breakdown voltage B of the present invention is higher than the conventional breakdown voltage A. FIG.

3A to 3C are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

As shown in FIG. 3A, an epitaxial layer P-EPI is formed on the semiconductor substrate 300, and an N well region HVNWELL 305 is formed in the epitaxial layer P-EPI.

For example, after an epitaxial layer is grown on the semiconductor substrate 300, the epitaxial layer is lightly doped with boron as a p-type impurity.

A first mask (not shown) for forming an active region is formed on the semiconductor substrate 300 by using photolithography, and an N-type impurity (eg, phosphorus phosphorus)) may be implanted into the epitaxial layer with high energy to form an N well region 305. In this case, additional impurity implantation may be performed to meet the threshold voltage of the cell as needed.

Next, impurity ions are implanted into a portion of the semiconductor substrate 300 to form the P-type body region 320 and the drift region 330 spaced by a predetermined interval.

First, an N-type impurity ion, for example, phosphorus ion, is implanted into the entire surface of the exposed semiconductor substrate 300 and then an impurity diffusion process is performed to form the drift region 330.

Subsequently, P-type impurity ions, for example boron (B) ions, are ion-implanted using a predetermined ion implantation mask (not shown) to form the P-type body region 320.

An N-drain extension region 340 may be formed on the surface of the semiconductor substrate between the N well region 301 and the P-type body region 220.

A P-drain extension 350 is formed under the P-type body region 320 and the N-drain extension region 340.

Next, the P well region 360 is formed on the other side of the N well region 305 by a predetermined interval.

As shown in FIG. 3B, an N-buried layer (NBL) region is formed at a predetermined position under the N well region HVNWELL 205. The NBL region 370 is formed by implanting an ion implantation mask (not shown) Phosphorous ions formed using a photolithography process.

One end of the NBL region 370 is positioned away from the P-type body region 220 in the lateral direction, and the other end thereof is formed to be adjusted to extend to a lower portion of the field insulating layer to be described later. In the longitudinal direction, it may be formed to be located under the bottom of the drain region.

As shown in FIG. 3C, field oxide films 370 and 375 are formed on a portion of the semiconductor substrate 300.

The field oxide films 370 and 375 form a silicon oxide film and a silicon nitride film pattern (not shown) on the semiconductor substrate 300, ion implantation of oxygen on the surface of the semiconductor substrate 300 exposed by the pattern, and thermal oxidation. A LOCOS type field oxide film can be formed.

Next, a gate insulating material such as silicon oxide and a gate electrode forming material such as polysilicon are deposited on the entire surface of the semiconductor substrate 300, and then a gate pattern including the gate insulating layer and the gate electrode using a photolithography process ( 380).

Next, N + type impurity ions are implanted on the exposed P-type body region 320 and the drift region 330 to form the source region 390 and the drain region 395 to a predetermined depth.

Next, a P + type impurity ion is implanted into the surface of the semiconductor substrate 300 spaced apart from the P well region 360 by a predetermined distance to form the substrate contact region 400.

As described above, the semiconductor device manufacturing method of FIG. 3A to FIG. 3C further includes forming an NBL region 370 under an N well region 305 which is a drain region of a low side LDMOS, thereby providing current characteristics of a transistor. And pressure resistance characteristics can be improved.

In the above-described LDMOS transistor, when a bias is applied to the drain region 395, the depletion region extends from the drift region 330, thereby greatly expanding the depletion region, thereby injecting a strong electric field formed at the edge portion of the gate electrode. This greatly improves the breakdown voltage.

3D is a graph showing the characteristics of a breakdown voltage of a conventional semiconductor device and a breakdown voltage of a semiconductor device of the present invention.

It can be seen that the breakdown voltage of the present invention is higher than the conventional breakdown voltage.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a cross-sectional view of a general semiconductor device.

2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.

Claims (6)

Forming an N-type well in a predetermined region of the epitaxial layer (P-EPI) formed in the semiconductor substrate; Forming a drift region on a surface of the semiconductor substrate in the N-type well, and forming a P-type body region spaced apart from the drift region by a predetermined distance in the epitaxial layer; Forming an N-buried layer (NBL) region at a predetermined position under the N-type well; Forming an isolation region on an upper surface of the N-type well; Forming a gate pattern on a portion of the N-type well and the epitaxial layer; And And forming a source region and a drain region in the P-type body region and the drift region, respectively. The method of claim 1, One end of the NBL region is positioned away from the P-type body region in the lateral direction, and is positioned below the field insulating layer, and the other end is formed to extend to the lower portion of the drain region, which will be described later. A method of manufacturing a semiconductor device, characterized in that formed to be located below the bottom. The method of claim 1, And forming an NBL region under the N well region, which is the drain region of the low side LDMOS transistor. Forming an N well region in the semiconductor substrate; Forming a P-type body region on a portion of the semiconductor substrate and forming a drift region spaced apart from the P-type body region by a predetermined distance in the N well region; Forming an N-drain extension region on the surface of the semiconductor substrate between the N well region and the P-type body region; Forming a P-drain extension region under the P-type body region and an N-drain extension region; Forming a P well region in the semiconductor substrate to be spaced apart from the N well region by a predetermined distance; Forming an N-buried layer (NBL) region at a predetermined position below the N well region; Forming device isolation regions on surfaces of the N-type wells and the semiconductor substrate; Forming a gate pattern on the N-drain extension region; And And forming a source region and a drain region in the P-type body region and the drift region, respectively. The method of claim 4, wherein One end of the NBL region is located away from the P-type body region in the lateral direction, and the other end thereof extends to a lower portion of the field insulating layer, which will be described later, and is formed to be located below the bottom of the drain region in the longitudinal direction. A method of manufacturing a semiconductor device. The method of claim 4, wherein And forming an NBL region below the N well region of the low side LDMOS transistor.

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