KR20110121528A - Output driver and semiconductor device including same - Google Patents

Abstract

The output driver of the present invention includes a pull-up signal generator for adjusting the pulse width of the first data and outputting it as a pull-up free drive signal, a pull-down signal generator for adjusting the pulse width of two data and outputting it as a pull-down free drive signal, and a pull-up free drive. A pull-up pre-driver section receiving a signal and generating a pull-up main drive signal, a pull-down pre-driver section receiving a pull-down main drive signal and generating a pull-down main drive signal, a pull-up main driver section taking up an output node according to the pull-up main drive signal; And a second driver unit configured to discharge the output node according to the pull-down main drive signal.

Description

Output driver and semiconductor device including the same {Outputting Driver and Semiconductor Apparatus with the same}

The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an output driver.

1 is a circuit diagram of an output driver according to the prior art. The output driver according to the related art includes a pull-up signal generator 10, a pull-down signal generator 20, a pull-up pre-driver 30, a pull-down pre-driver 40, a pull-up main driver 50a and a pull-down main driver. The part 60a is included.

The pull-up signal generator 10 may receive a first data rdata, generate a pull-up pre-drive signal pup, and may include an inverter.

The pull-down signal generator 20 may receive the second data fdata and generate a pull-down free drive signal pdn, and may include an inverter.

The pull-up pre-driver unit 30 receives a pull-up pre-drive signal pup and generates a pull-up main drive signal up. The pull-up main drive signal up generated by the pull-up pre-driver unit 30 is a signal whose slew rate and driving force are adjusted to drive the pull-up main driver unit 50a. Pull-up pre-driver unit 30 may be configured to include an inverter that can vary the driving force by the fuse option or the like.

The pull-down pre-driver unit 40 receives the pull-down main drive signal pdn and generates a pull-down main drive signal dn. The pull-down main drive signal dn generated by the pull-down pre-driver unit 40 is a signal whose slew rate and driving force are adjusted to drive the pull-down main driver unit 60a. Pull-down pre-driver unit 40 may be configured to include an inverter that can vary the driving force by the fuse option.

The pull-up main driver unit 50a occupies the output node no in response to the pull-up main drive signal up. The pull-up main driver unit 50a may include a PMOS transistor P.

The pull-down main driver 60a discharges the output node no in response to the pull-down main drive signal dn. The pull-down main driver unit 60a may include an NMOS transistor N.

The output driver according to the prior art uses a method of adjusting the slew rate of the pull-up main drive signal and the pull-down main drive signal (up, dn) to adjust the slew rate of the output signal (out). do. The slew rates of the pull-up main drive signal and the pull-down main drive signal (up, dn) are configured by including the inverter capable of varying the driving power by the pull-up pre-driver section 30 and the pull-down pre-driver section 40 by a fuse option or the like. Adjust. When the slew rate of the output signal (out) is checked and the driving force of the pull-up pre-driver unit 30 and the pull-down pre-driver unit 40 is changed according to the confirmed result, the slew rate of the main drive signal up can be adjusted. have. However, the method of controlling the slew rate of the output signal out by adjusting the slew rate of the main drive signals up and dn used in the output driver used in the related art is to adjust the slew rate of the output signal out. The disadvantage is that the slew rate of the main drive signals up, dn, which must be changed for the sake, is greater than the change in the slew rate of the output signal out. This means that the rising time and the falling time of the main drive signal up, dn must be able to change to be long enough to give a sufficient change in the slew rate of the output signal out. In extreme cases, the main drive signal (up, dn) may not fully swing from the supply voltage level to the ground voltage level, resulting in jitter due to inter symbol interference (ISI) depending on the data pattern. . This problem leads to degradation of timing characteristics of the output signal and generation of skew between the data pads DQ.

2 is a block diagram of a semiconductor device including an output driver according to the prior art. The semiconductor device illustrated in FIG. 2 includes a pull-up signal generator 10, a pull-down signal generator 20, a pull-up pre-driver 30, a pull-down pre-driver 40, a pull-up driver 50b, and a pull-down driver. 60b, the data determination unit 70 and the impedance correction signal generator 80 are included.

The semiconductor device shown in FIG. 2 can output data in a configuration similar to that of the output driver according to the related art shown in FIG. 1, and further includes a data determination unit 70 and an impedance correction signal generator 80. On Die Terminaton operation is also configured.

The pull-up signal generator 10 may receive a first data rdata, generate a pull-up pre-drive signal pup, and may include an inverter like the pull-up signal generator 10 shown in FIG. 1.

The pull-down signal generator 20 receives the second data fdata to generate a pull-down free drive signal pdn, and may include an inverter like the pull-down signal generator 20 illustrated in FIG. 1.

The pull-up pre-driver unit 30 receives a pull-up pre-drive signal pup and generates a pull-up main drive signal up. The pull-up main drive signal up generated by the pull-up pre-driver unit 30 is a signal whose slew rate and driving force are adjusted to drive the pull-up driver unit 50b. The pull-up pre-driver unit 30 may include a plurality of inverters connected in parallel as in the pull-up pre-driver unit 30 shown in FIG. 1 and varying driving power by a fuse option.

The pull-down pre-driver unit 40 receives the pull-down main drive signal pdn and generates a pull-down main drive signal dn. The pull-down main drive signal dn generated by the pull-down pre-driver unit 40 is a signal whose slew rate and driving force are adjusted to drive the pull-down driver unit 60b. The pull-down pre-driver unit 40 may include a plurality of inverters connected in parallel as in the pull-down pre-driver unit 40 shown in FIG.

The pull-up driver unit 50b occupies the output node no in response to the pull-up main drive signal up. In addition, the pull-up driver 50b adjusts the driving force and the internal impedance in response to the first impedance calibration signal pcode.

The pull-down driver unit 60b discharges the output node no in response to the pull-down main drive signal dn. In addition, the pull-down driver 60b adjusts the driving force and the internal impedance in response to the second impedance calibration signal ncode.

The data determiner 70 generates the first data rdata and the second data fdata in response to the ODT enable signal odten, the first source signal RDO, and the second fourth source signal FDO. . The data determining unit 70 and the ODT enable signal odten control the first data rdata and the second data fdata so that the semiconductor device shown in FIG. 2 performs an on die termination operation. You can do that. The detailed configuration of the data determination unit 70 and the on die termination operation according to the ODT enable signal odten will be described below with reference to FIG. 4.

The impedance calibration signal generator 80 checks the impedance value of the external resistor Rz, which is a resistor having a very small error connected to the ZQ pad, and according to the result, the first impedance calibration signal pcode and the second impedance calibration signal. produces (ncode) The first impedance calibration signal pcode and the second impedance calibration signal ncode are input to the pull-up driver unit 50b and the pull-down driver unit 60b, respectively, to form the pull-up driver unit 50b and the pull-down driver unit 60b. This signal adjusts driving force and internal impedance.

ZQ calibration refers to a process of generating pull-up and pull-down codes that change according to PVT changes, wherein the pull-up and pull-down codes generated as a result of impedance calibration, that is, first and second impedance calibration signals pcode and ncode ) To adjust the resistance value of the on-die termination device (in the case of a memory device, the termination resistance value of the output driver side or the termination resistance value of the input buffer side, see FIG. 3). The first and second impedance calibration signals pcode and ncode are signals that may vary in number depending on the semiconductor device, and are generally composed of 3 to 6 bits in the case of a semiconductor memory device (6 bits in a DDR3 DRAM). For ease of explanation, in the present specification, a case in which the first and second impedance correction signals pcode and ncode are configured with 3 bits will be described as an example.

The semiconductor device of the related art shown in FIG. 2 operates in a data output mode or an on die termination mode in response to an ODT enable signal odten. The data output mode is a mode in which the semiconductor device outputs data, and in the on die termination mode, the semiconductor device simultaneously charges and discharges the output node no, thereby outputting the output node in a high impedance (Hi-Z) state. It is a mode that fixes the voltage of no) to a specific level and prevents the end reflection of the signal when the input driver sharing the data pad DQ receives data through the data pad DQ.

When the ODT enable signal odten is deactivated, the semiconductor device operates in the data output mode, and the semiconductor device occupies the output node no in response to the first source signal RDO and the second source signal FDO. Alternatively, the output signal is output to the data pad DQ by discharge. In this case, the data determiner 70 generates the first source signal RDO and the second source signal FDO as first data rdata and second data fdata, respectively.

When the ODT enable signal odten is activated, the semiconductor device is operated in an on die termination mode, and the semiconductor device is output node no regardless of the first source signal RDO and the second source signal FDO. Charge and discharge at the same time. This results in an on die termination effect on the output node no. In this case, the data determination unit 70 may collect the first data rdata and the second data fdata so that the pull-up driver 50b and the pull-down driver 60b may simultaneously occupy and discharge the output node no. Set and print. In addition, in order to maximize the on-die termination effect on the output node no, the pull-up current of the pull-up driver unit 50b and the pull-down current of the pull-down driver unit 60b must match each other. To this end, the pull-up driver unit 50b and the pull-down driver unit 60b may respectively output the first impedance calibration signal pcode <0: 3> and the second impedance calibration signal ncode < 0: 2>) and adjust the driving force to match each other.

3 is a circuit diagram of the pull-up driver unit 50b and the pull-down driver unit 60b shown in FIG. 2. The pull-up driver unit 50b is configured such that two PMOS transistor groups connected in series are connected in parallel to three pairs. In the pull-up driver unit 50b shown in FIG. 3, the three PMOS transistors 51, 53, and 55 positioned on the upper side are turned on in response to the pull-up main drive signal up. In addition, the three PMOS transistors 52, 54, and 56 positioned on the lower side connected in series with the three PMOS transistors 51, 53, and 55 of the upper side may be configured to have the respective first impedance correction signals pcode <0: 2>. Turn on in response to the bit. In addition, three pairs of parallel connected PMOS transistor groups are connected to an output node no through a resistor 57. The pull-up driver unit 50b configured as shown in FIG. 3 occupies the output node no according to the pull-up main drive signal up, and its driving force, that is, the charge current for the output node no, is determined by the first impedance correction signal ( pcode <0: 2>).

The pull-down driver unit 60b includes a plurality of NMOS transistors and may be configured similarly to the pull-up driver unit 50b. The pull-down driver unit 60b is configured such that two NMOS transistor groups connected in series are connected in parallel to three pairs. In the pull-down driver unit 60b shown in FIG. 3, the three NMOS transistors 63, 65, and 67 located below are turned on in response to the pull-down main drive signal dn. In addition, the three PMOS transistors 62, 64, and 66 positioned in series with the lower three NMOS transistors 63, 65, and 67, respectively, are connected to the second impedance correction signal ncode <0: 2>. Turn on in response to the bit. In addition, three pairs of parallel connected NMOS transistor groups are connected to an output node no through a resistor 58. The pull-down driver 60b configured as shown in FIG. 3 discharges the output node no according to the pull-down main drive signal dn, and its driving force varies according to the second impedance correction signal ncode <0: 2>.

In this manner, the pull-up driver 50b and the pull-down driver 60b may use a termination resistance value, that is, driving force, in response to the first impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2>. Adjust to match each other's driving force.

FIG. 4 is a circuit diagram of the data determination unit 70 shown in FIG. 2. The data determination unit 70 includes a first data generation unit 71 and a second data generation unit 72.

The first data generator 71 includes a PMOS transistor 71-2 and an NMOS transistor 71-3 connected in an inverter configuration and turned on by the first source signal RDO, respectively. In addition, the PMOS transistor 71-2 is connected to the power supply voltage Vcc and connected in series with the PMOS transistor 71-1 activated by the ODT enable signal odten, thereby forming the PMOS transistor 71-1. Through this, the current path from the power supply voltage is formed. In addition, the NMOS transistor 71-3 is connected in series with the NMOS transistor 71-4 connected to the ground voltage Vss and activated by the inverted signal odtenb of the ODT enable signal. 71-4) forms a current path to ground voltage. The PMOS transistor 71-5 is activated by the inverted signal odtenb of the ODT enable signal, so that the PMOS transistor 71-2 and the NMOS transistor 71-3 are common from the power supply voltage Vcc. Form a current path to the connected node 307. The inverter 71-6 inverts the voltage of the node 307 and outputs the first data rdata. When the ODT enable signal odten is deactivated to a low level, the PMOS transistor 71-5 is turned off and the PMOS transistor 71-1 and the NMOS transistor 71-4 are turned on. Thus, the PMOS transistor 71-2 and the NMOS transistor 71-3 perform an inverter operation on the first source signal RDO. Therefore, when the ODT enable signal odten is deactivated to the low level, the first data generator 71 outputs the first source signal RDO as the first data rdata. Conversely, when the ODT enable signal odten is activated at a high level, the PMOS transistor 71-5 is turned on and the PMOS transistor 71-1 and the NMOS transistor 71-4 are turned off to make the PMOS. The transistor 71-2 and the NMOS transistor 71-3 do not form a current path to the node 307. A charge operation is performed from the power supply voltage to the node 307 through the PMOS transistor 71-5. Therefore, when the ODT enable signal odten is activated at the high level, the first data generator 71 outputs the first data rdata at the low level.

When the ODT enable signal odten is deactivated to a low level, the second data generator 72 outputs the second source signal FDO as second data fdata, and the ODT enable signal odten is high. When activated at the level, the second data generator 72 outputs the second data fdata at the high level. Since the second data generator 72 may be configured similarly to the first data generator 71 as illustrated in FIG. 4, a detailed description thereof will be omitted.

In the data output mode, when the ODT enable signal odten is deactivated to the low level, as mentioned above, the first source signal RDO is output as the first data rdata and the second source signal FDO is the second. It is output as data fdata. Accordingly, the pull-up signal generator 10, the pull-down signal generator 20, the pull-up pre-driver 30, and the pull-down pre-driver 40 shown in FIG. 2 adjust the driving force of the first data rdata. The pull-up main drive signal up is generated and the pull-down main drive signal dn is generated by adjusting the driving force of the second data fdata. In addition, the pull-up driver unit 50a and the pull-down driver unit 60 shown in FIG. 3 occupy or discharge the output node no in response to the pull-up main drive signal up and the pull-down main drive signal dn. Here, the driving force of the pull-up driver 50a and the pull-down driver 60 shown in FIG. 3 is the first impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2>, respectively. And PMOS transistors 52, 54, 56 and NMOS transistors 62, 64, 66 that are turned on in response to the &lt; RTI ID = 0.0 &gt; Here, charge and discharge operations for the output node no are alternately performed. More specifically, while the pull-up driver unit 50a is activated in response to the pull-up main drive signal up and occupies the output node no, the pull-down driver unit 60 responds to the pull-down main drive signal dn. It is deactivated and does not discharge the output node no. On the contrary, while the pull-down driver unit 60 is activated in response to the pull-down main drive signal dn and discharges the output node no, the pull-up driver unit 50a is deactivated in response to the pull-up main drive signal up and the output node. does not occupy (no)

In the on die termination mode, when the ODT enable signal odten is activated at the high level, as mentioned above, the first data rdata is output at the low level and the second data fdata is output at the high level. Accordingly, the pull-up signal generator 10, the pull-down signal generator 20, the pull-up pre-driver 30, and the pull-down pre-driver 40 shown in FIG. 2 set the pull-up main drive signal up to a low level. Generate a pull-down main drive signal dn to a high level. Accordingly, the PMOS transistors 51, 53, 55 and the NMOS transistors 63, 65, 67 of the pull-up driver unit 50a and the pull-down driver unit 60 shown in FIG. 3 are turned on. Therefore, the pull-up driver unit 50a and the pull-down driver unit 60 shown in FIG. 3 are turned on according to the first impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2>. The on-die termination operation is performed by simultaneously charging and discharging the output node no with different driving forces depending on the PMOS transistors 52, 54, 56 and the NMOS transistors 62, 64, 66. Typically, this on die termination operation is performed while the input driver sharing the DQ pad receives data.

The semiconductor device according to the related art shown in FIGS. 2 to 4 is similar to the output driver according to the prior art shown in FIG. 1. The slew rate of the pull-down main drive signal (up, dn) is adjusted. The slew rate of the pull-up and pull-down main drive signals (up, dn) includes a plurality of inverters in which the pull-up driver unit 30 and the pull-down pre-driver unit 40 are connected in parallel to vary the driving force by a fuse option or the like. Adjust by configuring. The semiconductor device according to the related art checks the slew rate of the output signal (out), and adjusts the driving force of the pull-up driver unit 30 and the pull-down pre-driver unit 40 by fuse cutting, etc. according to the result of the confirmation, and thus the main drive signal. Adjust the slew rate of (up). The plurality of inverters constituting the pull-up driver unit 30 and the pull-down driver unit 40 include a plurality of transistors for pull-up operation and a plurality of transistors for pull-down operation. It is composed. Accordingly, the semiconductor device used in the related art performs a plurality of transistors and a pull-down operation that perform pull-up operations for configuring the pull-up driver unit 30 and the pull-down driver unit 40. According to the characteristics of the plurality of transistors, the slew rate characteristic of the output signal out is greatly changed. That is, the semiconductor device used in the prior art has a disadvantage in that the characteristics change significantly according to PVT variation (Process, Voltage, Temperature Variation).

In addition, when the pull-up driver unit 30 and the pull-down pre-driver unit 40 are connected in parallel to include a plurality of inverters that can vary the driving force by the fuse option, the fuse option is a configuration that occupies a relatively large area Since it is a component, it is applied as a disadvantage to the integration of semiconductor devices.

In addition, in the semiconductor device according to the related art, the degree of change in the slew rate of the pull-up and pull-down main drive signals up and dn, which should be changed in order to adjust the slew rate of the output signal out in the data output mode, is adjusted to the output signal ( The disadvantage is that it is greater than the degree of change in the slew rate. This means that the rising time and the falling time of the main drive signal up, dn must be changed to be long enough to correct the slew rate of the output signal out according to the PVT change. In extreme cases, pull-up and pull-down main drive signals (up, dn) may fail to full swing from the supply voltage level to the ground voltage level, resulting in inter symbol interference (ISI) depending on the data pattern. This results in jitter. This problem leads to degradation of timing characteristics of the output signal and generation of skew between the data pads DQ.

The present invention provides an output driver insensitive to PVT variation of a pre-drive signal and a semiconductor device including the same.

According to an embodiment of the present invention, an output driver generates a pull-up signal generator for adjusting a pulse width of one data and outputs it as a pull-up free drive signal, and generates a pull-down signal for outputting it as a pull-down free drive signal by adjusting a pulse width of second data. A pull-up pre-driver unit receiving the pull-up pre-drive signal and generating a pull-up main drive signal, a pull-down pre-driver unit receiving the pull-down pre-drive signal and generating a pull-down main drive signal, and outputting the pull-up main drive signal A pull-up main driver unit occupying a node and a second driver unit discharging the output node according to the pull-down main drive signal.

In addition, the semiconductor device according to an embodiment of the present invention adjusts the pulse width of the first data according to the first impedance correction signal and the second impedance correction signal, outputs it as a pull-up pre-drive signal, and adjusts the pulse width of the second data. And a driver unit driving an output node in response to the pull-up free drive signal and the pull-down free drive signal, wherein the driver unit drives the output node in a data output mode. Charge and discharge at the same time.

The present invention creates the effect of making the slew rate characteristics of the output driver insensitive to PVT variations. The excessive slew rate of the main drive signal prevents the main drive signal from failing full swing from the supply voltage level to the ground voltage level. This prevents jitter due to ISI, and creates an effect of preventing timing characteristics of output signals and skew between data pads. In addition, the need for fuse options can be reduced, which is an advantage in the integration of semiconductor devices.

1 is a circuit diagram of an output driver according to the prior art,
2 is a block diagram of a semiconductor device including an output driver according to the prior art;
3 is a circuit diagram of the pull-up driver unit 50b and the pull-down driver unit 60b shown in FIG.
4 is a circuit diagram of the data determining unit 70 shown in FIG.
5 is a block diagram schematically illustrating a configuration of an output driver according to an embodiment of the present invention;
6 is a circuit diagram according to an embodiment of the output driver shown in FIG. 5;
7 is an internal / external signal waveform diagram of the output driver shown in FIG. 6;
8 is a circuit diagram of an output driver according to another embodiment of the present invention;
9 is a slew rate simulation result of the output driver according to the present invention,
10 is a block diagram schematically illustrating a configuration of an output driver according to another embodiment of the present invention;
FIG. 11 is a circuit diagram according to an exemplary embodiment 510a of the pull-up signal generator 510 shown in FIG. 10.
12 is a circuit diagram of an example of the pull-down signal generator 520 of FIG. 10.
FIG. 13 is a circuit diagram according to another embodiment 510b of the pull-up signal generator 510 shown in FIG. 10.
14A is a simulation result of slew rate versus PVT variation of an output driver according to the prior art,
14B is a simulation result showing that the output driver according to the embodiment of the present invention has a slew rate characteristic insensitive to PVT variation.

The output driver according to the related art shown in FIGS. 1 and 2 adjusts the driving force of the pull-up pre-driver unit 30 and the pull-down pre-driver unit 40 to pull-up main drive signal up and pull-down main drive signal ( The slew rate of the output signal (out) in the normal output mode is controlled by adjusting the slew rate of dn) and the slew rate of the pull-up main drive signal up and the pull-down main drive signal dn. Therefore, the slew rate characteristic of the output driver according to the prior art changes sensitively with PVT change, and jitter due to ISI may occur as the slew rates of the pull-up main drive signal up and the pull-down main drive signal dn decrease. have. In contrast, the output driver according to the present invention adjusts the pulse widths of the pull-up free drive signal pup and the pull-down free drive signal pdn to control the pull-up main drive signal pup and the pull-down main drive signal pdn. The slew rate of the output signal (out) in the normal output mode is controlled by adjusting the pulse width of the pulse width and the pulse width of the pull-up main drive signal (pup) and the pull-down main drive signal (pdn). In addition, the output driver according to the present invention may be configured to adjust the pulse width in response to an impedance calibration signal output from a ZQ calibration circuit. Therefore, the output driver according to the present invention can compensate for the slew rate characteristic that varies with the PVT change, thereby having a slew rate characteristic that is insensitive to the PVT change, and can prevent jitter due to ISI.

5 is a block diagram schematically illustrating a configuration of an output driver according to an embodiment of the present invention. The output driver includes a pull-up signal generator 100a, a pull-down signal generator 200a, a pull-up pre-driver 300, a pull-down pre-driver 400, a pull-up main driver 50a, and a pull-down main driver 60 It may be configured to include).

The pull-up signal generator 100a adjusts the pulse width of the first data rdata according to the selection signal sel and outputs the pull-up pre-drive signal pup.

The pull-down signal generator 200a adjusts the pulse width of the second data fdata according to the selection signal sel and outputs the pull-down free drive signal pdn.

The pull-up pre-driver unit 300 receives the pull-up pre-drive signal pup and generates a pull-up main drive signal up.

The pull-down pre-driver unit 400 receives the pull-down free drive signal pdn and generates a pull-down main drive signal dn.

The pull-up main driver unit 50a occupies the output node no according to the pull-up main drive signal up.

The pull-down main driver unit 60 discharges the output node no according to the pull-down main drive signal dn.

According to the prior art, the output driver occupies or discharges the output node no through the pull-up main driver unit 50a and the pull-down main driver unit 60, and the pull-up main driver unit 50a and the pull-down main driver unit. Alternately activate 60. In more detail, in the section in which the pull-up main driver 50a is activated and occupies the output node no, the pull-down main driver 60 is inactivated and does not discharge the output node no. On the contrary, the pull-up main driver 50a is deactivated and does not occupy the output node no during a period in which the pull-down main driver 60 is activated to discharge the output node no. In contrast, the output driver according to the present invention not only has a section for performing one of the charge operation and the discharge operation for the output node no, but also simultaneously performs the charge operation and the discharge operation for the output node no. It additionally has a section to perform. Simultaneously performing the charge operation and the discharge operation on the output node no adjusts the pulse widths of the first data rdata and the second data fdata to control the pull-up pre-drive signal pup and By generating the pull-down free drive signal pdn. The output driver according to the present invention can adjust the slew rate by having a section for simultaneously performing the charge operation and the discharge operation for the output node no. In more detail, it is assumed that the slew rate when only performing the charge operation on the output node no during the first interval is a, and the charge on the output node no during a portion of the first interval is assumed. And assuming that the discharge operation is performed at the same time and only the charge operation is performed on the output node no for the rest of the first interval, the absolute value of a is greater than the absolute value of b. Big. In addition, as the proportion of the portion of the first section which simultaneously performs the charge and discharge operations with respect to the output node no occupies in the first section is greater, the difference between the absolute value of a and the absolute value of b becomes larger.

In the data output mode, the first data rdata and the second data fdata are signals having the same voltage level and the same timing. In the case of the output driver according to the related art, the same signal value is input as the first data rdata and the second data rdata, and the pull-up free drive signal pup and the pull-down free drive signal generated accordingly are input. (pdn) also has the same signal value. Of course, the pull-up main drive signal up and the pull-down main drive signal dn also have the same signal value. Since the pull-up main driver unit 50a of FIG. 1 includes a PMOS transistor and the pull-down main driver unit 60 includes an NMOS transistor, the pull-up main driver signal having the same signal value ( The pull-up main driver unit 50a and the pull-down main driver unit 60, which are activated by receiving up and the pull-down main drive signal dn, are alternately activated. In other words, the pull-up main drive signal up and the pull-down main drive signal dn are not activated at the same time. In contrast, the output driver according to the present invention generates the pull-up free drive signal pup and the pull-down free drive signal pdn by adjusting the pulse widths of the first data rdata and the second data fdata. As a result, the pull-up main driver 50a and the pull-down main driver 60 may have a section in which the output node no is simultaneously occupied and discharged. The pulse width adjustment of the first data rdata and the second data fdata is adjusted according to the selection signal sel. The pulse width difference between the pull-up free drive signal pup and the pull-down free drive signal pdn is changed according to the selection signal sel, and thus the slew rate of the output signal out is also changed. A test mode signal may be used as the selection signal sel.

The output driver according to the present invention generates the pull-up free drive signal pup and the pull-down free drive signal pdn by adjusting the pulse widths of the first data rdata and the second data fdata. Adjusting the slew rate of the signal out can solve the problem occurring in the output driver according to the prior art. The main, which is a problem of a method of adjusting the slew rate of the pull-up main drive signal up and the pull-down main drive signal dn to adjust the slew rate of the output signal out according to the prior art shown in FIG. 1. The slew rate of the drive signals up and dn is excessively small to prevent full swing of the main drive signals up and dn from the power supply voltage level to the ground voltage level. Interference causes jitter, which causes degradation of the output signal timing characteristics and skew between the data pads DQ. The first data rdata and the second data The pulse width of fdata) can be adjusted to adjust the slew rate of the output signal out. This is because the slew rate of the pull-up main drive signal up and the pull-down main drive signal dn generated according to the present invention does not need to be changed to adjust the slew rate of the output signal out.

FIG. 6 is a circuit diagram according to an embodiment of the output driver shown in FIG. 5.

The output driver may include the pull-up signal generator 100a, the pull-down signal generator 200a, the pull-up pre-driver 300, the pull-down pre-driver 400, and the pull-up main driver 50a. ) And the pull-down main driver unit 60.

The pull-up main driver unit 50a may be configured like the pull-up main driver unit 50a according to the related art shown in FIG. 1. The pull-down main driver unit 60 may also be configured like the pull-down main driver unit 60 according to the related art shown in FIG. 1.

The pull-up pre-driver unit 300 may include a first inverter IV1. The first inverter IV1 is an inverter having a constant driving force. Unlike the pull-up pre-driver unit 30 according to the related art, the pull-up pre-driver unit 300 does not need to include an inverter capable of varying driving force with a fuse option. As described above, the output driver according to the present invention adjusts the pulse widths of the first data rdata and the second data fdata in the pull-up signal generator 100a and the pull-down signal generator 200a. This is because the pulse width of the output signal out is adjusted by generating the pull-up free drive signal pup and the pull-down free drive signal pdn. However, if the pull-up pre-driver unit 300 includes a driving force adjusting element (for example, an inverter capable of varying driving force with a fuse option), the pulse width of the output signal (out) can be adjusted in more detail. Therefore, as shown in FIG. 6, the configuration of the pull-up pre-driver unit 300 and the pull-down pre-driver unit 400 to be described below as an inverter having a constant driving force is not presented as an essential element for implementing the present invention. It must be understood.

The pull-down pre-driver unit 400 may be configured in the same manner as the pull-up pre-driver unit 300, and may include a second inverter IV2. Detailed description will be omitted.

6, when the selection signal sel is activated, the pull-up signal generator 100a adjusts the pulse width of the first data rdata and outputs the pull-up pre-drive signal pup. When the signal sel is inactivated, the output signal is output as the pull-up pre-drive signal pup without adjusting the pulse width of the first data rdata.

The pull-up signal generator 100a includes a first delay signal generator 110a and a first pulse controller 120.

The first delay signal generator 110a delays the first data rdata when the selection signal sel is activated and outputs the first delay signal d1 when the selection signal sel is inactivated. The first delay signal d1 is set to a specific voltage level and output.

The first pulse controller 120 receives the first data rdata and the first delay signal d1 and the first data rdata when the first delay signal d1 is at the specific voltage level. Output as the pull-up pre-drive signal pup without adjusting the pulse width of the signal, and if the first delay signal d1 is not at the specific voltage level, the pulse width of the first data rdata is adjusted to adjust the pull-up free signal. It outputs as a drive signal pup. The degree to which the pulse width is adjusted depends on the time when the first delay signal d1 is delayed with respect to the first data rdata.

The first delay signal generator 110a includes a first mode selector 111 and a first delay unit 112. The first mode selector 111 outputs the first data rdata as the first mode signal m1 when the selection signal sel is activated and the first mode when the selection signal sel is deactivated. The signal m1 is set to a specific voltage level and output. The first delay unit 112 delays the first mode signal m1 and outputs the first delay signal d1 as the first delay signal d1. When the selection signal sel is activated, the first mode selector 111 outputs the first data rdata as the first mode signal m1, and the first delay unit 112 outputs the first signal. Since the first mode signal m1 is delayed and output as the first delay signal d1, when the selection signal sel is activated, the first delay signal d1 is a signal in which the first data rdata is delayed. to be. In addition, when the selection signal sel is inactivated, the first mode selector 111 sets and outputs the first mode signal m1 to a specific voltage level, and the first delay unit 112 outputs the first mode. Since the signal m1 is delayed and output as the first delay signal d1, the first delay signal d1 is the specific voltage level when the selection signal sel is inactivated.

The first mode selector 111 may include a first tri-state inverter (TIV1, Tri-State Inverter), a third inverter (IV3), and a fixed NMOS transistor (N2). The third inverter IV3 inverts and outputs the selection signal sel. The first tri-state inverter TIV1 receives the first data rdata as an input terminal, receives the selection signal sel as an NMOS input terminal, and outputs the inverted signal of the selection signal sel. It is inputted to the input stage. The fixed NMOS transistor N2 is connected between the output terminal of the first tri-state inverter TIV1 and a ground voltage to receive an inverted value of the selection signal sel. When the selection signal sel is activated to a high level, the first mode selector 111 activates the first tri-state inverter TIV1 and turns off the fixed NMOS transistor N2 to turn the first data on. Inverting and outputting rdata as the first mode signal m1, and conversely, when the selection signal sel is inactivated to a low level, the first tri-state inverter TIV1 is inactivated and the fixed NMOS transistor N2. ) Is turned on to set and output the first mode signal m1 to a high level.

As described above, the first delay unit 112 delays the first mode signal m1 and outputs the first delay signal d1 as the first delay signal d1. The first delay unit 112 may be configured as a general delay inverter DIV1. Since the pulse width change of the pull-up pre-drive signal pup is determined according to the delay time of the first delay unit 112, the first delay unit 112 may be converted into the first mode signal m1 according to a person skilled in the art. ) May be designed to delay a predetermined time, or may be designed to variably delay the first mode signal m1 using a fuse option or the like.

The first pulse controller 120 may include a combination NAND gate ND1. The combined NAND gate ND1 receives the first data rdata and the first delay signal d1 to perform a NAND operation to generate the pull-up free drive signal pup. When the first delay signal d1 is at a high level due to the nature of the NAND operation, the combination NAND gate ND1 inverts the first data rdata and outputs the inverted first data rdata. Accordingly, when the first delay signal d1 is at a high level, the first pulse controller 120 generates and outputs the pull-up pre-drive signal pup without adjusting the pulse width of the first data rdata. When the selection signal sel becomes low level and the delayed signal of the first data rdata is input to the combination NAND gate ND1 as the first delay signal d1, the combination NAND gate ND1 is NAND. According to an operation, the pull-up pre-drive signal is generated in a form in which the high level pulse width of the first data rdata1 is narrowed. In this case, the width of the narrowing pulse is different depending on the time when the first delay signal d1 is delayed compared to the first data rdata.

6, when the selection signal sel is activated, the pull-down signal generator 200a adjusts the pulse width of the second data fdata and outputs the pull-down free drive signal pdn. When the signal sel is inactivated, the signal sel is output as the pull-down free drive signal pdn without adjusting the pulse width of the second data fdata.

The pull-down signal generator 200a includes a second delay signal generator 210a and a second pulse controller 220.

The second delay signal generator 210a delays the second data fdata when the selection signal sel is activated and outputs the second delay signal d2 when the selection signal sel is inactivated. The second delay signal d2 is set to a specific voltage level and output.

The second pulse controller 220 receives the second data fdata and the second delay signal d2 and the second data fdata when the second delay signal d2 is at the specific voltage level. The pull-down free drive signal pdn is output without adjusting the pulse width of the second delay signal d2 if the second voltage fdata is not the specific voltage level. It outputs as a drive signal pdn. The degree to which the pulse width is adjusted depends on the time delay for the second delay signal d2 to the second data fdata.

The second delay signal generator 210a includes a second mode selector 211 and a second delay unit 212. The second mode selector 212 outputs the second data fdata as the second mode signal m2 when the selection signal sel is activated and the second mode when the selection signal sel is deactivated. The signal m2 is set to a specific voltage level and output. The second delay unit 212 delays the second mode signal m2 and outputs the second delay signal d2 as the second delay signal d2. When the selection signal sel is activated, the second mode selector 211 outputs the second data fdata as the second mode signal m2, and the second delay unit 212 outputs the second signal. Since the second mode signal m2 is delayed and output as the second delay signal d2, when the selection signal sel is activated, the second delay signal d2 is a signal in which the second data fdata is delayed. to be. In addition, when the selection signal sel is inactivated, the second mode selector 211 sets and outputs the second mode signal m2 to a specific voltage level, and the second delay unit 212 outputs the second mode. Since the signal m2 is delayed and output as the second delay signal d2, the second delay signal d2 is the specific voltage level when the selection signal sel is inactivated.

The second mode selector 211 may include a second tri-state inverter TIV2, a fourth inverter IV4, and a fixed PMOS transistor P2. The fourth inverter IV4 inverts and outputs the selection signal sel. The second tri-state inverter TIV2 receives the second data fdata as an input terminal, receives the selection signal sel as an NMOS input terminal, and outputs the inverted signal of the selection signal sel. It is inputted to the input stage. The fixed PMOS transistor P2 is connected between the output terminal of the second tri-state inverter TIV2 and the ground voltage to receive the selection signal sel. When the selection signal sel is activated to a high level, the second mode selector 211 opens the second tri-state inverter TIV2 and turns off the fixed PMOS transistor P2 to turn off the second data. (fdata) is outputted as the second mode signal m2, on the contrary, when the selection signal sel is inactivated to a low level, the second tri-state inverter TIV2 is closed and the fixed PMOS transistor P2 is closed. When turned on, the second mode signal m2 is set to a low level and output.

As described above, the second delay unit 212 delays the second mode signal m2 and outputs the second delay signal d2 as the second delay signal d2. The second delay unit 212 may be configured as a general delay circuit. The pulse width change of the pull-down pre-drive signal pdn is determined according to the delay time of the second delay unit 212. Since the change in the pulse width of the pull-down free drive signal pdn changes the slew rate of the output signal out, the second delay unit 212 determines the second mode signal m2 according to the purpose of a person skilled in the art. The second mode signal m2 may be variably delayed by designing a time delay or a fuse option.

The second pulse controller 220 may include a combination NOR gate NR1. The combined NOR gate NR1 receives the second data fdata and the second delay signal d2 and performs a NOR operation to generate the pull-down free drive signal pdn. When the second delay signal d2 is at a low level due to the characteristics of the NOR operation, the combination NOR gate NR1 inverts and outputs the second data fdata. Therefore, when the second delay signal d2 is at the low level, the second pulse controller 220 outputs the pull-down free drive signal pdn without adjusting the pulse width of the second data rdata. When the selection signal sel becomes high level and the delayed signal of the second data fdata is input to the combination NOR gate NR1 as the second delay signal d2, the combination NOR gate NR1 is NOR. The pull-down free drive signal pdn is generated in a form in which the high level pulse width of the second data fdata1 is widened according to the operation. In this case, the width of the widened pulse is different depending on the time when the second delay signal d2 is delayed compared to the second data fdata.

When the selection signal sel is inactivated, the pull-up signal generator 100a and the pull-down signal generator 200a shown in FIG. 6 may pulse the first data rdata and the second data fdata. The pull-up free drive signal pup and the pull-down free drive signal pdn are generated without adjusting the width. In this case, the slew rate of the output signal out is determined according to the driving force of the pull-up pre-driver 300 and the pull-down pre-driver 400 like the output driver according to the prior art. On the contrary, when the selection signal sel is activated, the pull-up signal generator 100a and the pull-down signal generator 200a may adjust pulse widths of the first data rdata and the second data fdata. The pull-up free drive signal pup and the pull-down free drive signal pdn are generated. In this case, unlike the output driver according to the related art, the slew rate of the output signal out is determined according to the pulse widths of the pull-up free drive signal pup and the pull-down free drive signal pdn. This function can be easily used in the development process of the semiconductor device. In the development of the semiconductor device, the slew rate of the output signal (out) may be different from the design value and the post-production result. After production, the slew rate of the output signal (out) is checked, and the selected signal (sel) is set to be activated or deactivated depending on whether the confirmed result conforms to the design value. You can do that.

7 is generated by the first data rdata and the second data fdata and the pull-up signal generator 100a and the pull-down signal generator 200a input to the output driver shown in FIG. 6. The waveform diagram of the pull-up free drive signal pup and the pull-down free drive signal pdn is shown.

When the selection signal sel is activated, the pull-up pre-drive signal pup generated by the pull-up signal generating unit 100a is inverted and inverted in a high level pulse width of the first data rdata. Is generated. The size of the narrowed pulse width depends on the degree of delay of the first delay unit 112.

When the selection signal sel is activated, the pull-down free drive signal pdn generated by the pull-down signal generator 200a has a high pulse width of the second data fdata and is inverted. Is generated. The magnitude of the widened pulse width depends on the degree of delay of the second delay unit 212.

Unlike the first data rdata and the second data fdata having the same voltage level and the same pulse width as described above, the pull-up free drive signal pup has a lower logical value than the first data rdata. The pulse width of N is narrow and the pull-down free drive signal pdn has a wider pulse width with a lower logic value than that of the second data rdata. Therefore, the pull-up free drive signal pup and the pull-down free drive signal pdn have different values, that is, in the waveform diagram of FIG. 7, the pull-up free drive signal pup is at a high level and the pull-down free drive. The signal pdn has a low level section (hereinafter referred to as section (a)). In the section (a), the pull-up main driver unit 50a and the pull-down main driver unit 60 simultaneously charge and discharge the output node no. Section (b) is a section in which both the pull-up pre-drive signal pup and the pull-down free drive signal pdn are low level, and the pull-up main driver 50a does not occupy the output node no. The pull-down main driver 60 is a section for discharging the output node (no). The section (c) is a section in which both the pull-up free drive signal pup and the pull-down free drive signal pdn are high level, and the pull-up main driver unit 50a occupies the output node no, and the pull-down The main driver unit 60 is a section in which the output node no is not discharged. As such, a section (a) for simultaneously charging and discharging the output node no exists between the interval (b) for discharging the output node no and the interval (c) for occupying the output node no. The slew rate of the output signal out is adjusted.

8 is a circuit diagram of an output driver according to another embodiment of the present invention.

The output driver includes a pull-up signal generator 100b, a pull-down signal generator 200b, a pull-up pre-driver 300, a pull-down pre-driver 400, a pull-up main driver 50a, and a pull-down main driver 60 ).

The pull-up signal generator 100b receives the first data rdata and adjusts the pulse width to output the pull-up pre-drive signal pup.

The pull-down signal generator 200b receives the second data fdata and adjusts the pulse width to output the pull-down free drive signal pdn.

The pull-up pre-driver unit 300 receives the pull-up pre-drive signal pup and generates a pull-up main drive signal up. The pull-up pre-driver unit 300 may be configured in the same manner as the pull-up pre-driver unit 300 shown in FIG. 6.

The pull-down pre-driver unit 400 receives the pull-down free drive signal pdn and generates a pull-down main drive signal dn. The pull-down pre-driver unit 400 may be configured in the same manner as the pull-down pre-driver unit 400 shown in FIG. 6.

The pull-up main driver unit 50a occupies the output node no according to the pull-up main drive signal up. The pull-up main driver 50a may be configured in the same manner as the pull-up main driver 50a illustrated in FIG. 6.

The pull-down main driver unit 60 discharges the output node no according to the pull-down main drive signal dn. The pull-down main driver unit 60 may be configured in the same manner as the pull-down main driver unit 60 shown in FIG. 6.

The output driver shown in FIG. 8 operates in the same way as the operation when the selection signal sel is activated in the output driver shown in FIG. The output driver generates the pull-up free drive signal pup and the pull-down free drive signal pdn by adjusting the pulse widths of the first data rdata and the second data fdata, respectively, The slew rate of the output signal out is determined according to the pulse width of the drive signal pup and the pull-down free drive signal pdn. However, unlike the output driver illustrated in FIG. 5, the output driver illustrated in FIG. 8 does not receive the selection signal sel. The pull-up pre-drive signal without adjusting or adjusting the pulse widths of the first data rdata and the second data fdata according to whether the output driver illustrated in FIG. 6 is activated. Unlike generating a pup and the pull-down free drive signal pdn, the output driver shown in FIG. 8 adjusts the pulse widths of the first data rdata and the second data fdata so as to adjust the pull-up free signal. A drive signal pup and the pull-down free drive signal pdn are generated. The output driver shown in FIG. 8 generates the pull-up free drive signal pup and the pull-down free drive signal pdn by adjusting pulse widths of the first data rdata and the second data fdata. In addition to the section for performing one of the charge and discharge operations for the output node (no), it further has a section for performing the charge and discharge operations at the same time. The output driver according to the present invention determines the slew rate of the output signal out according to how long the charge and discharge operations for the output node no are simultaneously performed.

The pull-up signal generator 100b may include a first delay signal generator 110b and a first pulse controller 120.

The first delay signal generator 110b receives the first data rdata and delays the first data rdata to output the first delay signal d11. The first delay signal generator 110b may include a general delay circuit. Since the output driver shown in FIG. 8 is changed in the pulse width of the pull-up pre-drive signal pup according to the delay time of the first delay signal generator 110b like the output driver shown in FIG. For example, the first delay signal generator 110b may be designed to delay the first data rdata by a predetermined time or to variably delay the first data rdata by a fuse option or the like.

The first pulse controller 120 receives the first data rdata and the first delay signal d11 to generate the pull-up pre-drive signal pup. The first pulse controller 120 may include a combination NAND gate ND2. Since the first delay signal d11 is a delayed signal of the first data rdata, the pull-up pre-drive signal generated by the first pulse controller 120 including the combined NAND gate ND2 is generated. The pup has a narrow pulse width of the first data rdata. As described above, the pulse width of the pull-up pre-drive signal pup depends on the time when the first delay signal d11 is delayed from the first data rdata.

The pull-down signal generator 200b includes a second delay signal generator 210b and a second pulse controller 220.

The second delay signal generator 210b receives the second data fdata and delays it, and outputs the second delay signal d2 as a second delay signal d2. The second delay signal generator 210b may include a general delay circuit. The second delay signal generator 210b may be configured such that the second delay signal generator 210b delays the second data fdata for a predetermined time in accordance with the purpose of a person skilled in the art as the first delay signal generator 110b. The second data fdata may be designed to be variably delayed by a design or a fuse option.

The second pulse controller 220 receives the second data fdata and the second delay signal d12 to generate the pull-down free drive signal pdn. The second pulse controller 220 may include a combination NOR gate NR2. Since the second delay signal d12 is a delayed signal of the second data fdata, the pull-down free drive signal generated by the second pulse controller 220 including the combined NOR gate NR2 ( pdn) is a form in which the pulse width of the second data fdata is widened. The pulse width of the pull-down free drive signal pdn depends on the time delayed by the second delay signal d12 from the second data fdata.

In comparison with the output driver illustrated in FIGS. 5 and 6, the output driver illustrated in FIG. 8 does not receive the selection signal sel, and thus the first data rdata according to the selection signal sel. ) And the pull-up free drive signal pup and the pull-down free drive signal pdn without adjusting the pulse width of the second data fdata.

As described above, the slew rate of the output signal out is determined depending on how simultaneously the pull-up driver 300 and the pull-down driver 400 charge and discharge the output node no, How simultaneously the pull-up driver 300 and the pull-down driver 400 charge and discharge the output node no depends on the pulse width of the pull-up free drive signal pup and the pull-down free drive signal pdn. Since the slew rate of the output signal out is determined by the first delay signal generator 110b and the second delay signal generator 210b, respectively, the first data rdata and the second data ( fdata) is determined by how much delay. Therefore, when the first delay signal generator 110b and the second delay signal generator 210b are configured to include a delay circuit whose delay time is adjusted by a fuse option or the like, the slew rate of the output signal (out) is adjusted. Can be.

In the output driver shown in FIG. 9, the graph shown in FIG. 6 activates the selection signal sel to adjust the pulse widths of the first data rdata and the second data fdata to pull up the pull-up. The simulation result when the free drive signal pup and the pull-down free drive signal pdn are generated. The graph also applies to the output driver shown in FIG. 9 illustrates a slew rate of the rising edge of the output signal out according to the delay times of the first delay unit 112 and the second delay unit 212 of FIG. 6. The slew rate of the falling edge is shown. As shown in FIG. 9, as the delay time of the first delay unit 112 and the second delay unit 212 increases, the slew rate of the rising edge of the output signal out and the slew of the falling edge are shown. It can be seen that the rate decreases. As described above, the output driver generates the pull-up free drive signal pup and the pull-down free drive signal pdn by adjusting the pulse widths of the first data rdata and the second data fdata. The slew rate of the output signal (out) can be adjusted.

10 is a block diagram schematically illustrating a configuration of an output driver according to another embodiment of the present invention. The output driver may include a pulse width adjusting part 500 and a driver part 600.

The pulse width adjusting part 500 adjusts the pulse width of the first data rdata according to the first impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2>. The pulse width of the second data fdata is adjusted and output as the pull-down free drive signal pdn. The degree of adjustment of the pulse width depends on the first impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2>. In the output driver illustrated in FIG. 10, like the output driver illustrated in FIGS. 5 and 8, the slew rate of the output signal out is determined according to the degree of the pulse width adjusted by the pulse width adjuster 500.

The driver unit 600 drives the output node no in response to the pull-up main drive signal up and the pull-down main drive signal dn. In addition, the driver unit 600 simultaneously charges and discharges the output node no for a predetermined time in a data output mode. In this case, the predetermined time during which the driver 600 simultaneously charges and discharges the output node no corresponds to a degree in which the pulse width control unit 500 adjusts the pulse width. The output signal no is generated by charging and discharging the output node no by the driver 600. The output signal out is output through the DQ pad.

As illustrated in FIG. 10, the pulse width adjusting unit 500 may include a pull-up signal generator 510 and a pull-down signal generator 520. The pull-up signal generator 510 may adjust the pulse width of the first data rdata according to the first impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2>. Adjust to generate a pull-up pre-drive signal (pup). The pull-down signal generator 520 may adjust the pulse width of the second data fdata according to the first impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2>. Adjust to generate a pull-down free drive signal (pdn). In order for the driver unit 600 to simultaneously charge and discharge the output node no at a predetermined time, the pull-up signal generator 510 causes the driver unit 600 to output the output node no. The pull-up pre-drive signal pup is generated to occupy longer than the pulse width of the first data rdata, and the pull-down signal generator 520 causes the driver 600 to output the output node no. Preferably, the pull-down free drive signal pdn is configured to be discharged longer than the pulse width of the second data fdata.

The driver 600 may further receive the first impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2> to perform on die termination. have. In the on-die termination mode, the driver 600 determines the charge current for the output node no according to the first impedance calibration signal pcode <0: 2>, and the second impedance calibration signal ( The discharge current for the output node no is determined according to ncode <0: 2>. As shown in FIG. 10, the driver unit 600 may include a pull-up driver unit 50b and a pull-down driver unit 60b, and the pull-up driver unit 50b and the pull-down driver unit 60b. 3 may be configured in the same manner as the pull-up driver unit 50b and the pull-down driver unit 60b shown in FIG. 3.

In addition, the driver unit 600 may further include a pre-driver unit 300, 400 as shown in FIG. The pre-drivers 300 and 400 receive the pull-up pre-drive signal pup to generate a pull-up main drive signal up, and receive the pull-down pre-drive signal pdn to receive a pull-down main drive signal dn. Create The pre-drivers 300 and 400 may include a pull-up pre-driver 300 and a pull-down pre-driver 400, and the pull-up pre-driver 300 and the pull-down pre-driver shown in FIG. 5. 400 can be configured to include. As mentioned above, the pull-up pre-driver unit 300 and the pull-down pre-driver unit 400 may include a pull-up pre-driver unit 30 and a pull-down pre-driver unit 40 according to the related art shown in FIGS. 1 and 2. Alternatively, it may be configured to have a fixed driving force because there is no need to vary the driving force. Accordingly, the pre-drivers 300 and 400 may exclude the pull-up main drive signal up and the pull-down main drive signal dn except for the pull-up free drive signal pup and the pull-down free drive signal pdn. There is no need to receive other signals to adjust the slew rate. In addition, the pull-up pre-driver unit 300 and the pull-down pre-driver unit 400 may include a driving force adjusting element such as a fuse option or may be connected to the driving force adjusting element so that the driving force does not need to be adjusted. However, when the pull-up pre-driver 300 and the pull-down pre-driver 400 include the driving force adjusting element, the slew rate of the output signal out can be adjusted in more detail. Therefore, it should be understood that the configuration of the pre-drivers 300 and 400 as inverters having a constant driving force, as shown in FIG. 10, is not presented as an essential element for implementing the present invention. However, the driving force adjusting element has a relatively large area in the semiconductor device, and in order to adjust the slew rate of the output signal out, the output driver according to the present invention uses the pre-pull drive signal and the pre-pull drive signal. Since the method of adjusting the pulse width of pdn is used, the pre-drivers 300 and 400 are preferably configured without a driving force reducing element such as a fuse option in order to efficiently use the area of the semiconductor device.

As mentioned above, in the data output mode, the pull-up driver section 50b and the pull-down driver section 60b of the output driver according to the prior art shown in FIG. 3 alternately occupy or discharge the output node no. . In more detail, in the section in which the pull-up driver unit 50b is activated and occupies the output node no, the pull-down driver unit 60b is inactivated and does not discharge the output node no. On the contrary, in the period in which the pull-down driver unit 60b is activated to discharge the output node no, the pull-up driver unit 50b is deactivated and does not occupy the output node no. In contrast, the output driver according to an embodiment of the present invention not only has a section for performing one of the charge operation and the discharge operation for the output node no in the data output mode, but also for the output node no. It further has a section for simultaneously performing the charge operation and the discharge operation. A period in which the charge operation and the discharge operation for the output node no are simultaneously performed lowers the slew rate of the output signal out. In addition, the output signal (out) increases as the interval for simultaneously performing the charge operation and the discharge operation for the output node no is larger than the interval for performing one of the charge operation and the discharge operation for the output node no. Slew rate is lower. Using this principle, the output driver according to an embodiment of the present invention adjusts the slew rate of the output signal (out) by adjusting a section for simultaneously performing the charge operation and the discharge operation for the output node (no). Can be. Further having a section for simultaneously performing the charge operation and the discharge operation for the output node (no) is the pull-up pre-drive signal by adjusting the pulse width of the first data (rdata) and the second data (fdata) It can be achieved by generating a pup and the pull-down free drive signal pdn. In addition, the degree of adjustment of the pulse width depends on the first impedance calibration signal (pcode <0: 2>) and the second impedance calibration signal (ncode <0: 2>). The slew rate to be adjusted is applied compensation for the change according to the PVT change. The first data rdata and the second data fdata used for outputting data in the data output mode are signals having the same voltage level and the same timing, that is, having the same signal value. The output driver according to the related art shown in FIG. 2 receives the first data rdata and the second data rdata having the same signal value and the pull-up pre-drive signal pup having the same signal value. And generate the pull-down free drive signal pdn, and generate the pull-up main drive signal up and the pull-down main drive signal dn having the same signal value. As shown in FIG. 1, since the pull-up driver unit 50b includes a PMOS transistor group and the pull-down driver unit 60b includes an NMOS transistor group, the pull-up driver unit 50b may have the same signal value. The pull-up driver 50b and the pull-down driver 60b, which are activated by receiving a pull-up main drive signal up and the pull-down main drive signal dn, are alternately activated. That is, in the data output mode, the pull-up main drive signal up and the pull-down main drive signal dn according to the prior art are not activated at the same time. Alternatively, the output driver according to an embodiment of the present invention adjusts the pulse widths of the first data rdata and the second data fdata so that the pull-up free drive signal pup and the pull-down free drive signal ( By generating pdn), the pull-up driver unit 50b and the pull-down driver unit 60b are simultaneously activated in the data output mode to have a section for simultaneously charging and discharging the output node no. Here, a section for simultaneously charging and discharging the output node no exists for a predetermined time between sections for alternately charging or discharging the output node no. In the data output mode, the operation of simultaneously occupying and discharging the output node no by the output driver according to the exemplary embodiment of the present invention is not maintained for the duration of the on die termination operation like the on die termination mode, and the waveform of FIG. As such, it is maintained for a certain time between the sections alternately occupying or discharging the output node no. In addition, in the data output mode, a period in which the output node no is simultaneously occupied and discharged is adjusted according to the pulse widths of the pull-up free drive signal pup and the pull-down free drive signal pdn, The degree of adjustment is adjusted according to the first and second impedance calibration signals pcode <0: 2> and ncode <0: 2>. Accordingly, the pulse width difference between the pull-up free drive signal pup and the pull-down free drive signal pdn varies according to the first and second impedance calibration signals pcode <0: 2> and ncode <0: 2>. Thus, the slew rate of the output signal out is also changed.

The output driver according to the present invention generates the pull-up free drive signal pup and the pull-down free drive signal pdn by adjusting pulse widths of the first data rdata and the second data fdata. The slew rate of the output signal out is adjusted through the pull-up free drive signal pup and the pull-down free drive signal pdn, thereby preventing a problem occurring in the output driver according to the prior art. As mentioned above, the output driver according to the related art shown in FIG. 2 has a significant change in the slew rate of the output signal out according to the PVT change. The output driver according to the related art uses a method of adjusting the slew rates of the pull-up and pull-down main drive signals up and dn to compensate for the change in the slew rate, which is the main drive signal up, The slew rate of dn) is too small to allow full swing of the main drive signal up, dn from the power supply voltage level to the ground voltage level, resulting in jitter due to ISI, resulting in the output signal out. There is a problem in that timing characteristics deteriorate and skew between data pads occurs. The output driver according to an exemplary embodiment of the present invention does not adjust the slew rates of the main drive signals up and dn, but rather adjusts the pulse widths of the pull-up free drive signal pup and the pull-down free drive signal pdn. By adjusting the slew rate of the output signal out, the slew rate of the main drive signals up and dn is set excessively low to prevent the occurrence of ISI jitter. In addition, since the pulse width is adjusted according to the first and second impedance calibration signals pcode <0: 2> and ncode <0: 2>, it is possible to compensate for a slew rate change depending on the PVT change.

In addition, a semiconductor device according to an embodiment of the present invention may include an output driver including the pulse width adjusting unit 500 and the driver unit 600 illustrated in FIG. 10, a data determination unit 70 illustrated in FIG. 10, and It may be configured to further include an impedance calibration signal generator 80. The data determiner 70 and the impedance correction signal generator 80 are the same as the data determiner 70 and the impedance correction signal generator 80 according to the related art shown in FIGS. 2 and 4. Can be configured. Therefore, detailed descriptions of the data determiner 70 and the impedance calibration signal generator 80 will be omitted.

FIG. 11 is a circuit diagram of an embodiment 510a of the pull-up signal generator 510 shown in FIG. 10.

As described above, the pull-up signal generator 510a may generate the first data rdata according to the first impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2>. Pulse width is adjusted and output as a pull-up pre-drive signal (pup). The pull-up signal generator 510a may include a first delay signal generator 511a and a first pulse controller 512a. The pull-up signal generator 510a shown in FIG. 11 generates a first delay signal d1 through the first delay signal generator 511a, and generates the first data rdata and the first delay signal. The pull-up pre-drive signal pup may be generated by adjusting a pulse width of the first data rdata by performing a NAND operation on the d1 through the first pulse controller 512a.

The first pulse controller 512a receives the first data rdata and the first delay signal d1 to generate the pull-up pre-drive signal pup. As illustrated in FIG. 11, the first pulse controller 512a may include a first NAND gate ND3 that receives the first data rdata and the first delay signal d1.

The first delay signal generator 511a may generate the first data rdata according to the first impedance correction signal pcode <0: 2> and the second impedance correction signal ncode <0: 2>. Variable delay is performed to generate the first delay signal d1. Referring to FIG. 11, the first delay signal generator 511a is configured by a series combination of two variable delay inverters 511-1 and 511-2. The first variable delay inverter 511-1 variably delays the first data rdata according to the second impedance correction signal ncode <0: 2> to change the level of the first node n1. The second variable delay inverter 511-2 receives the voltage of the first node n1 and variably delays the first impedance calibration signal pcode <0: 2> to the second node n2. The one delay signal d1 is output. In FIG. 11, the first variable delay inverter 511-1 includes a first PMOS transistor 1111, a first NMOS transistor 1112, first to third adjustable NMOS transistors 1113 to 1115, and a first variable delay inverter 511-1. 1 to 3 enable NMOS transistors 1116 to 1118. The first PMOS transistor 1111 is connected between a power supply voltage Vcc terminal and the first node n1 to receive the first data rdata. The first NMOS transistor 1112 is connected between the first node n1 and a ground terminal to receive the first data rdata. The first to third control NMOS transistors 1113 to 1115 have a common drain terminal connected to the first node n1, and the first to third enable NMOS transistors 1116 to 1118, respectively. Is connected in series. In addition, the first to third regulating NMOS transistors 1113 to 1115 receive the first data rdata in common. The first to third enable NMOS transistors 1116 to 1118 have a common source terminal connected to a ground terminal and receive respective bits of the second impedance correction signal ncode <0: 2>. That is, the first to third enable NMOS transistors 1116 to 1118 are activated according to the respective bits of the second impedance correction signal ncode <0: 2>, respectively, and the first to third control NMOS transistors, respectively. It serves as a current sink path of the transistors 1113 to 1115. According to the second impedance calibration signal ncode <0: 2>, which of the first to third enable NMOS transistors 1116 to 1118 is turned on, and the first data rdata is determined. When input to the high level, the first NMOS transistor 1112 is activated to discharge the first node n1 and is turned on according to the second impedance correction signal ncode <0: 2> to serve as a current sink path. The first to third control NMOS transistors 1113 to 1115 connected in series with the first to third enable NMOS transistors 1116 to 1118 further discharge the first node n1. Since the discharge speed of the first node n1 is changed according to the turn-on or turn-off states of the first to third regulating NMOS transistors 1113 to 1115, the second impedance calibration signal ncode <0: 2>), the rate of change of the voltage level of the first node n1 varies. That is, the first variable delay inverter 511-1 variably delays and inverts the first data rdata according to the second impedance correction signal ncode <0: 2> to the first node n1. Output The second variable delay inverter 511-2 includes a second NMOS transistor 1119, a second PMOS transistor 1120, first to third adjustable PMOS transistors 1121 to 1123, and first to third It is comprised including the enable PMOS transistors 1124-1126. The second NMOS transistor 1119 is connected between the second node n2 and the ground terminal to receive the voltage of the first node n1. The second PMOS transistor 1120 is connected between a power supply voltage Vcc terminal and the second node n2 to receive a voltage of the first node n1. Each of the first to third adjustable PMOS transistors 1121 to 1123 has a common drain terminal connected to the second node n2, and the first to third enable PMOS transistors 1124 to 1126, respectively. Is connected in series. In addition, the first to third regulating PMOS transistors 1121 to 1123 may receive a voltage of the first node n1 in common. The first to third enable PMOS transistors 1124 to 1126 have a common source terminal connected to a power supply voltage Vcc terminal and receive the first impedance calibration signals pcode <0: 2>, respectively. That is, the first to third enable PMOS transistors 1124 to 1126 are activated according to the first impedance correction signal pcode <0: 2>, respectively, to respectively the first to third adjustable PMOS transistors 1121 to 1. 1123) to supply power. That is, the second variable delay inverter 511-2 variably delays and inverts the voltage of the first node n1 according to the first impedance calibration signal pcode <0: 2> to allow the second node n2 to be inverted. ) Is output as the first delay signal d1. According to the operations of the first variable delay inverter 511-1 and the second variable delay inverter 511-2 connected in series, the first delay signal d1 is configured to convert the first data rdata into a first impedance. The signal is variable delayed according to the calibration signal pcode <0: 2>. In FIG. 10, the first and second variable delay inverters 511-1 and 511-2 may receive the first to third enable signals that receive the third impedance correction signal ncode <0: 2> of 3 bits. The NMOS transistors 1116 to 1118 and three transistors receiving the first 3-bit first impedance correction signal pcode <0: 2>, that is, the first to third enable PMOS transistors 1124 to 1126, are connected. Including configuration is shown. Here, the first impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2> are three-bit signals, which are illustrated for ease of explanation. The number of bits of the signal pcode <0: 2> and the second impedance correction signal ncode <0: 2> may be set differently. Alternatively, it is also possible to combine the n bits of the impedance correction signal according to the design of a person skilled in the art to generate an adjustment signal having a bit number smaller than n. As mentioned above, the first impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2> are illustrated in three bits for ease of explanation, and thus, the first impedance It is not intended to limit the number of bits of the calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2>. If the first and second variable delay inverters shown in FIG. 11 are configured as a general single inverter, the delay time of the first and second variable delay inverters is changed according to the PVT change, but the first impedance correction signal pcode <0: 2> and the first In FIG. 11, in which transistors turned on or turned off according to the impedance correction signal ncode <0: 2> are adjusted in parallel, in the condition that the delay time is increased according to the PVT change, a relatively large number of transistors in parallel are configured. Are turned on to reduce the delay time, and in a condition where the delay time is shortened according to the PVT change, a relatively small number of transistors in parallel are turned on to increase the delay time to compensate for the delay of the PVT change.

Referring to the circuit diagram of FIG. 11, the first variable delay inverter 511-1 configures NMOS transistors for discharging the first node n1 in parallel and the second variable delay inverter 511-2. ) Shows that the PMOS transistors occupying the second node n2 are configured in parallel connection. The PMOS transistor occupying the first node n1 includes only the first PMOS transistor 1111, and the NMOS transistor discharged from the second node n2 is the second NMOS transistor ( 1119) only. This is because the configuration of the waveform of the pull-up pre-drive signal (pup) generated by the pull-up signal generator 510a. As shown in the waveform diagram of FIG. 7, the pull-up pre-drive signal pup has a narrow pulse width of the first data rdata and is inverted. Since the first pulse controller 512a performs the NAND operation on the first data rdata and the first delay signal d1 to generate the pull-up pre-drive signal pup, the first delay signal d1 is generated. The timing of the rising edge of () determines the pulse width of the pull-up pre-drive signal (pup). The above-described configuration of the first variable delay inverter 511-1 and the second variable delay inverter 511-2 shown in FIG. 11 includes the first impedance correction signal pcode <0: 2> and the first variable delay inverter 511-2. 2 is a configuration for determining the timing of the rising edge of the first delay signal d1 according to the impedance correction signal ncode <0: 2>. Since the falling edge of the first delay signal d1 does not affect the waveform of the pull-up pre-drive signal pup, the first PMOS transistor 1111 occupies the first node n1. ) And the second NMOS transistor 1119, which discharges the second node n2, may include the first impedance correction signal pcode <0: 2> and the second impedance correction signal ncode <0: 2>. It does not need to be configured as a parallel combination of transistors that receive. Therefore, for the area efficiency, it is preferable to configure a single transistor as the first PMOS transistor 1111 and the second NMOS transistor 1119. How the first variable delay inverter 511-1 and the second variable delay inverter 511-2 delays the rising edge of the first data rdata to generate the first delay signal d1 Accordingly, the predetermined time during which the driver unit 600 simultaneously charges and discharges the output node no varies. The delay time of the rising edge of the first data rdata by the first delay signal generator 511a shown in FIG. 11 is longer than the pulse width of the first data rdata by the driver 600. The driver node 600 causes the output node to occupy the output node no, and delays the falling edge of the second data fdata by the second delay signal generator 521 shown in FIG. 12. The output node no is discharged longer than the pulse width of 2 data fdata. Accordingly, the delay time of the rising edge of the first data rdata by the first delay signal generator 511a shown in FIG. 11 and the second delay signal generator 521 to be presented in FIG. The sum of the delay times of the falling edges of two data fdata is equal to the predetermined time.

FIG. 12 is a circuit diagram of an example of the pull-down signal generator 520 of FIG. 10. As described above, the pull-down signal generator 520 may generate the second data fdata according to the first impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2>. The pulse width is adjusted and output as a pull-down free drive signal pdn. The pulldown signal generator 520 may include a second delay signal generator 521 and a second pulse controller 522. The pulldown signal generator 520 illustrated in FIG. 12 generates a second delay signal d2 through the second delay signal generator 521, and generates the second data fdata and the second delay signal. (d2) is generated by performing a NOR operation through the second pulse controller 522.

The second pulse controller 522 receives the second data fdata and the second delay signal d2 to generate the pull-down free drive signal pdn. In FIG. 12, the second pulse controller 522 may include a first NOR gate NR3 that receives the second data fdata and the second delay signal d2.

The second delay signal generator 521 delays the second data fdata according to the first impedance correction signal pcode <0: 2> and the second impedance correction signal ncode <0: 2>. To output as a second delay signal d2. The second delay signal generator 521 is illustrated in a similar configuration to the first delay signal generator 510a. The second delay signal generator 521 is composed of a combination of two variable delay inverters, like the first delay signal generator 510a. As shown in the waveform diagram of FIG. 7, the second delay signal generator 521 controls the pulse width of the second data fdata to be wider than the first delay signal generator 510 so as to widen the pull-down free drive. Generate a signal pdn. That is, it is configured to determine the falling edge timing of the second delay signal d2. The configuration and operation principle of the second delay signal generation unit 521 are symmetrical and similar to the configuration and operation principle of the first delay signal generation unit 510a, and thus a detailed description thereof will be omitted.

FIG. 13 is a circuit diagram according to another embodiment 510b of the pull-up signal generator 510 shown in FIG. 10. Unlike the pull-up signal generator 510a illustrated in FIG. 11, the pull-up signal generator 510b receives a delay enable signal enb from the first delay signal generator 511b. It further includes two transistors (Pe, Ne). The delay enable signal enb may be configured using a test mode signal as a low active signal. When the delay enable signal enb is activated, the pull-up signal generator 510b shown in FIG. 13 performs the first data rdata like the pull-up signal generator 510a shown in FIG. The pulse width is adjusted according to the impedance calibration signal pcode <0: 2> and the second impedance calibration signal ncode <0: 2> and output as the pull-up free drive signal pup. However, when the delay enable signal enb is deactivated, the pull-up signal generator 510b shown in FIG. 13 is different from the pull-up signal generator 501a shown in FIG. 11. Output as the pull-up pre-drive signal pup without adjusting the width. Unlike the first delay signal generator 511a illustrated in FIG. 11, the first delay signal generator 511b illustrated in FIG. 13 may include two transistors Pe, which receive the delay enable signal enb. Ne) additionally. The first delay signal generator 511b may apply the delay enable signal enb between the first PMOS transistor P1 and the power voltage Vcc terminal of the first delay signal generator 511a. The switch PMOS transistor 1301 further includes an input. In addition, the first delay signal generator 511b may be disposed between the fifth node n5 corresponding to the first node n1 of the first delay signal generator 511a and the ground terminal of FIG. 11. The switch NMOS transistor 1302 may further include a delay enable signal enb. When the delay enable signal enb is activated, the switch PMOS transistor 1301 is turned on and the switch NMOS transistor 1302 is turned off, so that the first delay signal generator 511b is turned on by the first delay signal. It operates in the same manner as the generation unit 511a. In contrast, when the delay enable signal enb is activated, the switch PMOS transistor 1301 is turned off and the switch NMOS transistor 1302 is turned on so that the first delay signal generator 511b is a sixth node. The voltage of n6 is changed to a low level, that is, the first delay signal d1 is fixed at a low level and output. Since the first delay signal d1 is input to the first NAND gate ND1, the first NAND gate ND1 that receives the first delay signal d1 having a low level has a characteristic of NAND operation. It acts as an inverter. Accordingly, the pull-up pre-drive signal pup becomes a signal having the same pulse width as the first data rdata. As described above, unlike the first delay signal generator 511a, the first delay signal generator 511b receives the delay enable signal enb additionally so that the pull-up signal generator 510b receives a pulse width. You can enable / disable the operation to control. The pulldown signal generator 520 also receives the delay enable signal enb additionally, that is, the second delay signal generator 511b as shown in FIG. 13. By configuring 520, the pull-down signal generator 520 may activate / deactivate an operation of adjusting the pulse width.

10 to 13, the output driver according to an embodiment of the present invention, unlike the output driver according to the prior art, adjusts the pulse width of the pull-up pre-drive signal (pup) and the pull-down free drive signal (pdn) To adjust the slew rate of the output signal out in the normal output mode, and also to the first impedance correction signal pcode <0: 2> and the second impedance correction signal ncode <0: 2>. In response, the pulse width is varied so that it has a slew rate characteristic insensitive to PVT variation.

FIG. 14A is a simulation result of slew rate versus PVT change of an output driver according to the prior art, and FIG. 14B is a simulation result showing that the output driver has a slew rate characteristic insensitive to PVT change. The bunch of dots shown in FIGS. 14A and 14B lock the supply voltage (Vcc) step by step (2.00V, 1.80V, 1.65V, 1.50V, 1.35V, and 1.20V) and process and temperature These are the results of the calculated slew rate when the is changed.

Referring to FIGS. 14A and 14B, when the slope of the slew rate changes when the power supply voltage Vcc changes according to the voltage voltage, the slope of the slew rate is lower than that of FIG. 14A. can see. As such, the output driver according to the embodiment of the present invention has a smaller slew rate change due to voltage change than the output driver of the prior art.

14A and 14B, when the degree of dispersion of the slew rate varies depending on the process and the temperature, it can be seen that the degree of dispersion of FIG. 14B is lower than that of FIG. 9A. As such, the output driver according to the embodiment of the present invention has a smaller slew rate change due to process and temperature change than the output driver of the prior art.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above are intended to be illustrative in all respects and should not be considered as limiting. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

10 / 100a / 100b / 510 / 510a / 510b: pull-up signal generator
20 / 200a / 200b / 520: Pulldown signal generator
30/300: pull-up free driver part 40/400: pull-down free driver part
50a / 50b: pull-up main driver section 60a / 60b: pull-down main driver section
70: data determining unit 71: first data generating unit
72: second data generator 80: impedance calibration signal generator
110a / 110b / 511a / 511b: first delay signal generator
111: first mode selection unit 112: first delay unit
120 / 512a / 512b: first pulse control unit
210a / 210b / 521: second delay signal generator
211: second mode selection unit 212: second delay unit
220/522: second pulse adjusting unit 500: pulse width adjusting unit
511-1: First Variable Delay Inverter 511-2: Second Variable Delay Inverter
600: driver unit

Claims (19)

A pull-up signal generator which adjusts a pulse width of the first data and outputs the pull-up free drive signal;
Pull-down signal generator for adjusting the pulse width of the second data to output as a pull-down free drive signal
A pull-up pre-driver unit configured to receive the pull-up pre-drive signal and generate a pull-up main drive signal;
A pull-down pre-driver unit configured to receive the pull-down free drive signal and generate a pull-down main drive signal;
A pull-up main driver unit occupying an output node according to the pull-up main drive signal; And
And a second driver unit configured to discharge the output node according to the pull-down main drive signal. The method of claim 1,
The pull-up signal generation unit adjusts the pulse width of the first data when the selection signal is activated and outputs the pull-up pre-drive signal. When the selection signal is inactivated, the pull-up pre-drive signal does not adjust the pulse width of the first data. Output driver, characterized in that output as. The method of claim 1,
The pull-down signal generation unit adjusts the pulse width of the second data when the selection signal is activated and outputs the pull-down free drive signal. When the selection signal is inactivated, the pull-down free drive signal does not adjust the pulse width of the second data. Output driver, characterized in that output as. A pulse width adjusting unit configured to adjust a pulse width of the first data and output the pull-up free drive signal according to the first impedance correction signal and the second impedance correction signal, and output a pull-down free drive signal by adjusting the pulse width of the second data. ; And
A driver unit driving an output node in response to the pull-up free drive signal and the pull-down free drive signal;
And the driver unit charges and discharges the output node simultaneously for a predetermined time in a data output mode. The method of claim 4, wherein
The driver unit occupies the output node in response to the pull-up free drive signal, discharges the output node in response to the pull-down free drive signal,
The predetermined time period corresponds to a degree in which the pulse width control unit adjusts the pulse width. The method of claim 4, wherein
The pulse width adjusting unit may variably delay the first data and output the first delay signal as a first delay signal according to the first impedance correction signal and the second impedance correction signal, and output the second delay signal as a second delay signal. A delay signal generator; And
And a pulse controller configured to receive the first data and the first delay signal to generate the pull-up pre-drive signal, and to receive the second data and the second delay signal to generate the pull-down free drive signal. . The method according to claim 6,
And the delay signal generator generates the first delay signal by delaying the rising edge of the first data, and generates the second delay signal by delaying the falling edge of the second data. The method according to claim 6,
The delay signal generator is configured to delay the falling edge of the first data to generate the first delay signal, and to delay the rising edge of the second data to generate the second delay signal. The method according to claim 6,
The delay signal generator includes a PMOS transistor configured to receive the first impedance correction signal and an NMOS transistor configured to receive the second impedance correction signal. The method of claim 9,
The delay signal generator includes a first variable delay inverter receiving the first impedance correction signal and a second variable delay inverter receiving the second impedance correction signal. The method of claim 4, wherein
The pulse width adjusting unit further receives a delay enable signal and adjusts or does not adjust a pulse width of the first data and the second data according to the delay enable signal, respectively, and the pull-up free drive signal and the pull-down free drive. Output as a signal, a semiconductor device. The method of claim 4, wherein
The pulse width adjusting unit may include a pull-up signal generation unit configured to adjust the pulse width of the first data according to the first impedance calibration signal and the second impedance calibration signal and output the same as the pull-up free drive signal; And
A pull-down signal generation unit configured to adjust the pulse width of the second data according to the first impedance calibration signal and the second impedance calibration signal and output the same as the pull-down free drive signal;
The pull-up signal generation unit generates the pull-up pre-drive signal so that the driver occupies the output node longer than the pulse width of the first data,
And the pull-down signal generator generates the pull-down free drive signal such that the driver discharges the output node longer than a pulse width of the second data. The method of claim 4, wherein
The driver unit may further receive the first impedance calibration signal and the second impedance calibration signal, determine a charge current for the output node in an on die termination mode according to the first impedance calibration signal, and correct the second impedance. And a discharge current for the output node is determined in the on die termination mode according to a signal. The method of claim 4, wherein
The driver unit receives the pull-up pre-drive signal to generate a pull-up main drive signal, and receives the pull-down pre-drive signal to generate a pull-down main drive signal; And
And a main driver unit occupying the output node in response to the pull-up main drive signal and discharging the output node in response to the pull-down main drive signal. The method of claim 14,
The pre-driver unit has a fixed driving force with respect to the pull-up main drive signal and the pull-down main drive signal. The method of claim 4, wherein
And a data determiner configured to generate the first data and the second data in response to a first source signal, a second source signal, and an ODT enable signal. 17. The method of claim 16,
The data determiner outputs the first source signal as the first data and the second source signal as the second data when the ODT enable signal is inactivated.
And generating the first data and the second data so that the pull-up driver unit and the pull-down driver unit perform an on die termination operation when the ODT enable signal is activated. The method of claim 17,
And the ODT enable signal is activated in the on die termination mode and inactivated in the data output mode. The method of claim 4, wherein
And an impedance calibration signal generator for checking an impedance value of an external resistor connected to a ZQ pad and generating the first and second impedance calibration signals according to the result.

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