KR20130045041A - 3d structured nonvolatile memory device and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a nonvolatile memory device having a three-dimensional structure and a method of manufacturing the same. According to an embodiment of the present invention, a nonvolatile memory device having a three-dimensional structure includes: a plurality of control gates stacked on a substrate; A plurality of first channels passing through the plurality of control gates; And a plurality of memory layer patterns interposed between the first channel and the plurality of control gates to surround the first channel and separated from each other. According to the present invention, the interference between the select gates and the memory cells can be minimized to improve the efficiency of program / erase / lead operations. In addition, the memory device may be driven in an enhanced mode.

Description

Non-volatile memory device having a three-dimensional structure and a method of manufacturing the same {3D STRUCTURED NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device having a three-dimensional structure and a method of manufacturing the same.

A non-volatile memory device is a memory device in which stored data is retained even if power supply is interrupted. Recently, as the degree of integration of a memory device having a two-dimensional structure that manufactures a memory device in a single layer on a silicon substrate has reached a limit, a non-volatile memory device having a three-dimensional structure in which memory cells are stacked vertically from a silicon substrate has been proposed. .

Hereinafter, a structure and a problem thereof of a nonvolatile memory device having a three-dimensional structure according to the prior art will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a structure of a nonvolatile memory device having a three-dimensional structure according to the prior art.

As shown in FIG. 1, the nonvolatile memory device having a three-dimensional structure according to the related art includes a channel CH protruding from the substrate 10 and a plurality of memory cells stacked along the channel CH. The memory device may further include a lower select gate LSG formed under the plurality of memory cells MC and an upper select gate USG formed over the plurality of memory cells MC. The bit line BL is connected to the channel CH. According to the structure, a plurality of memory cells MC connected in series between the lower select gate LSG and the upper select gate USG constitute one string STRING, and the string STRING is a substrate 10. Vertically).

In the drawings, reference numerals 11, 14, and 17 denote interlayer insulating films, reference numeral 12 denotes a lower selection line, reference numeral 15 denotes a word line, and reference numeral 18 denotes an upper selection line. Indicates. Reference numerals 13 and 19 denote gate insulating films, and reference numeral 16 denotes a charge blocking film, a charge trap film and a tunnel insulating film.

The formation method of the memory cell CH will be briefly described as follows. First, a plurality of conductive layers and a plurality of interlayer insulating layers are alternately formed, and then a plurality of conductive layers 15 and a plurality of interlayer insulating layers 14 are etched to form trenches. Subsequently, after the charge blocking film, the charge trap film, and the tunnel insulating film 16 are formed on the inner wall of the trench, the channel film is buried in the trench. According to the manufacturing process as described above, the charge trap layers of the plurality of memory cells MC stacked along the channel CH are connected to each other.

Here, the charge trap film serves as a substantial data store in which charge is injected or released to store data. Therefore, in the conventional structure in which the charge trap layers of the memory cells MC are interconnected, charges stored in one memory cell MC may be moved to another memory cell, thereby damaging the stored data.

The present invention provides a non-volatile memory device having a three-dimensional structure in which charge trap films of stacked memory cells are separated from each other, and a method of manufacturing the same.

According to an embodiment of the present invention, a nonvolatile memory device having a three-dimensional structure includes: a plurality of control gates stacked on a substrate; A plurality of first channels passing through the plurality of control gates; And a plurality of memory layer patterns interposed between the first channel and the plurality of control gates to surround the first channel and separated from each other.

Another embodiment of the present invention is a method of manufacturing a nonvolatile memory device having a three-dimensional structure, the method comprising: alternately forming a plurality of first material films and a plurality of second material films; Etching the plurality of first material layers and the plurality of second material layers to form a plurality of first trenches; Etching a plurality of thicknesses of the second material layers exposed on the inner wall of the first trench; Forming a charge trap layer along an inner surface of the first trench in which the plurality of second material layers are partially etched; Forming a channel film on the charge trap film to form a first channel having a plurality of protrusions protruding between the plurality of stacked first material films; Etching the plurality of first material layers and the plurality of second material layers to form a slit between the adjacent first trenches; Etching the charge trap layer exposed on the inner wall of the slit to separate the charge trap layers of the plurality of stacked memory cells from each other; And embedding an insulating layer in the slit in which the charge trap layer is etched.

In still another aspect of the present invention, there is provided a method of manufacturing a nonvolatile memory device having a three-dimensional structure, the method comprising: alternately forming a plurality of conductive layers and a plurality of first sacrificial layers; Etching the plurality of conductive layers and the plurality of first sacrificial layers to form a plurality of first trenches; Forming a charge trap layer along an inner surface of the first trench; Forming a channel film on the charge trap film to form a first channel protruding from the substrate; Etching the plurality of conductive layers and the plurality of second sacrificial layers to form a slit between the adjacent first trenches; Etching the plurality of first sacrificial layers exposed on the inner wall of the slit to expose the charge trap layer; Etching the charge trap layers exposed on the inner walls of the slits so as to separate the charge trap layers of the plurality of stacked memory cells from each other; Etching the charge trap layer to form a junction in the exposed first channel; And embedding an insulating film in the slit in which the junction is formed.

According to the present invention, the charge trap layers of the stacked memory cells can be separated from each other. Therefore, the interference between the select gates and the memory cells may be minimized to improve the efficiency of program / erase / lead operations. In addition, a junction may be formed in a channel between the stacked control gates to drive the memory device in an enhanced mode.

1 is a cross-sectional view illustrating a structure of a nonvolatile memory device having a three-dimensional structure according to the prior art.
2A to 2F are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a first embodiment of the present invention.
3A to 3D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a second embodiment of the present invention.
4A through 4D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a third embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating a structure of a nonvolatile memory device having a three-dimensional structure to which a memory cell according to a first embodiment of the present invention is applied.
FIG. 6 is a cross-sectional view illustrating a structure of a nonvolatile memory device having a three-dimensional structure to which a memory cell according to a second embodiment of the present invention is applied.
FIG. 7 is a cross-sectional view illustrating a structure of a nonvolatile memory device having a three-dimensional structure to which a memory cell according to a third embodiment of the present invention is applied.

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, the thickness and spacing are expressed for convenience of description and may be exaggerated compared to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. It should be noted that, in the case of adding the reference numerals to the constituent elements of the drawings, the same constituent elements have the same number as much as possible even if they are displayed on different drawings.

2A to 2F are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a first embodiment of the present invention. However, only the memory cell area is shown for convenience of description.

As shown in FIG. 2A, a plurality of first material layers 21 and a plurality of second material layers 22 are alternately formed.

Here, the first material film 21 is for forming a control gate, and the second material film 22 is for forming an interlayer insulating film that separates the stacked control gates from each other. Therefore, the number of the first material layer 21 and the second material layer 22 to be stacked is determined according to the number of memory cells to be stacked.

The first material layer 21 and the second material layer 22 may be formed of a material having a high etching selectivity. For example, the first material layer 21 may be formed of a conductive film for a control gate, and the second material layer 22 may be formed of a sacrificial layer. Alternatively, the first material layer 21 may be formed as a sacrificial layer, and the second material layer 22 may be formed as an interlayer insulating layer. In the first embodiment, a case in which the first material film 21 is formed of a sacrificial film such as a nitride film and the second material film 22 is formed of an interlayer insulating film such as an oxide film will be described.

Subsequently, the plurality of first material layers 21 and the plurality of second material layers 22 are etched to form a plurality of first trenches, and then the plurality of second material layers exposed on the inner wall of the first trench. The thickness 22 is etched to some extent.

Subsequently, the plurality of second material layers 22 may form the memory layer 23 along the inner surface of the first trench partially etched in thickness. The memory film 23 includes a charge blocking film, a charge trap film, and a tunnel insulating film. However, it is also possible to form only the charge trapping film and the tunnel insulating film without forming all of the charge blocking film, the charge trapping film and the tunnel insulating film.

Subsequently, a channel layer is formed on the memory layer 23 to form a plurality of first material layers 21 and first channels 24 that pass through the plurality of second material layers 22. Here, the channel film is formed on the inner wall of the first trench while filling the region where the plurality of second material films 22 are partially etched. Accordingly, the first channel 24 includes a plurality of protrusions A protruding between the stacked first material layers 21.

In this case, the channel film may be completely filled up to the center region of the first trench or may be formed to a thickness that opens the center region. When the center region is open, the insulating film 25 is buried in the open center region.

As shown in FIG. 2B, the plurality of first material layers 21 and the plurality of second material layers 22 are etched to form a slit S between the adjacent first channels 24. do. In the drawing, the etched first material film is denoted by reference numeral 21A, and the etched second material film is denoted by reference numeral 22A. In addition, although the plurality of second material films 22A are partially left after the slit S is formed in the drawing, all of the plurality of second material films 22 may be removed.

As illustrated in FIG. 2C, after the plurality of remaining second material layers 22A are removed to expose the memory layer 23, the memory layer 23 exposed on the inner wall of the slit S is etched. (See drawing "B"). In this case, since the protrusions fill a portion between the first material layers 21A, the memory layer 23 may be easily etched while preventing the first material layers 21A from being collapsed.

As a result, the memory layer 23 is patterned into the plurality of memory layer patterns 23A, and the charge trap layers of the memory cells stacked along the first channel 24 are separated from each other. Therefore, it is possible to prevent the charge from being transferred between the stacked memory cells.

Subsequently, although not shown in the drawing, a junction may be formed by etching impurities into the plurality of protrusions of the exposed first channel 24 by etching the memory layer 23. At this time, the depth of the junction may be adjusted by adjusting the implantation depth of the impurities.

As shown in FIG. 2D, the plurality of first material layers 21A exposed on the inner wall of the slit S are removed to form a plurality of control gate regions. In this case, the plurality of protrusions serve as a mold for the control gate, and an area between the plurality of protrusions becomes a control gate area.

Subsequently, a plurality of control gates 28 are formed by filling a conductive film in the plurality of control gate regions. For example, after the first metal layer 26 is formed along the inner surface of the slit S in which the plurality of control gate regions are formed, the second metal layer on the first metal layer 26 to fill the control gate region. (27) is formed. Here, the first metal layer 26 may be a barrier metal layer and the second metal layer 27 may be a gap fill metal layer. Subsequently, a wet etching process and a dry etching process are combined to etch the second metal layer 27 formed on the inner wall of the slit S except for the plurality of control gate regions. Subsequently, the first metal layer 26 formed on the inner wall of the slit S except for the plurality of control gate regions is etched by the cleaning process. As a result, the conductive layers embedded in the plurality of control gate regions are separated from each other to form the plurality of control gates 28.

As described above, when only the charge trap layer and the tunnel insulation layer are formed in the memory layer 23 forming step, the charge blocking layer is first formed before forming the control gates 28.

As shown in FIG. 2E, a plurality of protrusions protruding between the stacked control gates 28 are etched. In this figure, the first channel in which the protrusions are etched is denoted by reference numeral 24A.

When the protrusions are etched in this way, the effective length of the channel of each memory cell may be reduced. Of course, only some of the protrusions may be etched, or the protrusions may remain without being etched. It is also possible to form a junction in the first channel 24A between the stacked control gates 28 after etching the protrusions.

As shown in FIG. 2F, an insulating film is embedded in the slit S in which the plurality of protrusions are etched. As a result, a plurality of red and blue memory cells are formed along the first channel 24A. In particular, according to the first embodiment, the memory film pattern 23A of the "c" shape surrounds the control gate 28, respectively. That is, the memory layer pattern 23A is interposed between the first channel 24A and the plurality of control gates 28 while surrounding the top and bottom surfaces of the plurality of control gates 28. Thus, the plurality of memory cells stacked along the first channel 24A may include charge trap layers that are separated from each other.

Meanwhile, in the first embodiment, the first material film 21 is formed of a conductive film for control gate, such as a doped polysilicon film or a doped amorphous silicon film, and the second material film 22 is an undoped polysilicon film. Or a sacrificial film such as an undoped amorphous silicon film. Here, 'doped' means that the dopant such as boron (B) is doped, 'undoped' means that the dopant is not doped.

In this case, after performing the processes corresponding to FIGS. 2A to 2C, an insulating film is embedded in the slit S to complete formation of memory cells stacked along the first channel 24. In this case, before filling the insulating layer, the plurality of first material layers 21 exposed on the inner wall of the slit S may be silicided. For example, the first material layers 21 may be silicided by forming a metal layer in the slit, and then removing the remaining metal layer after silicideating the first material layer 21 by a heat treatment process. In addition, the first material layers 21 stacked after forming junctions, etching the protrusions, or etching the protrusions may be formed in the protrusions protruding between the stacked first material layers 21 before filling the insulating layer. Junctions may be formed in the first channel 24 therebetween.

3A to 3D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a second embodiment of the present invention.

The second embodiment relates to a method of forming a control gate by forming a separate mold after etching the protrusion of the first channel. Hereinafter, descriptions of the second embodiment will be omitted by omitting contents overlapping with those described in the first embodiment.

As shown in FIG. 3A, the first channel 33 penetrates through the plurality of first material layers 31 and includes a plurality of protrusions, and surrounds the first channel 33 and the first channel 33. The memory layer 32 interposed between the plurality of control gates 31 and the slit S between the adjacent first channels 34 are formed. Here, the first material film 31 may be formed of a sacrificial film such as a nitride film, and the second material film 32 may be formed of an interlayer insulating film such as an oxide film.

As shown in FIG. 3B, the plurality of protrusions of the first channel 33 protruding between the stacked first material layers 31 are etched. In this case, the memory layers 32 surrounding the plurality of protrusions are etched together. Here, the region in which the plurality of protrusions and the memory layer 32 are etched is a region for forming a mold to be used for subsequent control gate formation (hereinafter referred to as mold region M).

In this case, the memory layer 32 is patterned into a plurality of memory layer patterns 32A, and each of the memory layer patterns 32A has a shape of "|" and the first channel 33A and the plurality of first material layers ( 31). Therefore, the plurality of memory layer patterns 32A are spaced apart from each other by a predetermined distance, and charge transfer between stacked memory cells is prevented.

In addition, the protrusions of the first channel 33A are removed so that the channels of each memory cell are formed in a straight line without enclosing the control gate. Thus, the channel effective length of the memory cell can be reduced.

Subsequently, although not shown in the drawing, after etching the plurality of protrusions and the memory layer 32 surrounding the plurality of protrusions, impurities are injected into the first channel 33A exposed between the stacked first material layers 31. It may form a junction.

As shown in FIG. 3C, an insulating film such as an oxide film is embedded in the mold region M. As shown in FIG. Here, the insulating layers embedded in the mold region M become the control gate forming mold 35.

Subsequently, the plurality of first material layers 31 are removed to form a plurality of control gate regions. Here, the plurality of control gate regions are separated from each other by the mold 35.

As shown in FIG. 3D, a plurality of control gates 38 are formed by filling a conductive film in the plurality of control gate regions. Each control gate 38 may include a first metal layer 36 such as a barrier metal layer and a second metal layer 36 such as a gap fill metal layer.

Subsequently, the insulating layer 39 is buried in the slit S in which the plurality of control gates 38 are formed, thereby completing the formation of the memory cells stacked along the first channel 33A.

Meanwhile, in the second embodiment, the first material layer 31 may be formed of a conductive gate control film, and the second material layer 31 may be formed of a sacrificial layer. In this case, after a process corresponding to FIGS. 3A and 3B, an insulating film is embedded in the slit S to complete formation of memory cells stacked along the first channel 33A. In this case, before filling the insulating layer, the plurality of first material layers 31 exposed on the inner wall of the slit S may be silicided.

4A through 4D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a third embodiment of the present invention. However, only the memory cell area is shown for convenience of description.

As shown in FIG. 4A, a plurality of first material layers 41 and a plurality of second material layers 42 are alternately formed. Here, the first material layer 41 is formed of a conductive film for the control gate, and the second material layer 42 is formed of a sacrificial layer.

Subsequently, the plurality of first material layers 41 and the plurality of second material layers 42 are etched to form a plurality of first trenches, and then a memory layer 43 is formed on an inner wall of the first trench. . The memory film 43 includes a charge blocking film, a charge trap film, and a tunnel insulating film.

Subsequently, a channel layer is formed on the memory layer 43 to form a first channel 44 that penetrates the plurality of first material layers 41 and the plurality of second material layers 42. In this case, when the first channel 44 is formed to have an open central region, the insulating layer 45 is embedded in the open central region.

As shown in FIG. 4B, the plurality of first material layers 41 and the plurality of second material layers 42 are etched to form a slit S between the adjacent first channels 44. . Subsequently, the plurality of second material layers 42 exposed on the inner wall of the slit S are etched.

Next, the plurality of second material layers 42 are etched to etch the exposed memory layer 43. In this case, the memory layer 43 is patterned into a plurality of memory layer patterns 43A, and each memory layer pattern 43A is interposed between the first channel 44 and the plurality of first material layers 41 only. do.

As illustrated in FIG. 4C, an impurity is implanted into the first channel 44 exposed between the memory layer patterns 43A to form the junction 46. For example, the junction 46 may be formed by implanting ions in a horizontal direction. As another example, after forming the third material layer doped with impurities (not shown), the junction 46 may be formed by diffusing the impurities of the third material layer into the exposed first channel 44 by a heat treatment process. . In this case, the third material film may be removed after the junction 46 is formed.

As a result, the first channel 44A includes a plurality of junctions 46 formed between the stacked first material layers 41, and each junction 46 is positioned between the stacked memory cells. Accordingly, the junction 46 is provided in the first channel 44A between the stacked memory cells, thereby enabling enhanced mode driving of the memory device.

As shown in FIG. 4D, the insulating layer 47 is filled in the slit S in which the junction 46 is formed to complete formation of the memory cells stacked along the first channel 44A.

FIG. 5 is a cross-sectional view illustrating a structure of a nonvolatile memory device having a three-dimensional structure to which a memory cell according to a first embodiment of the present invention is applied.

As shown in FIG. 5, the memory device is embedded in the interlayer insulating film 52 formed on the substrate 51, the pipe gate 53 formed on the interlayer insulating film 52, and the pipe gate 53. The second channel 55 is connected to the first channels 24A. Here, the pair of first channels 24A and the second channel 55 are connected in a 'U' form to form one channel CH. In addition, the memory device may further include a gate insulating layer 54 surrounding the second channel 54.

The gate insulating layer 54 may be formed together when the memory layer 23 is formed, and the second channel 55 may be formed together when the first channel 23A is formed.

For example, before forming the plurality of first material layers and the plurality of second material layers, the pipe gate 53 may be etched to form a second trench at a position connected to the pair of first trenches. 2 Fill the sacrificial layer in the trench. After the plurality of first trenches are formed, the sacrificial layer is removed to form a U-type trench formed of a pair of first trenches and second trenches. Subsequently, as described above in the first embodiment, the memory film 23, the channel film, and the like are formed. At this time, the memory film 23 and the channel film are formed in the U-type trench.

When the memory cells are formed by the above method, the memory layer 23 and the first channel surrounding the second channel are formed in the process of etching the memory layer 23 to form the plurality of memory layer patterns 23A. The surrounding memory film 23 is separated. Here, the memory layer patterns 23A surrounding the first channel are separated from each other by surrounding the plurality of control gates 28 in a 'c' shape. In addition, the memory layer pattern surrounding the second channel surrounds the sidewall and the bottom surface of the second channel in a 'U' shape, and serves as the gate insulating layer 54.

Therefore, according to the present invention, not only the charge trap films of the stacked memory cells can be separated from each other, but also the memory film pattern 23A of the lowermost memory cell and the gate insulating film 53 of the pipe gate can be separated from each other.

Meanwhile, in the process of etching the protrusions of the first channel 24 after the control gate 28 is formed, a connection portion between the first channel 24A and the second channel 55 exposed in the slit may be etched. . Therefore, in order to prevent the connection between the first channel 24A and the second channel 55 being completely etched so that the first channel 24A and the second channel 55 are separated from each other, the etching process may be controlled.

Alternatively, a protective film may be formed on the bottom surface of the slit S prior to the protrusion etching process. For example, a passivation layer may be formed at the height of the control gate of the lowermost memory cell to cover the connection portion between the first channel 24A and the second channel 55 on the bottom of the slit. Alternatively, when the slit is formed, the etching depth may be adjusted to expose all of the first material layers 21 while forming the slit to a depth such that the lowermost second material layer 22 is not etched. In this case, the connection portion between the first channel 24A and the second channel 55 is not exposed during the protrusion etching process. In addition, it is possible to reduce the width of the pipe trench so that the connection portion between the first channel 24A and the second channel 55 is not exposed.

In addition, although not shown in the drawing, a pipe gate may be further formed after the sacrificial film is buried in the second trench. In this case, the gate insulating film on the second channel 54 is maintained. The gate insulating layer can be maintained in the same manner as in the previous method of preventing the etching of the connection portion between the first channel 24A and the second channel 55. As such, by further forming the pipe gate to cover the upper portion of the second channel 54, the cell current flowing through the second channel 54 may be improved to improve the performance of the memory device.

FIG. 6 is a cross-sectional view illustrating a structure of a nonvolatile memory device having a three-dimensional structure to which a memory cell according to a second embodiment of the present invention is applied.

As shown in FIG. 6, the memory device includes a U-type channel CH including a pair of first channels 24A and second channels 65, and each memory layer pattern 23A is formed of '|'. It is interposed between the plurality of control gates and the first channel 24A in the form. Other structures and formation methods are the same as those of the memory device described above with reference to FIG. 5, and thus detailed descriptions thereof will be omitted.

FIG. 7 is a cross-sectional view illustrating a structure of a nonvolatile memory device having a three-dimensional structure to which a memory cell according to a third embodiment of the present invention is applied.

As shown in FIG. 7, the memory device includes a U-type channel CH including a pair of first channels 24A and second channels 75, and each memory layer pattern 43A has a shape of '|'. It is interposed between the plurality of control gates and the first channel 24A in the form. In addition, a junction 46 is provided in the first channel 44A between the stacked memory cells. Other structures and formation methods are the same as those of the memory device described above with reference to FIG. 5, and thus detailed descriptions thereof will be omitted.

It is to be noted that the technical spirit of the present invention has been specifically described in accordance with the above-described preferred embodiments, but it is to be understood that the above-described embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

10: substrate 11, 14, 17: interlayer insulating film
12: lower selection line 15: word line
18: upper select line 13, 19: gate insulating film
16: charge blocking film, charge trap film and tunnel insulating film
21, 31, 41: first material film 22, 42: second material film
23, 32, 43: memory film 23A, 32A, 43A: memory film pattern
24, 33, 44: first channel 25, 34, 45, 47: insulating film
26, 36: first metal film 27, 37: second metal film
28, 38: control gate 35: mold
46: junction 51, 61, 71: substrate
52, 62, 72: interlayer insulating film 53, 63, 73: pipe gate
54, 64, 74: gate insulating film 55, 65, 75: second channel

Claims (19)

A plurality of control gates stacked on the substrate;
A plurality of first channels passing through the plurality of control gates; And
A plurality of memory layer patterns interposed between the first channel and the plurality of control gates and surrounding the first channel and separated from each other;
Non-volatile memory device having a three-dimensional structure comprising a.
The method of claim 1,
The first channel,
A plurality of protrusions protruding between the plurality of stacked control gates.
Non-volatile memory device having a three-dimensional structure.
The method of claim 1,
A plurality of junctions formed in the first channel between the stacked plurality of control gates
Non-volatile memory device having a three-dimensional structure further comprising.
The method of claim 1,
The memory layer pattern is interposed between the first channel and the plurality of control gates while surrounding the top and bottom surfaces of the plurality of control gates.
Non-volatile memory device having a three-dimensional structure.
The method of claim 1,
The memory layer pattern is interposed between the first channel and the plurality of control gates only.
Non-volatile memory device having a three-dimensional structure.
The method of claim 1,
A pipe gate formed on the substrate; And
A second channel embedded in the pipe gate and connected to the pair of first channels
Non-volatile memory device having a three-dimensional structure further comprising.
Alternately forming a plurality of first material films and a plurality of second material films;
Etching the plurality of first material layers and the plurality of second material layers to form a plurality of first trenches;
Etching a plurality of thicknesses of the second material layers exposed on the inner wall of the first trench;
Forming a charge trap layer along an inner surface of the first trench in which the plurality of second material layers are partially etched;
Forming a channel film on the charge trap film to form a first channel having a plurality of protrusions protruding between the plurality of stacked first material films;
Etching the plurality of first material layers and the plurality of second material layers to form a slit between the adjacent first trenches;
Etching the charge trap layer exposed on the inner wall of the slit to separate the charge trap layers of the plurality of stacked memory cells from each other; And
Filling an insulating film in the slit in which the charge trap film is etched
Method of manufacturing a non-volatile memory device having a three-dimensional structure comprising a.
The method of claim 7, wherein
Etching the charge trap film,
When the second material film remains on the inner wall of the slit, the charge trap film is etched after removing the remaining second material film.
A method of manufacturing a nonvolatile memory device having a three-dimensional structure.
The method of claim 7, wherein
After etching the charge trap film,
Forming a junction in the plurality of protrusions exposed between the plurality of first material layers
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.
The method of claim 7, wherein
After etching the charge trap film,
Etching the plurality of protrusions exposed between the plurality of first material layers.
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.
The method of claim 10,
After etching the plurality of protrusions of the first channel,
Forming a junction in the first channel exposed between the plurality of first material films
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.
The method of claim 7, wherein
After etching the charge trap film,
Removing the plurality of first material layers exposed on the inner wall of the slit to form a plurality of control gate regions; And
Embedding a conductive layer in the plurality of control gate regions to form a plurality of control gates;
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.
The method of claim 7, wherein
Etching the charge trap film,
Forming a mold region by etching the plurality of protrusions of the first channel and the charge trap layer surrounding the plurality of protrusions.
A method of manufacturing a nonvolatile memory device having a three-dimensional structure.
The method of claim 13,
After etching the charge trap film,
Embedding an insulating film in the mold region to form a mold for forming a plurality of control gates;
Removing the plurality of first material layers to form a plurality of control gate regions; And
Filling a conductive layer in the plurality of control gate regions to form a plurality of control gates
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.
15. The method according to claim 12 or 14,
Forming the plurality of control gates,
Forming a first metal film and a second metal film in the slit in which the plurality of control gate regions are formed;
Etching the second metal film formed in the slit excluding the plurality of control gate regions by combining a wet etching process and a dry etching process; And
Etching the first metal film formed in the slit excluding the plurality of control gate regions by a cleaning process.
A method of manufacturing a nonvolatile memory device having a three-dimensional structure.
The method of claim 7, wherein
Before forming the plurality of first material layers and the plurality of second material layers alternately, etching a pipe gate to form a second trench at a position connected to the pair of first trenches;
Filling a sacrificial layer in the second trench; And
After forming the plurality of first trenches, removing the sacrificial layer
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.
The method of claim 7, wherein
The first material layer and the second material layer are formed of a material having a high etching selectivity.
A method of manufacturing a nonvolatile memory device having a three-dimensional structure.
Alternately forming a plurality of conductive layers and a plurality of first sacrificial layers;
Etching the plurality of conductive layers and the plurality of first sacrificial layers to form a plurality of first trenches;
Forming a charge trap layer along an inner surface of the first trench;
Forming a channel film on the charge trap film to form a first channel protruding from the substrate;
Etching the plurality of conductive layers and the plurality of second sacrificial layers to form a slit between the adjacent first trenches;
Etching the plurality of first sacrificial layers exposed on the inner wall of the slit to expose the charge trap layer;
Etching the charge trap layers exposed on the inner walls of the slits so as to separate the charge trap layers of the plurality of stacked memory cells from each other;
Etching the charge trap layer to form a junction in the exposed first channel; And
Embedding an insulating film in the slit in which the junction is formed
Method of manufacturing a non-volatile memory device having a three-dimensional structure comprising a.
19. The method of claim 18,
Before forming the plurality of conductive layers and the plurality of first sacrificial layers alternately, etching a pipe gate to form a second trench at a position connected to the pair of first trenches;
Filling a second sacrificial layer in the second trench; And
After forming the plurality of first trenches, removing the second sacrificial layer
Non-volatile memory device manufacturing method of the three-dimensional structure further comprising.

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