KR20140136254A - Scan Driver and Display Device Using the same - Google Patents

Abstract

The present invention provides a semiconductor memory device comprising: a level shifter for outputting a start signal, clock signals and reset clock signals; And a shift register composed of stages for shifting and outputting a scan signal in response to the start signal, the clock signals and the reset clock signals, and the Nth stage of the stages includes a Nth clock signal corresponding to the potential of the Q node A pull-up transistor for outputting a low-potential voltage to the output terminal of the N-th stage corresponding to the potential of the QB node, a Q-node charging and discharging unit for charging and discharging the Q-node, and a pull- The QB node charge / discharge unit may maintain the QB node at a voltage between a logic high and a logic low after a low potential voltage is output through an output terminal of the Nth stage.

Description

[0001] The present invention relates to a scan driver and a display device using the same,

The present invention relates to a scan driver and a display device using the same.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as an organic light emitting display (OLED), a liquid crystal display (LCD), and a plasma display panel (PDP) is increasing.

Some of the above-described display devices, for example, a liquid crystal display device and an organic light emitting display device, include a display panel including a plurality of sub-pixels arranged in a matrix form and a driver for driving the display panel. The driving unit includes a scan driver for supplying a scan signal (or a gate signal) to the display panel, and a data driver for supplying a data signal to the display panel.

When a scan signal, a data signal, or the like is supplied to the subpixels arranged in a matrix form, the selected subpixel emits light so that an image can be displayed.

On the other hand, the scan driver for outputting a scan signal is divided into an external type, which is mounted on an external substrate of a display panel in the form of an integrated circuit, and a built-in type, which is formed on a display panel in a gate-

The built-in scan driver includes an amorphous silicon or an oxide thin film transistor. In the case of the oxide thin film transistor, the current transfer characteristic is superior to that of the amorphous silicon thin film transistor, and the circuit size can be reduced. However, the oxide thin film transistor has a disadvantage that the threshold voltage recovery characteristic is low due to the stress bias compared to the amorphous silicon thin film transistor.

Therefore, when the built-in scan driver is constructed of the oxide thin film transistor and the display panel is driven, the time to reach the limit life time of the amorphous silicon thin film transistor is short. Therefore, the built-in scan driver requires measures to increase the reliability and lifetime of the circuit.

According to an aspect of the present invention, there is provided a scan driver and a display device using the same, which can improve the lifetime and reliability of a scan driver by reducing positive bias stress.

According to an aspect of the present invention, there is provided a semiconductor memory device including: a level shifter for outputting a start signal, clock signals, and reset clock signals; And a shift register composed of stages for shifting and outputting a scan signal in response to the start signal, the clock signals and the reset clock signals, and the Nth stage of the stages includes a Nth clock signal corresponding to the potential of the Q node A pull-up transistor for outputting a low-potential voltage to the output terminal of the N-th stage corresponding to the potential of the QB node, a Q-node charging and discharging unit for charging and discharging the Q-node, and a pull- The QB node charge / discharge unit may maintain the QB node at a voltage between a logic high and a logic low after a low potential voltage is output through an output terminal of the Nth stage.

The QB node charge / discharge unit can maintain the QB node at a voltage between a logic high and a logic low when a Nth reset clock signal of a logic low is supplied.

The QB node charge / discharge unit includes a QB node discharge transistor for discharging the QB node corresponding to the potential of the Q node, and a QB node discharge transistor for discharging the QB node corresponding to at least one of the N reset clock signals or between the logic high and logic low The QB node can be maintained at a voltage level corresponding to the threshold voltage of one of the mirrored transistors.

The mirror type transistor includes a first side transistor having a gate electrode and a first electrode connected to a N-th reset clock signal terminal to which a Nth reset clock signal is supplied and a second electrode connected to a QB node, And a second side transistor having an electrode connected thereto and a second electrode connected to the N reset clock signal terminal.

The mirror type transistor includes a first side transistor having a gate electrode and a first electrode connected to a N-th reset clock signal terminal to which a Nth reset clock signal is supplied and a second electrode connected to a QB node, A second-side transistor having a first electrode and a gate electrode connected to the second electrode of the second-first transistor, and a second electrode connected to the N reset clock signal terminal, .

The Q node charge / discharge unit includes a first transistor having a gate electrode and a first electrode connected to a start signal terminal to which a start signal is supplied or an output terminal of the (N-1) th stage and a second electrode connected to a Q node, A second transistor having a first electrode connected to the low potential voltage terminal to which the low potential voltage is supplied and a second electrode connected to the Q node, a gate electrode connected to the output terminal of the (N + 2) And a Q node discharge transistor having a first electrode connected to the terminal and a second electrode connected to the Q node.

In another aspect, the present invention provides a display panel comprising: a display panel; A data driver connected to the data lines of the display panel; And a level shifter connected to the scan lines of the display panel and outputting a start signal, clock signals and reset clock signals, stages for shifting and outputting a scan signal corresponding to the start signal, the clock signals and the reset clock signals, The N stage of the stages includes a pull-up transistor for outputting a N-th clock signal to the output terminal of the N-th stage corresponding to the potential of the Q-node, and a pull-up transistor for outputting a low potential voltage corresponding to the potential of the QB node And a QB node charge / discharge unit for charging / discharging the QB node, wherein the QB node charge / discharge unit includes a pull-up transistor for outputting to the output terminal of the N-th stage, And a QB node is maintained at a voltage between a logic high and a logic low after the low potential voltage is outputted through the node All.

The QB node charge / discharge unit can maintain the QB node at a voltage between a logic high and a logic low when a Nth reset clock signal of a logic low is supplied.

The QB node charge / discharge unit includes a QB node discharge transistor for discharging the QB node corresponding to the potential of the Q node, and a QB node discharge transistor for discharging the QB node corresponding to at least one of the N reset clock signals or between the logic high and logic low The QB node can be maintained at a voltage level corresponding to the threshold voltage of one of the mirrored transistors.

The mirror type transistor includes a first side transistor having a gate electrode and a first electrode connected to a N-th reset clock signal terminal to which a Nth reset clock signal is supplied and a second electrode connected to a QB node, And a second side transistor having an electrode connected thereto and a second electrode connected to the N reset clock signal terminal.

The mirror type transistor includes a first side transistor having a gate electrode and a first electrode connected to a N-th reset clock signal terminal to which a Nth reset clock signal is supplied and a second electrode connected to a QB node, A second-side transistor having a first electrode and a gate electrode connected to the second electrode of the second-first transistor, and a second electrode connected to the N reset clock signal terminal, .

The Q node charge / discharge unit includes a first transistor having a gate electrode and a first electrode connected to a start signal terminal to which a start signal is supplied or an output terminal of the (N-1) th stage and a second electrode connected to a Q node, A second transistor having a first electrode connected to the low potential voltage terminal to which the low potential voltage is supplied and a second electrode connected to the Q node, a gate electrode connected to the output terminal of the (N + 2) And a Q node discharge transistor having a first electrode connected to the terminal and a second electrode connected to the Q node.

The present invention provides a scan driver capable of lowering a voltage applied to a QB node and reducing a positive bias stress of a corresponding node, thereby improving the lifetime and reliability of the scan driver, and a display using the same. In addition, the present invention provides a scan driver capable of self-refreshing a corresponding node by automatically varying a voltage applied to a QB node by a mirror transistor, and a display using the same.

1 is a schematic block diagram of a display device;
FIG. 2 is a diagram illustrating a configuration example of a subpixel shown in FIG. 1; FIG.
3 is a block diagram of a shift register according to a first embodiment of the present invention;
4 is a circuit configuration diagram of an Nth stage according to the first embodiment of the present invention;
FIG. 5 is a schematic view for explaining the operation of the Nth stage shown in FIG. 4; FIG.
6 is an operation timing diagram of the Nth stage shown in Fig.
7 is a circuit configuration diagram of an Nth stage according to a second embodiment of the present invention;
8 is a schematic view for explaining the operation of the Nth stage shown in FIG.
FIG. 9 is an operation timing diagram of the Nth stage shown in FIG. 7; FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

≪ Embodiment 1 >

Fig. 1 is a schematic block diagram of a display device, and Fig. 2 is an exemplary configuration diagram of subpixels shown in Fig.

1, the display device includes a display panel 100, a timing controller 110, a data driver 120, and a scan driver 130 and 140, as shown in FIG.

The display panel 10 includes sub-pixels connected to the intersecting data lines DL and the scan lines GL separately. The display panel 10 includes a display region 100A in which subpixels are formed and a non-display region 100B in which various signal lines, pads, and the like are formed outside the display region 100A. The display panel 100 may be implemented by a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD), or the like.

As shown in FIG. 2, one subpixel SP is supplied with a scan signal supplied through a switching transistor SW and a switching transistor SW connected to a scan line GL1 and a data line DL1, And a pixel circuit PC that operates in response to the data signal DATA. The subpixel SP is implemented by a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element according to the configuration of the pixel circuit PC.

When the display panel 100 is composed of a liquid crystal display panel, it may be a twisted nematic (TN) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, a FFS (Fringe Field Switching) mode, or an ECB (Electrically Controlled Birefringence) Mode. When the display panel 100 is formed of an organic light emitting display panel, it may be implemented as a top emission, a bottom emission, or a dual emission.

The timing controller 110 receives a timing signal such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock through an LVDS or TMDS interface receiving circuit connected to an image board. The timing controller 110 generates timing control signals for controlling the operation timings of the data driver 120 and the scan drivers 130 and 140 based on the input timing signal.

The data driver 120 includes a plurality of source drive ICs (Integrated Circuits). The source drive ICs are supplied with digital video data (RGB) and source timing control signal (DDC) from the timing controller 110. The source driver ICs convert the digital video data RGB to a gamma voltage in response to the source timing control signal DDC to generate a data voltage and apply the data voltage to the data lines DL of the display panel 100 Supply. The source drive ICs are connected to the data lines DL of the display panel 100 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The scan drivers 130 and 140 include a level shifter 130 and a shift register 140. The scan driver 130 and the scan driver 140 are formed in a gate in panel (GIP) scheme in which the level shifter 130 and the shift register 140 are separately formed. The level shifter 130 is formed on an external substrate connected to the display panel 100 in the form of an IC.

The level shifter 130 shifts the level of the clock signals clk, the reset clock signals reset_clk and the start signal vst under the control of the timing controller 11 and supplies the shifted levels to the shift register 140. The shift register 140 is formed in the non-display area 100B of the display panel 100 in the form of a thin film transistor (hereinafter referred to as TFT) by the GIP method. The shift register 140 consists of stages for shifting and outputting the scan signal in response to the clock signals clk, reset clock signals reset_clk and start signal vst. The stages included in the shift register 140 sequentially output the scan signals through the output terminals.

On the other hand, the shift register 140 is formed of thin film transistors. The oxide thin film transistor has an advantage of being able to reduce the size of the circuit due to its excellent current transfer characteristic compared to the amorphous silicon thin film transistor. However, the oxide thin film transistor has a disadvantage that the threshold voltage recovery characteristic is low due to the stress bias compared to the amorphous silicon thin film transistor. This is because, in the case of the amorphous silicon thin film transistor, the threshold voltage is kept constant over time (Clamping Voltage Saturation), but in the case of the oxide thin film transistor, the threshold voltage continues to shift toward the positive (+) direction over time (Clamping Voltage Not Saturation).

The present invention proposes a method of shortening the effective stress time of a pull-down transistor which receives a lot of positive bias stress in order to improve the life and reliability of the shift register 140 built in the GIP scheme . According to this method, lifetime and reliability can be improved when the shift register 140 is implemented by oxide thin film transistors. According to this method, the shift register 140 can be implemented not only in the oxide thin film transistor but also in the amorphous silicon thin film transistor.

Hereinafter, a GIP shift register capable of improving the lifetime and reliability will be described.

FIG. 3 is a block diagram of a shift register according to the first embodiment of the present invention, FIG. 4 is a circuit configuration diagram of an Nth stage according to the first embodiment of the present invention, FIG. 6 is a timing chart of the operation of the N-th stage shown in FIG. 4; FIG.

As shown in Figs. 3 to 6, the shift register according to the first embodiment of the present invention includes a plurality of stages STG [n] to STG [n + 2]. Phase clock signals clk1 to clk4, four-phase reset clock signals reset_clk1 to reset_clk4, a low potential voltage and a start signal vst are input to the stages STG [n] to STG [n + 2] .

The N-th stage STG [n] is connected to the output terminal of the start signal vst, the first clock signal clk1, the first reset clock signal reset_clk1 and the N + 2 stage STG [n + 2] And the scan signal Vg_out [n + 2] output from the scan driver Gout [n + 2]. The Nth stage STG [n] outputs the Nth scan signal Vg_out [n] through its output terminal Gout [n].

The n + 1 stage STG [n + 1] outputs the scan signal Vg_out [n] output from the output terminal Gout [n] of the N stage STG [n] ), The second reset clock signal (reset_clk2), and the scan signal output from the output terminal of the (N + 3) -th stage. The (N + 1) th stage STG [n + 1] outputs the (N + 1) th scan signal Vg_out [n + 1] through its output terminal Gout [n + 1].

The (N + 2) -th stage STG [n + 2] outputs the scan signal Vg_out [n + 1] output from the output terminal Gout [n + 1] of the (N + 1) ), The third clock signal clk3, the third reset clock signal (reset_clk3), and the scan signal output from the output terminal of the (N + 4) th stage. The (N + 2) th stage STG [n + 12] outputs the (N + 2) th scan signal Vg_out [n + 2] through its output terminal Gout [n + 2].

The plurality of stages STG [n] to STG [n + 2] are connected in a dependent manner so that the subsequent stage uses the scan signal output from the output terminal of the previous stage as described above. For example, the scan signal Vg_out [n] output from the output terminal Gout [n] of the Nth stage STG [n] is supplied to the start signal terminal VST). The plurality of stages STG [n] to STG [n + 2] are connected in such a manner that the scan signal output from the output terminal located two stages later than the self-scan stage is used as the reset signal do. For example, the scan signal Vg_out [n + 2] output from the output terminal Gout [n + 2] of the (N + 2) th stage STG [n + And is supplied to the reset terminal Vnext.

Hereinafter, the circuit configuration for the plurality of stages STG [n] to STG [n + 2] will be described in detail as an example of the Nth stage STG [n].

The pull-up transistor Tpd, the Q node charging portions T1, T2 and T8, the QB node charging portions T3, T4 and T5, the first capacitor (the first capacitor) C1 and a second capacitor C2.

First, the pull-up transistor Tpu, the Q-node charging units T1, T2 and T8, the QB node charging units T3, T4 and T5, the first capacitor C1 and the second capacitor C2 ) And the connection relationship between them will be described as follows.

The pull-up transistor Tpu outputs the Nth clock signal to the output terminal Gout [n] of the Nth stage corresponding to the potential of the Q node Q. Hereinafter, for convenience of explanation, the Nth clock signal is defined as the first clock signal clk1. Note, however, that in the case of a clock signal, other signals (e.g., a second clock signal, a third clock signal, etc.) may be selected depending on the position of the stage. The pull-up transistor Tpu has a first electrode connected to the first clock signal terminal CLK [n] to which a gate electrode is connected to the Q node Q and supplies the first clock signal clk1, and the output of the Nth stage And the second electrode is connected to the terminal Gout [n].

The pull-down transistor Tpd outputs a low potential voltage to the output terminal Gout [n] of the N-th stage corresponding to the potential of the QB node QB. The pull-down transistor Tpd has a gate electrode connected to the QB node QB and a first electrode connected to a low potential voltage terminal VGL (or VSS) for supplying a low potential voltage, and an output terminal Gout [ n] connected to the second electrode.

The Q node charging units T1, T2 and T8 charge the Q node Q corresponding to the potential of the start signal vst or the output terminal Gout [n-1] of the N- do. The Q node charging portions T1, T2 and T8 include a first transistor T1, a second transistor T2 and a Q node discharging transistor T8.

The first transistor T1 is turned on in response to the potential of the start signal vst or the output terminal Gout [n-1] of the (N-1) th stage and charges the Q node Q. Hereinafter, for convenience of explanation, the first transistor T1 follows the potential of the start signal vst as an example. However, in the case of the first transistor T1, it is noted that the start signal may be directly received according to the position of the stage, or a signal corresponding to the start signal may be supplied from the output terminal of the previous stage (or two stages before). The first transistor T1 has the gate electrode and the first electrode connected in common and the second electrode connected to the Q node Q at the output terminal Gout [n-1] of the (N-1) th stage.

The second transistor T2 is turned on in response to the potential of the QB node QB and discharges the Q node Q to a low potential voltage. The second transistor T2 has a gate electrode connected to the QB node QB and a first electrode connected to a low potential voltage terminal VGL for supplying a low potential voltage and a second electrode connected to the Q node Q .

The Q node discharge transistor T8 is turned on in response to the potential of the output terminal Gout [n + 2] of the (N + 2) th stage and discharges the Q node Q to the low potential voltage. The Q node discharge transistor T8 serves to maintain the discharge level of the Q node Q at a low potential voltage. The Q node discharge transistor T8 has the gate electrode connected to the output terminal Gout [n + 2] of the (N + 2) th stage and the first electrode connected to the low potential voltage terminal VGL supplying the low potential voltage And the second electrode is connected to the Q node (Q).

The QB node charging units T3, T4 and T5 charge the QB node QB corresponding to the first reset clock signal clk1 or maintain the QB node QB at a voltage between logic high and logic low, do. The QB node charging units T3, T4 and T5 include the mirror transistors T3 and T4 and the QB node discharging transistor T5.

At least one of the mirrored transistors T3 and T4 charges the QB node QB in response to the N reset clock signal or maintains the QB node QB at a voltage between logic high and logic low. Hereinafter, for convenience of explanation, the Nth reset clock signal is defined as a first reset clock signal (reset_clk1). Note, however, that in the case of a reset clock signal, other signals (e.g., a second reset clock signal, a third reset clock signal, etc.) may be selected and input depending on the position of the stage.

The mirrored transistors T3 and T4 include a first side transistor T3 and a second side transistor T4. The first transistor T3 is connected to the gate electrode and the first electrode of the first reset clock signal terminal Reset_CLK1 to which the first reset clock signal reset_clk1 is supplied and the second electrode of the transistor Q3 to the QB node QB . The second transistor T4 has a gate electrode and a first electrode connected to the QB node QB and a second electrode connected to the first reset clock signal terminal Reset_CLK1.

The QB node discharge transistor T5 is turned on in response to the potential of the Q node Q and discharges the QB node QB to the low potential voltage. The QB node discharge transistor T5 serves to maintain the discharge level of the QB node QB at a low potential voltage.

The first capacitor Cl serves to hold the voltage of the node at a logic low voltage when the Q node Q is electrically floated. One end of the first capacitor C1 is connected to the Q node Q and the other end is connected to the low potential voltage terminal VGL. The second capacitor C2 serves to hold the voltage of the node at a logic low voltage when the QB node QB is electrically floated. The second capacitor C2 has one end connected to the QB node QB and the other end connected to the low potential voltage terminal VGL.

In the above description, the shift register is composed of N type transistors, but the present invention is not limited thereto. In the above description, the drain electrode and the source electrode of the N-type transistor are described as the first electrode and the second electrode, but may be changed to the second electrode and the first electrode.

Next, the system of the clock signals and the reset clock signals will be described as follows.

The first through fourth clock signals clk1 through clk4 are sequentially switched from the logic high state to the logic low state in the system of the four clock signals clk1 through clk4. At this time, the first to fourth clock signals clk1 to clk4 are formed to have non-overlapping sections.

The first to fourth reset clock signals (reset_clk1 to reset_clk4) are sequentially switched from a logic high state to a logic low state in view of the scheme of reset clock signals (reset_clk1 to reset_clk4) on four phases. At this time, the first to fourth reset clock signals (reset_clk1 to reset_clk4) are formed such that the signals of the logic high state are spaced apart from each other. In addition, the logic high sections of the first to fourth reset clock signals (reset_clk1 to reset_clk4) are formed to precede the logic high sections of the first to fourth clock signals clk1 to clk4. That is, the rising edges of the first to fourth reset clock signals (reset_clk1 to reset_clk4) are formed to be ahead of the rising edges of the first to fourth clock signals clk1 to clk4. The reason for forming the rising edges of the first to fourth reset clock signals (reset_clk1 to reset_clk4) before the rising edges of the first to fourth clock signals clk1 to clk4 is to minimize the coupling between them, It is to lower power.

Hereinafter, the operation characteristics of the Nth stage will be described.

The Q node Q is charged corresponding to the potential of the start signal vst corresponding to the logic high H and the output terminal Gout [+2] of the (N + 2) As shown in FIG. The scan signal corresponding to the logic high H of the first clock signal clk1 is outputted while the Q node Q is charged. On the other hand, when the Q node Q is discharged, A scan signal corresponding to the row L is output.

More specifically, the Q node Q is charged as the first transistor T1 is turned on corresponding to the potential of the start signal vst corresponding to the logic high (H). At this time, the QB node QB is temporarily charged as the first and second side transistors T3 and T4 are temporarily turned on corresponding to the potential of the first reset clock signal (reset_clk1) of the logic high (H) 6 (1)). However, the pull-down transistor Tpd is reset without being turned on because the Vgs1 (see FIG. 5) of the QB node discharge transistor T5 becomes larger than Vgs2 (see FIG. 5) of the second side transistor T4.

It is preferable that the width of the channel of the QB node discharge transistor T5 is made larger than the width of the channel of the first side transistor T3 so as to constitute an optimum condition in which the mirror type transistors T3 and T4 can operate as described above good.

As the Q node Q is charged, the pull-down transistor Tpu outputs the first clock signal clk1 of the logic high H through the output terminal Gout [n] of the Nth stage. After the first clock signal clk1 of the logic high H is outputted, the Q node Q is discharged by the first capacitor C1.

The first transistor T1 is turned off in response to the potential of the start signal vst corresponding to the logic low L and corresponds to the potential of the output terminal Gout [n + 2] of the (N + 2) And the Q node Q is discharged as the Q node discharge transistor T8 is turned on. The QB node QB is reset through the second side transistor T4 turned on in response to the potential of the first reset clock signal reset_clk1 corresponding to the logic high H. At this time, the QB node QB is maintained at a voltage corresponding to the threshold voltage Vth of the second transistor T4 (see (2) in FIG. 6).

During this interval, the effective stresses applied to the gate electrodes of the second transistor T4 and the pull-down transistor Tpd become similar, so that the degree of the threshold voltage shift (Vth Shift) thereof will be similar. Accordingly, when the threshold voltage of the second transistor T4 is shifted in the positive direction, the level of the voltage applied to the QB node QB increases correspondingly. That is, the QB node QB receives a voltage corresponding to the threshold voltage of the second transistor T4.

Normally, the QB node QB receives a positive bias stress as a logic high (H) is continuously applied after outputting a scan signal of a logic low (L). However, when the mirror type transistors T3 and T4 and the QB node discharge transistor T5 configured according to the present invention are applied, the threshold voltage of the second side transistor T4 after the scan signal of the logic low L is outputted The voltage of the QB node QB is maintained at a voltage corresponding to the threshold voltage Vth and thus the positive bias stress can be reduced.

≪ Embodiment 2 >

7 is a circuit configuration diagram of the N-th stage according to the second embodiment of the present invention, 8 is a partial configuration diagram for explaining the operation of the N-th stage shown in Fig. 7, and Fig. 9 N stage.

As shown in Figs. 3 and 7 to 9, the shift register according to the second embodiment of the present invention also includes a plurality of stages STG [n] to STG [n + 2]. Phase clock signals clk1 to clk4, four-phase reset clock signals reset_clk1 to reset_clk4, a low potential voltage and a start signal vst are input to the stages STG [n] to STG [n + 2] .

The shift register according to the second embodiment of the present invention also has a plurality of stages STG [n] to STG [n + 2] in the same manner as in the first embodiment, And the N-th stage STG [n] will be concretely described with respect to the circuit configuration for the plurality of stages STG [n] to STG [n + 2].

The pull-up transistor Tpd, the Q node charging portions T1, T2 and T8, the QB node charging portions T3, T4 and T5, the first capacitor (the first capacitor) C1 and a second capacitor C2.

First, the pull-up transistor Tpu, the Q-node charging units T1, T2 and T8, the QB node charging units T3, T4 and T5, the first capacitor C1 and the second capacitor C2 ) And the connection relationship between them will be described as follows.

The pull-up transistor Tpu outputs the Nth clock signal to the output terminal Gout [n] of the Nth stage corresponding to the potential of the Q node Q. Hereinafter, for convenience of explanation, the Nth clock signal is defined as the first clock signal clk1. Note, however, that in the case of a clock signal, other signals (e.g., a second clock signal, a third clock signal, etc.) may be selected depending on the position of the stage. The pull-up transistor Tpu has a first electrode connected to the first clock signal terminal CLK [n] to which a gate electrode is connected to the Q node Q and supplies the first clock signal clk1, and the output of the Nth stage And the second electrode is connected to the terminal Gout [n].

The pull-down transistor Tpd outputs a low potential voltage to the output terminal Gout [n] of the N-th stage corresponding to the potential of the QB node QB. The pull-down transistor Tpd has a gate electrode connected to the QB node QB and a first electrode connected to a low potential voltage terminal VGL (or VSS) for supplying a low potential voltage, and an output terminal Gout [ n] connected to the second electrode.

The Q node charging units T1, T2 and T8 charge the Q node Q corresponding to the potential of the start signal vst or the output terminal Gout [n-1] of the N- do. The Q node charging portions T1, T2 and T8 include a first transistor T1, a second transistor T2 and a Q node discharging transistor T8.

The first transistor T1 is turned on in response to the potential of the start signal vst or the output terminal Gout [n-1] of the (N-1) th stage and charges the Q node Q. Hereinafter, for convenience of explanation, the first transistor T1 follows the potential of the start signal vst as an example. However, in the case of the first transistor T1, it is noted that the start signal may be directly received according to the position of the stage, or a signal corresponding to the start signal may be supplied from the output terminal of the previous stage (or two stages before). The first transistor T1 has the gate electrode and the first electrode connected in common and the second electrode connected to the Q node Q at the output terminal Gout [n-1] of the (N-1) th stage.

The second transistor T2 is turned on in response to the potential of the QB node QB and discharges the Q node Q to a low potential voltage. The second transistor T2 has a gate electrode connected to the QB node QB and a first electrode connected to a low potential voltage terminal VGL for supplying a low potential voltage and a second electrode connected to the Q node Q .

The Q node discharge transistor T8 is turned on in response to the potential of the output terminal Gout [n + 2] of the (N + 2) th stage and discharges the Q node Q to the low potential voltage. The Q node discharge transistor T8 serves to maintain the discharge level of the Q node Q at a low potential voltage. The Q node discharge transistor T8 has the gate electrode connected to the output terminal Gout [n + 2] of the (N + 2) th stage and the first electrode connected to the low potential voltage terminal VGL supplying the low potential voltage And the second electrode is connected to the Q node (Q).

The QB node charging units T3, T4 and T5 charge the QB node QB corresponding to the first reset clock signal clk1 or maintain the QB node QB at a voltage between logic high and logic low, do. The QB node charging units T3, T4 and T5 include the mirror transistors T3, T4-1 and T4-2 and the QB node discharging transistor T5.

At least one of the mirrored transistors T3, T4-1 and T4-2 charges the QB node QB in response to the N reset clock signal or the QB node QB in a voltage between logic high and logic low . Hereinafter, for convenience of explanation, the Nth reset clock signal is defined as a first reset clock signal (reset_clk1). Note, however, that in the case of a reset clock signal, other signals (e.g., a second reset clock signal, a third reset clock signal, etc.) may be selected and input depending on the position of the stage.

The mirror transistors T3, T4-1 and T4-2 include a first transistor T3, a second transistor T4-1 and a second transistor T4-2. The first transistor T3 is connected to the gate electrode and the first electrode of the first reset clock signal terminal Reset_CLK1 to which the first reset clock signal reset_clk1 is supplied and the second electrode of the transistor Q3 to the QB node QB . A gate electrode and a first electrode of the second-first transistor T4-1 are connected to the QB node QB. The second-2-side transistor T4-2 has the first electrode and the gate electrode connected to the second electrode of the second-1-side transistor T4-1 and the second reset transistor T4-1 connected to the first reset clock signal terminal (Reset_CLK1) Lt; / RTI >

In the second embodiment of the present invention, the second side transistors T4-1 and T4-2 are formed by two transistors. However, the second side transistors T4-1 and T4-2 may be constituted by N (N is an integer of 2 or more) to increase the voltage applied to the QB node QB. That is, the voltage applied to the QB node QB increases as the number of the second side transistors T4-1 and T4-2 increases and the number of the second side transistors T4-1 and T4-2 decreases . As described above, the voltage applied to the QB node QB can be adjusted by changing the number of the second side transistors T4-1 and T4-2. The second side transistors T4-1 and T4-2 ) Can be set corresponding to the positive bias stress received by the QB node QB. For example, when the second side transistors T4-1 and T4-2 are composed of two transistors as in the second embodiment of the present invention, the QB node QB is connected to the second side transistors T4-1 and T4-2 A voltage corresponding to a threshold voltage (e.g., 2 * Vth) is applied.

The QB node discharge transistor T5 is turned on in response to the potential of the Q node Q and discharges the QB node QB to the low potential voltage. The QB node discharge transistor T5 serves to maintain the discharge level of the QB node QB at a low potential voltage.

The first capacitor Cl serves to hold the voltage of the node at a logic low voltage when the Q node Q is electrically floated. One end of the first capacitor C1 is connected to the Q node Q and the other end is connected to the low potential voltage terminal VGL. The second capacitor C2 serves to hold the voltage of the node at a logic low voltage when the QB node QB is electrically floated. The second capacitor C2 has one end connected to the QB node QB and the other end connected to the low potential voltage terminal VGL.

In the above description, the shift register is composed of N type transistors, but the present invention is not limited thereto. In the above description, the drain electrode and the source electrode of the N-type transistor are described as the first electrode and the second electrode, but may be changed to the second electrode and the first electrode.

Next, the system of the clock signals and the reset clock signals will be described as follows.

The first through fourth clock signals clk1 through clk4 are sequentially switched from the logic high state to the logic low state in the system of the four clock signals clk1 through clk4. At this time, the first to fourth clock signals clk1 to clk4 are formed to have non-overlapping sections.

The first to fourth reset clock signals (reset_clk1 to reset_clk4) are sequentially switched from a logic high state to a logic low state in view of the scheme of reset clock signals (reset_clk1 to reset_clk4) on four phases. At this time, the first to fourth reset clock signals (reset_clk1 to reset_clk4) are formed such that the signals of the logic high state are spaced apart from each other. In addition, the logic high sections of the first to fourth reset clock signals (reset_clk1 to reset_clk4) are formed to precede the logic high sections of the first to fourth clock signals clk1 to clk4. That is, the rising edges of the first to fourth reset clock signals (reset_clk1 to reset_clk4) are formed to be ahead of the rising edges of the first to fourth clock signals clk1 to clk4. The reason for forming the rising edges of the first to fourth reset clock signals (reset_clk1 to reset_clk4) before the rising edges of the first to fourth clock signals clk1 to clk4 is to minimize the coupling between them, It is to lower power.

Hereinafter, the operation characteristics of the Nth stage will be described.

The Q node Q is charged corresponding to the potential of the start signal vst corresponding to the logic high H and the output terminal Gout [+2] of the (N + 2) As shown in FIG. The scan signal corresponding to the logic high H of the first clock signal clk1 is outputted while the Q node Q is charged. On the other hand, when the Q node Q is discharged, A scan signal corresponding to the row L is output.

More specifically, the Q node Q is charged as the first transistor T1 is turned on corresponding to the potential of the start signal vst corresponding to the logic high (H). At this time, the QB node QB outputs the first, second and first 2-side transistors T3, T4-1 and T4 (corresponding to the potential of the first reset clock signal reset_clk1 of the logic high H) -2) is temporarily turned on (see (1) of FIG. 9). However, since Vgs1 (see FIG. 8) of the QB node discharge transistor T5 becomes larger than Vgs2 (see FIG. 8) of the 2-1 and 2-2 side transistors T4-1 and T4-2, Tpd) is reset without being turned on.

The width of the channel of the QB node discharge transistor T5 is set to be smaller than the width of the channel of the first side transistor T3 in order to configure the optimum conditions for the mirror type transistors T3, T4-1, It is preferable that the width is larger than the width.

As the Q node Q is charged, the pull-down transistor Tpu outputs the first clock signal clk1 of the logic high H through the output terminal Gout [n] of the Nth stage. After the first clock signal clk1 of the logic high H is outputted, the Q node Q is discharged by the first capacitor C1.

The first transistor T1 is turned off in response to the potential of the start signal vst corresponding to the logic low L and corresponds to the potential of the output terminal Gout [n + 2] of the (N + 2) And the Q node Q is discharged as the Q node discharge transistor T8 is turned on. The QB node QB through the second-1 and second 2-side transistors T4-1 and T4-2 turned on in response to the potential of the first reset clock signal (reset_clk1) corresponding to the logic high H, Is reset. At this time, the QB node QB is maintained at a voltage corresponding to the threshold voltage Vth of the second-first and second-side transistors T4-1 and T4-2 (see (2) ).

Since the effective stresses applied to the gate electrodes of the second-type and second-side transistors T4-1 and T4-2 and the pull-down transistor Tpd during this period are similar to each other, their threshold voltage shifts Vth Shift) will be similar. Accordingly, when the threshold voltages of the second-first and second-side transistors T4-1 and T4-2 are shifted in the positive direction, the level of the voltage applied to the QB node QB increases correspondingly . That is, the QB node QB receives a voltage corresponding to the threshold voltages of the 2-1 and 2-2-side transistors T4-1 and T4-2.

Normally, the QB node QB receives a positive bias stress as a logic high (H) is continuously applied after outputting a scan signal of a logic low (L). However, when the mirror type transistors T3, T4-1, T4-2 and QB node discharge transistor T5 configured as in the present invention are applied, the scan signals of the logic low L are output, The voltage of the QB node QB is maintained at a voltage corresponding to the threshold voltage Vth of the second-second transistors T4-1 and T4-2, so that the positive bias stress can be reduced.

As described above, the present invention provides a scan driver and a display device using the same that can lower the voltage applied to the QB node and reduce the positive bias stress of the node, thereby improving the life and reliability of the scan driver. In addition, the present invention provides a scan driver capable of self-refreshing a corresponding node by automatically varying a voltage applied to a QB node by a mirror transistor, and a display using the same.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

100: display panel 110: timing controller
120: data driver 130, 140: scan driver
130: level shifter 140: shift register
Tpu: pull-up transistor Tpd: pull-down transistor
T1: first transistor T2: second transistor
T3, T4: mirror type transistor T4-1: second-1-side transistor
T4-2: 2nd-2 <

Claims (12)

A level shifter for outputting a start signal, clock signals and reset clock signals; And
And a shift register including stages for shifting and outputting a scan signal corresponding to the start signal, the clock signals, and the reset clock signals,
The Nth stage of the stages
A pull-up transistor for outputting an N-th clock signal to an output terminal of the N-th stage corresponding to a potential of a Q-
A pull-down transistor for outputting a low potential voltage to the output terminal of the Nth stage in correspondence with the potential of the QB node,
A Q node charging / discharging unit for charging / discharging the Q node,
And a QB node charge / discharge unit for charging / discharging the QB node,
Wherein the QB node charge / discharge unit maintains the QB node at a voltage between a logic high and a logic low after the low potential voltage is output through an output terminal of the Nth stage. The method according to claim 1,
The QB node charge /
And maintains the QB node at a voltage between a logic high and a logic low when the N reset clock signal of the logic low is supplied. The method according to claim 1,
The QB node charge /
A QB node discharge transistor for discharging the QB node corresponding to the potential of the Q node,
At least one of which is responsive to a N reset clock signal to charge the QB node or to maintain the QB node at a voltage between a logic high and a logic low,
Wherein the QB node is maintained at a voltage level corresponding to a threshold voltage of one of the mirror transistors. The method of claim 3,
The mirror-
A first side transistor having a gate electrode and a first electrode connected to an N-th reset clock signal terminal to which the N-th reset clock signal is supplied, and a second electrode connected to the QB node,
And a second side transistor having a gate electrode and a first electrode connected to the QB node and a second electrode connected to the N reset clock signal terminal. The method of claim 3,
The mirror-
A first side transistor having a gate electrode and a first electrode connected to an N-th reset clock signal terminal to which the N-th reset clock signal is supplied, and a second electrode connected to the QB node,
A second-side transistor having a gate electrode and a first electrode connected to the QB node,
And a second 2-side transistor having a first electrode and a gate electrode connected to a second electrode of the second-1-side transistor and a second electrode connected to the N reset clock signal terminal. The method according to claim 1,
The Q node charge /
A first transistor having a gate electrode and a first electrode connected to a start signal terminal to which the start signal is supplied or an output terminal of the (N-1) th stage, and a second electrode connected to the Q node;
A second transistor having a gate electrode connected to the QB node and having a first electrode connected to a low potential voltage terminal to which the low potential voltage is supplied and a second electrode connected to the Q node;
And a Q node discharge transistor having a gate electrode connected to an output terminal of the (N + 2) stage, a first electrode connected to the low potential voltage terminal, and a second electrode connected to the Q node. Display panel;
A data driver connected to the data lines of the display panel; And
A level shifter connected to the scan lines of the display panel and outputting a start signal, clock signals, and reset clock signals; a shift register for shifting a scan signal in response to the start signal, the clock signals, A shift register comprising stages,
The Nth stage of the stages
A pull-up transistor for outputting an N-th clock signal to an output terminal of the N-th stage corresponding to a potential of a Q-
A pull-down transistor for outputting a low potential voltage to the output terminal of the Nth stage in correspondence with the potential of the QB node,
A Q node charging / discharging unit for charging / discharging the Q node,
And a QB node charge / discharge unit for charging / discharging the QB node,
Wherein the QB node charge / discharge unit holds the QB node at a voltage between a logic high and a logic low after the low potential voltage is output through the output terminal of the Nth stage. 8. The method of claim 7,
The QB node charge /
And maintains the QB node at a voltage between a logic high and a logic low when the N reset clock signal of the logic low is supplied. 8. The method of claim 7,
The QB node charge /
A QB node discharge transistor for discharging the QB node corresponding to the potential of the Q node,
At least one of which is responsive to a N reset clock signal to charge the QB node or to maintain the QB node at a voltage between a logic high and a logic low,
And the QB node is maintained at a voltage level corresponding to a threshold voltage of one of the mirror-type transistors. 10. The method of claim 9,
The mirror-
A first side transistor having a gate electrode and a first electrode connected to an N-th reset clock signal terminal to which the N-th reset clock signal is supplied, and a second electrode connected to the QB node,
And a second side transistor having a gate electrode and a first electrode connected to the QB node and a second electrode connected to the N reset clock signal terminal. 10. The method of claim 9,
The mirror-
A first side transistor having a gate electrode and a first electrode connected to an N-th reset clock signal terminal to which the N-th reset clock signal is supplied, and a second electrode connected to the QB node,
A second-side transistor having a gate electrode and a first electrode connected to the QB node,
And a second-2-side transistor having a first electrode and a gate electrode connected to a second electrode of the second-1-side transistor and a second electrode connected to the N-th reset clock signal terminal. 8. The method of claim 7,
The Q node charge /
A first transistor having a gate electrode and a first electrode connected to a start signal terminal to which the start signal is supplied or an output terminal of the (N-1) th stage, and a second electrode connected to the Q node;
A second transistor having a gate electrode connected to the QB node and having a first electrode connected to a low potential voltage terminal to which the low potential voltage is supplied and a second electrode connected to the Q node;
And a Q node discharge transistor having a gate electrode connected to the output terminal of the (N + 2) stage, a first electrode connected to the low potential voltage terminal, and a second electrode connected to the Q node.

Images