KR20150051531A - Manufacturing method of liquid crystal display device - Google Patents

Abstract

Provided is a method of manufacturing a liquid crystal display device capable of improving aperture rate by preventing the generation of an active tail. A method of manufacturing a liquid crystal display device can prevent the generation of an active tail protruding from the lateral part of a data line, by forming an active layer, a source electrode and a drain electrode, and a pixel electrode at the same time after forming the data line.

Description

[0001] The present invention relates to a manufacturing method of a liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a liquid crystal display device, and more particularly, to a method of manufacturing a liquid crystal display device capable of preventing an occurrence of an active tail and improving an aperture ratio.

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out.

Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

1 is a view schematically showing a structure of a general liquid crystal display device.

As shown in the figure, a liquid crystal display comprises a color filter substrate 20, an array substrate 10 and a liquid crystal layer 30 between the two substrates.

The color filter substrate 20 separates each of the color filters C and the sub color filters 25 constituted by a plurality of sub color filters 25 that emit red, And a black matrix 21 for blocking light transmitted through the black matrix 21.

The array substrate 10 includes a plurality of gate lines 2b and data lines 5c arranged to intersect with each other to define a plurality of pixel regions P and a plurality of gate lines 2b and a plurality of data lines 5c A thin film transistor T which is a switching element formed at each intersection and a pixel electrode 6 formed for each of a plurality of pixel regions P. [

(Not shown) formed on the pixel electrode 6 and applying a voltage to the liquid crystal layer 30 together with the pixel electrode 6, although not shown in the drawing.

The color filter substrate 20 and the array substrate 10 described above are adhered to each other by a sealant (not shown) formed on the periphery of the image display area to constitute a liquid crystal panel. At this time, the color filter substrate 20 and the array substrate 10 are bonded together by a joining key (not shown) formed on at least one substrate of the two substrates.

Such a liquid crystal display device has a structure in which liquid crystal molecules of the liquid crystal layer 30 are driven in a horizontal direction with respect to the color filter substrate 20 and the array substrate 10 to form in-plane switching (IPS) ) Method.

FIG. 2 is a cross-sectional view of the array substrate shown in FIG. 1, and FIGS. 3A to 3C are manufacturing process diagrams of the array substrate shown in FIG.

Referring to the drawings, a conventional array substrate 10 is composed of a thin film transistor region, a pixel region, and a link region.

In the thin film transistor region, a thin film transistor including a gate electrode 2a, a source electrode 5a, and a drain electrode 5b is formed. A pixel electrode 6 connected to the drain electrode 5b of the thin film transistor is formed in the pixel region. A data line 5c connected to the source electrode 5a is formed in the link region.

First, a first metal film (not shown) is deposited on a substrate 1 such as glass, and a first metal film is selectively patterned through a first mask process to form a gate electrode (2a) and a gate line (not shown).

Subsequently, a gate insulating film 3, an amorphous silicon film (not shown), an n + amorphous silicon film (not shown) and a second metal film (not shown) are sequentially formed on the entire surface of the substrate 1 on which the gate electrode 2a and the gate line are formed Lt; / RTI >

Then, the remaining films except for the gate insulating film 3 are selectively patterned through a second mask process to form an active layer 4a on the gate electrode 2a. The active layer 4a includes a channel region composed of an amorphous silicon film and a source / drain region composed of an amorphous silicon film and an n + amorphous silicon film. The n + amorphous silicon film is an ohmic contact layer (not shown) for ohmic contact between the source electrode 5a and the source region of the active layer 4a or between the drain electrode 5b and the drain region of the active layer 4a. ).

In addition, a source electrode 5a and a drain electrode 5b made of a second metal film are formed on the active layer 4a through a second mask process.

Further, a data line 5c composed of an amorphous silicon film, an n + amorphous silicon film, and a second metal film is formed in the link region of the array substrate 10 through the second mask process.

Thus, the active layer 4a, the source electrode 5a and the drain electrode 5b of the thin film transistor are formed through a single second mask process, and the data line 5c is formed.

A third metal film (not shown) is deposited on the entire surface of the substrate 1 on which the source electrode 5a, the drain electrode 5b and the data line 5c are formed. Then, the pixel electrode 6 is formed to be connected to the drain electrode 5b through a third mask process.

Subsequently, a protective film 7 is deposited on the entire surface of the substrate 1 on which the pixel electrodes 6 are formed, and a part of the protective film 7 is patterned through a fourth mask process to form contact holes (not shown) And exposes the data line 5c to the outside.

A fourth metal film (not shown) is deposited on the protective film 7, and a common electrode 8 is formed in the pixel portion of the array substrate 10 through a fifth mask process. Here, the common electrode 8 and the pixel electrode 6 are formed of a transparent metal material through which light can pass, for example, ITO or IZO. The common electrode 8 is formed to be connected to the data line 5c by filling the contact hole of the protective film 7. [

As described above, the manufacturing process of the conventional array substrate 10 requires five mask processes, that is, five photolithography processes.

Particularly, in the conventional second mask process, a half tone mask is used, and the active layer 4a, the source electrode 5a, the drain electrode 5b, and the data line 5c are formed by using a half- .

However, since the active layer 4a and the data line 5c are formed at one time by the second mask process using the halftone mask, as shown in Fig. 2, The active sub-active layer 4b, that is, the active tail is formed.

Such an active tail lowers the aperture ratio of the liquid crystal display device and reduces the transmittance.

In other words, the end of the pixel electrode 6 should be formed at a predetermined distance from the side of the data line 5c. The distance d1 between the end of the pixel electrode 6 and the side of the data line 5c is preset in the designing stage of the liquid crystal display device and has a spacing distance of about 3.5 μm or less.

However, since the sub-active layer 4b protrudes around both sides of the data line 5c to form the active tail as described above, the distance d1 between the pixel electrode 6 and the data line 5c, Needs to be adjusted.

That is, the pixel electrode 6 should be formed to be shorter than the one-side length d2 of the active tail so that the distance d1 between the previously set pixel electrode 6 and the data line 5c can be satisfied.

In this manner, in the conventional array substrate 10 of the liquid crystal display device, since the pixel electrode 6 is formed to be shorter by the length d2 of the active tail, the area of the pixel region of the array substrate 10 is reduced and the aperture ratio is lowered . Such a decrease in the aperture ratio causes a decrease in the transmittance of the liquid crystal display device.

An object of the present invention is to provide a method of manufacturing a liquid crystal display device capable of increasing the transmittance of a liquid crystal display device by improving the aperture ratio by suppressing the occurrence of an active tail.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including: forming a gate electrode by depositing a first metal layer on a substrate and selectively patterning the first metal layer; Forming an active pattern, a data electrode pattern, and a data line by sequentially depositing a silicon layer and a second metal layer on the substrate having the gate electrode formed thereon and selectively patterning the same; And forming a third metal layer on the substrate on which the active pattern, the data electrode pattern, and the data line are formed, and selectively patterning the third metal layer to form the active layer, the source electrode, the drain electrode, and the pixel electrode.

According to the method of manufacturing a liquid crystal display of the present invention, active tails can be prevented from being generated in the data lines by forming the active layer, the source electrode, and the drain electrode together with the pixel electrode after forming the data line.

Therefore, the liquid crystal display device according to the present invention has an increased pixel area, thereby increasing the aperture ratio and increasing the transmittance.

1 is a view schematically showing a structure of a general liquid crystal display device.
2 is a cross-sectional view of the array substrate shown in Fig.
FIGS. 3A to 3C are manufacturing process diagrams of the array substrate shown in FIG.
4 is a schematic plan view of an array substrate of a liquid crystal display device according to an embodiment of the present invention.
5 is a cross-sectional view of the array substrate of FIG. 4 taken along line A-A '.
Figs. 6A to 6E are manufacturing process diagrams of the array substrate shown in Fig.
7A to 7D are detailed flow diagrams of the array substrate shown in FIG. 6C.
8 is a graph showing the relationship between the active tail and the transmittance in the liquid crystal display device.

Hereinafter, a method of manufacturing a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a schematic plan view of an array substrate of a liquid crystal display device according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view of the array substrate of FIG. 4 taken along line A-A '.

4 and 5, the array substrate 100 of the liquid crystal display according to an exemplary embodiment of the present invention may include a thin film transistor region, a pixel region, and a link region.

A thin film transistor T may be formed in the thin film transistor region of the array substrate 100. In addition, the pixel electrode 151 may be formed in the pixel region, and the gate line 111 and the data line 141 may be formed in the link region.

A gate line 111 and a data line 141 may be formed on the array substrate 100 so as to cross each other. A pixel region may be formed in a crossing region of the gate line 111 and the data line 141. A common line 115 may be formed on the upper or lower portion of the pixel region in parallel with the gate line 111. In the present embodiment, the common line 115 is formed below the pixel region, but the present invention is not limited thereto.

A thin film transistor T may be formed at an intersection where the gate line 111 and the data line 141 intersect. The thin film transistor T may include a gate electrode 110, an active layer 131, a source electrode 143, and a drain electrode 145.

The gate electrode 110 may be formed by protruding a part of the gate line 111. An active layer 131 may be formed on the gate electrode 110 with a gate insulating layer 120 interposed therebetween.

The active layer 131 may include a source / drain region overlapping the source electrode 143 and the drain electrode 145, and a channel region forming a conductive channel between the two electrodes. The source / drain regions of the active layer 131 may be formed to overlap the source electrode 143 and the drain electrode 145, respectively.

The source electrode 143 may be branched from the data line 141 and overlap the active layer 131. The drain electrode 145 may be formed spaced apart from the source electrode 143 around the channel region of the active layer 131.

The pixel electrode 151 and the common electrode 170 may be formed in the pixel region. The pixel electrode 151 may be formed to overlap the drain electrode 145 and extend to a pixel region of the array substrate 100. In addition, the pixel electrode 151 may be formed overlapping the source electrode 143.

The common electrode 170 may be formed to overlap the pixel electrode 151 with the interlayer insulating layer 160 therebetween. The common electrode 170 is divided into a plurality of fingers from a common electrode line 171 formed to be connected to the common line 115 or the data line 141 through the contact hole 165, Direction. The common electrode line 171 may be formed in parallel with the common line 170 or the gate line 111.

The pixel electrode 151 and the common electrode 170 can generate a transverse electric field in the pixel region of the array substrate 100 to drive the liquid crystal molecules of the liquid crystal layer (not shown).

A gate line 111, a data line 141, and a common line 115 may be formed in the link region of the array substrate 100.

The gate line 111 and the common line 115 may be formed in the same layer as the gate electrode 110 in the same process. The data line 141 may be formed in the same layer as the source electrode 143 and the drain electrode 145 in the same process.

On the other hand, in the array substrate 100 of the present embodiment, the source electrode 143 and the drain electrode 145 may be formed together with the active layer 131. Accordingly, the sub-active layer 133 may be formed under the data line 141.

The sub-active layer 133 may be a double structure of an amorphous silicon film (not shown) and an n + amorphous silicon film (not shown).

In addition, the sub-active layer 133 may be formed to have the same width as the data line 141 thereabove, or may have a width slightly larger than the data line 141. [

For example, the sub-active layer 133 may be formed to have the same width as the data line 141 or an increased width to a length of about 0.2 μm or less than the width of the data line 141.

In addition, since the sub active layer 133 is formed together with the data line 141, it is possible to prevent the active tail which has occurred in the conventional array substrate.

The pixel electrode 151 is not connected to the data line 141 because the active tail 133 is not formed by the sub active layer 133 formed under the data line 141. Therefore, So as to extend as far as possible.

In other words, when determining the distance between the pixel electrode and the data line in the conventional array substrate, the length of one side of the active tail formed on the data line should be further considered. In the array substrate 100 of this embodiment, Only the distance d3 between the end of the data line 141 and the data line 141 may be considered.

Accordingly, the array substrate 100 according to the present embodiment can increase the area of the pixel region as compared with the conventional array substrate. Such an increase in the area of the pixel region can improve the aperture ratio of the array substrate 100, thereby increasing the transmittance of the liquid crystal display device.

Figs. 6A to 6E are manufacturing process diagrams of the array substrate shown in Fig.

Hereinafter, the manufacturing process of the array substrate 100 of the liquid crystal display device according to the present invention will be described in detail with reference to FIGS. 6A to 6E.

Referring to FIG. 6A, a first metal layer (not shown) may be formed by completely depositing a metal material having a low resistance characteristic on a transparent substrate 101 such as glass.

The first metal layer may be formed of one or more metal materials selected from among low resistance opaque metal materials such as aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), chromium (Cr), molybdenum . In other words, the first metal layer may be formed as a single layer or a multilayer structure of two or more layers with the low resistance opaque metal material described above.

Next, a first metal layer may be selectively patterned through a first mask process to form a gate line (not shown) and a gate electrode 110 connected thereto and a common line (not shown) formed to be in parallel with the gate line.

The first mask process may refer to a series of processes for forming a photoresist pattern and patterning the first metal layer using the photoresist pattern. Here, patterning may mean etching the first metal layer using a photoresist pattern.

In other words, in the first mask process, a photoresist (not shown) is coated on the entire surface of the first metal layer, and a photoresist is selectively exposed and developed by using a mask to form a first photoresist pattern (not shown) can do. The first photoresist pattern may remain on only the region where the gate line, the gate electrode 110 and the common line are to be formed on the substrate 101, or may remain only in the remaining region except for the region.

The first metal layer may be patterned using the first photoresist pattern to form gate lines, gate electrodes 110, and common lines. Next, the first photoresist pattern remaining on the substrate 101 may be stripped.

The gate insulating layer 120 may be formed on the entire surface of the substrate 101 on which the gate line, the gate electrode 110, and the common line are formed through the first mask process.

The gate insulating layer 120 may be formed by depositing an inorganic insulating material such as silicon oxide (SiO 2) or silicon nitride (SiN x) on the entire surface of the substrate 101.

Referring to FIG. 6B, a silicon layer (not shown) and a second metal layer (not shown) may be sequentially formed on the gate insulating layer 120.

The silicon layer may be formed by sequentially depositing an amorphous silicon film and an n + amorphous silicon film on the gate insulating film 120.

The second metal layer may be formed by depositing a metal material selected from an opaque metal material having a low resistance characteristic, such as Cu or a copper alloy, on the silicon layer.

The active pattern 130, the data electrode pattern 140, and the data line 141 may be formed by selectively patterning the second metal layer and the silicon layer through a second mask process.

The second mask process is similar to the first mask process described above. In other words, in the second mask process, a photoresist (not shown) is applied to the entire surface of the second metal layer, and a second photoresist pattern (not shown) is formed by selectively exposing and developing the applied photoresist using a mask can do. The active pattern 130, the data electrode pattern 140, and the data line 141 can be formed by patterning the second metal layer and the silicon layer using the second photoresist pattern. Then, the second photoresist pattern remaining on the substrate 101 can be removed.

Here, the active pattern 130 may be formed to correspond to the gate electrode 110 formed through the first mask process, and may be formed to have a size enough to cover both the side surface and the top surface of the gate electrode 110. The data electrode pattern 140 may be formed to overlap with the active pattern 130. At this time, the active pattern 130 and the data electrode pattern 140 may have the same width, or the active pattern 130 may have a slightly larger width.

In addition, the data line 141 may be formed of a double structure of a silicon layer and a second metal layer. In other words, since the data line 141 is formed by patterning the second metal layer and the silicon layer together through the second mask process, the sub-active layer 133 formed of the silicon layer is positioned below the data line 141 .

The width of the sub-active layer 133 may be equal to or slightly larger than the width of the data line 141 located thereabove.

In other words, the sub-active layer 133 may be formed to have the same width as that of the data line 141 or may have an increased width to a size of 0.2um or less in comparison with the width of the data line 141. [

The sub active layer 133 is formed to have the same or slightly larger width than that of the data line 141. In contrast to the conventional case, the sub active layer 133 is formed by protruding on both sides of the data line 141, The occurrence of tail can be suppressed.

Meanwhile, the second metal layer and the silicon layer may be patterned simultaneously or sequentially through the second mask process. When the second metal layer and the silicon layer are sequentially patterned, a process of ashing the second photoresist pattern after the patterning of the second metal layer may be further performed.

Referring to FIGS. 6B and 6C, a third metal layer (not shown) may be formed on the entire surface of the substrate 101 on which the active pattern 130, the data electrode pattern 140, and the data line 141 are formed.

The third metal layer may be formed by depositing a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Next, the third metal layer may be selectively patterned through a third mask process to form the pixel electrode 151.

The pixel electrode 151 may be formed on the drain electrode 145 to extend to the pixel region of the array substrate 100. In addition, the pixel electrode 151 may be formed on the source electrode 143 in a superimposed manner.

The source electrode 143 and the drain electrode 145 can be formed from the data electrode pattern 140 through the third mask process and the active layer 131 can be formed from the active pattern 130. [

Although the third mask process is similar to the first and second mask processes described above, the first and second mask processes form a photoresist pattern using a general mask, whereas the third mask process uses a half tone ) Mask is used to form a photoresist pattern.

6C, the pixel electrode 151, the source electrode 143, the drain electrode 145, and the active layer 131 are all formed through a single third mask process. Therefore, in the process shown in FIG. 6C, A photoresist pattern can be formed.

Figs. 7A to 7D are detailed flow charts for Fig. 6C.

Hereinafter, the third mask process described above with reference to the drawings will be described in detail.

First, a gate electrode 110, a gate insulating film 120, an active pattern 130, a data electrode pattern 140, and a data line 141 are formed on the substrate 101 through the process of FIG. 6B. Here, a sub-active layer 133 is formed under the data line 141.

Referring to FIG. 7A, a transparent conductive material may be deposited on the entire surface of the substrate 101 to form a third metal layer 150.

Next, a photoresist (not shown) is coated on the entire surface of the third metal layer 150, and then a photoresist is selectively exposed and developed using a halftone mask (not shown) to form a third photoresist pattern 210 .

The third photoresist pattern 210 may have three different regions by a halftone mask. For example, the third photoresist pattern 210 may include a transmissive region III corresponding to the transmissive region of the halftone mask, from which the photoresist is completely removed, a semi-transmissive region corresponding to the semi-transmissive region of the halftone mask, And the blocking region (I) corresponding to the blocking region of the region (II) and the halftone mask and the photoresist is not removed. A part of the data electrode pattern 140 can be exposed by the transmissive region III of the third photoresist pattern 210. [

7A and 7B, the pixel electrode pattern 150 ', the source electrode 143 and the drain electrode 145 are formed by performing the patterning process at least twice using the third photoresist pattern 210 .

In other words, the pixel electrode pattern 150 'can be formed by patterning the third metal layer 150 using the third photoresist pattern 210.

The source electrode 143 and the drain electrode 145 may be formed by patterning the data electrode pattern 140 using the third photoresist pattern 210 and the pixel electrode pattern 150 '.

The pixel electrode pattern 150 ', the source electrode 143, and the drain electrode 145 may be formed to be spaced apart from each other in the channel region of the active pattern 130.

In the patterning process for forming the pixel electrode pattern 150 ', the source electrode 143, and the drain electrode 145, wet patterning may be used, but is not limited thereto.

On the other hand, the source electrode 143 and the drain electrode 145 can be over-etched more than the pixel electrode pattern 150 'due to the characteristics of the patterning process. 7B, the pixel electrode pattern 150 'may have a structure protruding from the ends of the source electrode 143 and the drain electrode 145. In this case,

After the pixel electrode pattern 150 ', the source electrode 143 and the drain electrode 145 are formed, the ashed third photoresist pattern 215 may be formed by ashing the third photoresist pattern 210.

In other words, the third photoresist pattern 215 ashed by ashing the third photoresist pattern 210 is removed only in the thin film transistor region and the pixel region of the array substrate 100 after the transflective region II is removed .

Referring to FIGS. 7B and 7C, the pixel electrode 151 may be formed by patterning the pixel electrode pattern 150 'using the ashed third photoresist pattern 215. FIG.

The pixel electrode 151 may overlap the drain electrode 145 and extend to a pixel region. In addition, the pixel electrode 151 may be overlapped with the source electrode 143.

The protruding portions of the pixel electrode pattern 150 'corresponding to the channel region of the active pattern 130, that is, the portions protruding from the ends of the source electrode 143 and the drain electrode 145, The pixel electrode pattern 150 'may be removed by patterning the pixel electrode pattern 150' again using the second insulating layer 215. As a result, the channel region of the active pattern 130 is exposed.

Then, the pixel electrode pattern 150 'of the thin film transistor region of the array substrate and the remaining region excluding the pixel region, that is, the pixel region 150' of the link region where the data line 141 is formed, can be removed.

Referring to FIGS. 7C and 7D, after the pixel electrode 151 is formed, the ashed third photoresist pattern 215 remaining on the substrate 101 may be removed.

The channel region of the active pattern 130 is patterned using the pixel electrode 151, the source electrode 143 and the drain electrode 145 to pattern and remove the n + amorphous semiconductor layer (not shown) ) Can be formed.

In other words, the active pattern 130 is composed of a channel region and a source / drain region, and may be a double structure of an amorphous silicon film and an n + amorphous silicon film. The n + amorphous silicon film can be removed in the channel region of the active pattern 130 through the above-described process. The n + amorphous silicon film remaining in the source / drain regions of the active pattern 130 is electrically connected to the source electrode 143 and the active layer 131 or between the drain electrode 145 and the active layer 131, Can play a role.

Referring again to FIG. 6D, an interlayer insulating layer 160 may be formed on the entire surface of the substrate 101 on which the pixel electrode 151 is formed, to a predetermined thickness.

The interlayer insulating layer 160 may be formed by depositing a selected one of inorganic insulating materials such as SiO2 or SiNx. The interlayer insulating layer 160 may be formed by applying an organic insulating material such as benzocyclobutene (BCB) or photo acryl.

Then, a contact hole 165 may be formed in the interlayer insulating layer 160 through a fourth mask process. The contact hole 165 may expose a part of the data line 141.

The fourth mask process is similar to the first and second mask processes described above, and a detailed description thereof will be omitted.

Referring to FIG. 6E, a fourth metal layer (not shown) may be formed on the entire surface of the substrate 101 on which the interlayer insulating film 160 having the contact holes 165 is formed. The fourth metal layer may be formed by depositing a transparent conductive material such as ITO or IZO.

Next, the fourth metal layer may be selectively patterned through the fifth mask process to form the common electrode 170. The common electrodes 170 may be formed as a plurality of fingers in a bar shape corresponding to pixel regions of the array substrate and spaced apart from each other by a predetermined distance. The plurality of bar shapes of the common electrode 170 may be formed to correspond to the pixel electrode 151.

In addition, the common electrode 170 may be formed to be connected to the data line 141 through the contact hole 165.

As described above, the array substrate 100 of the present embodiment can be completed through five mask processes. After the data line 141 having the sub active layer 133 is formed through the second mask process, the active layer 131, the source electrode 143, the drain electrode 145, And the pixel electrode 151 can be formed.

Since the data line 141 is formed first in the masking process in the array substrate 100 of the present embodiment, the data line 141 and the subactive layer 133 under the data line 141 can be formed to have substantially the same width. Accordingly, the pixel electrode 151 formed through the subsequent mask process can be formed as close as possible to one side of the data line 141 while keeping the distance d3 from the data line 141.

That is, the liquid crystal display according to the present invention can form the pixel electrode 151 in the pixel region of the array substrate 100 as large as possible, thereby increasing the aperture ratio of the pixel region. Such an increase in the aperture ratio increases the transmittance of the liquid crystal display device.

8 is a graph showing the relationship between the active tail and the transmittance in the liquid crystal display device.

8, it can be seen that the transmittance of the liquid crystal display improves as the size of the active tail, that is, the shorter the length of the subactive layer protruding from both sides of the data line is shortened.

That is, according to the method of manufacturing a liquid crystal display device according to the present invention, since the data line and the subactive layer below it are formed to have substantially the same width or the subactive layer has a slightly larger width, Can be generated with a size of 0.2 um or less. Accordingly, it can be seen that the transmittance of the liquid crystal display device is increased by about 5% as compared with the case where the active tail is generated at 2.2 μm in the conventional liquid crystal display device.

The amorphous silicon thin film transistor using the amorphous silicon thin film as the active layer is described as an example of the array substrate of the liquid crystal display according to the present invention. However, the present invention is not limited to this, The present invention can also be applied to a polycrystalline silicon thin film transistor using a thin film.

Although the liquid crystal display device according to the present invention has been described by way of example of a liquid crystal display device of a transverse electric field system, the present invention is not limited thereto. The present invention can be applied to a liquid crystal display device of a twisted nematic type or a vertical alignment (VA) Type liquid crystal display device.

In addition, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) have.

While a number of embodiments have been described in detail above, it should be construed as being illustrative of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

100: array substrate 110: gate electrode
131: active layer 133: sub active layer
141: Data line 143: Source electrode
145: drain electrode 151: pixel electrode
170: common electrode

Claims (15)

Depositing and selectively patterning a first metal layer on the substrate to form a gate electrode;
Forming an active pattern, a data electrode pattern, and a data line by sequentially depositing a silicon layer and a second metal layer on the substrate having the gate electrode formed thereon and selectively patterning the same; And
And forming a third metal layer on the substrate on which the active pattern, the data electrode pattern, and the data line are formed, and selectively patterning the third metal layer to form an active layer, a source electrode, a drain electrode, and a pixel electrode. The method according to claim 1,
The forming of the active pattern, the data electrode pattern, and the data line may include:
Applying a photoresist on the second metal layer and selectively exposing and developing the photoresist using a mask to form a photoresist pattern; And
And patterning the second metal layer and the silicon layer together using the photoresist pattern to form the active pattern, the data electrode pattern, and the data line. The method according to claim 1,
Wherein the data line is formed by a dual structure of the second metal layer and the silicon layer. The method of claim 3,
Wherein the silicon layer is formed to have the same width as the width of the second metal layer. The method of claim 3,
Wherein the silicon layer is formed to have an increased width to a length of 0.2 m or less than the width of the second metal layer. The method according to claim 1,
Wherein the pixel electrode is spaced apart from the one side of the data line by a distance of 3.5 mu m or less. The method according to claim 1,
Wherein the active layer, the source electrode, the drain electrode, and the pixel electrode are formed by patterning the third metal layer deposited on the substrate at least twice or more. The method according to claim 1,
The step of forming the active layer, the source electrode, the drain electrode,
Applying a photoresist on the third metal layer and selectively exposing and developing the photoresist using a halftone mask to form a photoresist pattern;
Forming a pixel electrode pattern by patterning the third metal layer using the photoresist pattern;
Forming the source electrode and the drain electrode by patterning the data electrode pattern using the photoresist pattern and the pixel electrode pattern; And
And patterning the pixel electrode pattern to form the pixel electrode. 9. The method of claim 8,
Further comprising ashing the photoresist pattern after forming the source electrode and the drain electrode,
Wherein the pixel electrode is formed by patterning the pixel electrode pattern using an ashed photoresist pattern. 9. The method of claim 8,
Wherein the forming of the pixel electrode pattern is performed such that a portion of the third metal layer corresponding to the channel region of the active pattern protrudes from the end of each of the source electrode and the drain electrode. 9. The method of claim 8,
The silicon layer has a dual structure of an amorphous silicon film and an n + amorphous silicon film,
After forming the pixel electrode,
Removing the photoresist pattern remaining on the substrate; And
And patterning the n + amorphous silicon film of the silicon layer in the channel region of the active pattern using the pixel electrode, the source electrode, and the drain electrode. 9. The method of claim 8,
Wherein the pixel electrode is formed to overlap the source electrode and the drain electrode. The method according to claim 1,
Forming an interlayer insulating film on the substrate on which the active layer, the source electrode, the drain electrode, and the pixel electrode are formed; And
Further comprising forming a common electrode by depositing a fourth metal layer on the substrate on which the interlayer insulating film is formed and selectively patterning the fourth metal layer. 14. The method of claim 13,
Forming a contact hole exposing the data line by selectively patterning the interlayer insulating film,
And the common electrode is formed to fill the contact hole and contact the data line. 14. The method of claim 13,
And a portion of the common electrode corresponding to the pixel electrode is patterned in a finger shape.

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