KR20150073544A - Gate shift register and and driving method the same - Google Patents

Abstract

The present invention relates to a gate shift register and a driving method thereof, and more particularly, to a gate shift register including a plurality of stages for sequentially outputting scan pulses using a plurality of gate shift clocks; Each of the stages includes a voltage generator for generating a high potential or a low potential by switching the input first and second AC voltages; A node controller for controlling charge and discharge of the Q node and the QB node using the high potential voltage or the low potential voltage provided from the voltage generator; And an output unit for outputting the scan pulse according to a voltage level of the Q node and the QB node; The first and second AC voltages have a gate high voltage or a gate low voltage and are phase-shifted every frame, and are opposite in phase to each other.

Description

[0001] GATE SHIFT REGISTER AND DRIVING METHOD [0002]

The present invention relates to a gate shift register and a driving method thereof.

Recently, a GIP (Gate In Panel) type display device has been proposed in which a gate driver is incorporated in a display panel to reduce the volume and weight of a flat panel display. In the GIP type display device, the gate driver is composed of an amorphous silicon thin film transistor (hereinafter referred to as TFT) and is embedded in a non-display area of the display panel. The gate driver includes a gate shift register that sequentially outputs scan pulses.

On the other hand, recent flat panel displays are in a trend of high resolution and narrow bezel. Therefore, efforts to reduce the design area of the gate driver embedded in the display panel are continuously required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gate shift register which is easy to design a narrow bezel and a driving method thereof.

According to an aspect of the present invention, there is provided a gate shift register including a plurality of stages for sequentially outputting scan pulses using a plurality of gate shift clocks; Each of the stages includes a voltage generator for generating a high potential or a low potential by switching the input first and second AC voltages; A node controller for controlling charge and discharge of the Q node and the QB node using the high potential voltage or the low potential voltage provided from the voltage generator; And an output unit for outputting the scan pulse according to a voltage level of the Q node and the QB node; The first and second AC voltages have a gate high voltage or a gate low voltage and are phase-shifted every frame, and are opposite in phase to each other.

Wherein the voltage generator is switched in accordance with the first AC voltage and the first AC voltage is the gate high voltage and the second AC voltage is turned on in an odd frame period in which the gate low voltage is applied, A first switch for outputting a voltage as the low potential voltage; The first alternating voltage is switched in accordance with the second alternating voltage and the second alternating voltage is the gate high voltage and the first alternating voltage is turned on in an even frame period in which the gate is low, And a second switch for outputting the potential as a potential voltage.

A third switch which is switched according to the first AC voltage and is turned on in the odd frame period to output the first AC voltage as the high potential voltage; And a fourth switch that is switched according to the second AC voltage and is turned on in the even frame period to output the second AC voltage as the high potential voltage.

Wherein the node control unit is responsive to at least one preceding carry signal provided from at least one of the previous single stages and at least one subsequent carry signal provided from at least one of the following single stages, And a plurality of TFTs for controlling discharge.

Each of the stages outputs first and second scan pulses, and has first and second sub stages having the same circuit configuration; Wherein each of the first and second sub-stages has a node control unit and an output unit; The node control unit includes: a first TFT for applying the high potential voltage provided from the voltage generation unit to the Q node in response to the previous carry signal input to the first input terminal; A second TFT for applying the low potential voltage provided from the voltage generator to the Q node in response to the rear stage carry signal input to the second input terminal; A third TFT for applying the low potential voltage to the Q node according to a voltage state of the first QB node; A fourth TFT for applying the low potential voltage to the Q node according to a voltage state of the second QB node; A fifth TFT for applying the low potential voltage to the first QB node in response to the previous carry signal; A sixth TFT for applying the first alternating voltage to the set node in accordance with the first alternating voltage or applying the second alternating voltage to the set node in accordance with the second alternating voltage; A seventh TFT for applying the low potential voltage to the set node according to a voltage state of the Q node; An eighth TFT for applying the first AC voltage to the first QB node according to a voltage state of the set node; A ninth TFT for applying the low potential voltage to the first QB node according to a voltage state of the Q node; And a tenth TFT for applying the low potential voltage to the set node according to a voltage state of the Q node of the first sub stage or a voltage state of the Q node of the second sub stage; The output section including: a pull-up TFT for applying the input gate shift clock to an output terminal according to a voltage state of the Q node; A first pull-down TFT for applying the low potential voltage to the output terminal according to a voltage state of the first QB node; And a second pull-down TFT for applying the low potential voltage to the output terminal in accordance with a voltage state of the second QB node.

According to another aspect of the present invention, there is provided a method of driving a gate shift register including a plurality of stages sequentially outputting scan pulses using a plurality of gate shift clocks, A driving method of a shift register including a voltage generating unit, a node control unit and an output unit, the method comprising: generating a high or low potential voltage by switching the first and second AC voltages inputted by the voltage generating unit; The node control unit controlling charge and discharge of the Q node and the QB node using the high potential voltage or the low potential voltage provided from the voltage generating unit; And outputting the scan pulse according to a voltage level of the Q node and the QB node; The first and second AC voltages have a gate high voltage or a gate low voltage and are phase-shifted every frame, and are opposite in phase to each other.

Wherein the step of generating the low potential voltage by the voltage generating section includes the step of generating the first alternating voltage in accordance with the first alternating voltage in the odd frame period in which the first alternating voltage is the gate high voltage and the second alternating voltage is the gate low voltage, Outputting the second alternating-current voltage as the low-potential voltage using a switch; Wherein the second alternating voltage is switched in accordance with the second alternating voltage in an even frame period in which the second alternating voltage is the gate high voltage and the first alternating voltage is the gate low voltage, And outputting a second switch which outputs the low potential voltage as a low potential voltage.

Wherein the step of generating the high voltage by the voltage generating unit includes the steps of outputting the first alternating voltage as the high potential voltage using the third switch which is switched in accordance with the first alternating voltage in the odd frame period; And outputting the second alternating voltage as the high potential voltage by using a fourth switch which is switched in accordance with the second alternating voltage in the even frame period.

Wherein the node control unit is responsive to at least one preceding carry signal provided from at least one of the previous single stages and at least one subsequent carry signal provided from at least one of the following single stages, And the discharge is controlled.

In the gate shift register of the present invention, each stage generates a high-potential voltage or a low-potential voltage by itself using a voltage generator. Therefore, the gate shift register of the present invention does not need to separately supply the high-potential voltage and the low-potential voltage from the outside. Therefore, the gate shift register according to the present invention can eliminate the high-potential voltage supply line and the low-potential voltage supply line. Accordingly, the present invention can easily design the narrow bezel by reducing the design area of the signal line for driving the gate driver in the GIP type flat panel display. In addition, since the timing controller and the power supply unit, which functioned to supply the high-potential voltage or the low-potential voltage, can reduce the number of output pins, manufacturing cost is reduced.

1 is a configuration diagram of a gate shift register according to an embodiment of the present invention.
2 is a driving waveform diagram of the gate shift register shown in FIG.
Fig. 3 is a configuration diagram of the first stage ST1 shown in Fig.
4 is a configuration diagram of the voltage generator 30 shown in FIG.
5 is a configuration diagram of a first stage ST1 according to another embodiment of the present invention.
6 is a configuration diagram of a first stage ST1 according to another embodiment of the present invention.

Hereinafter, a gate shift register and a driving method thereof according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a gate shift register according to an embodiment of the present invention. 2 is a driving waveform diagram of the gate shift register shown in FIG.

Referring to FIG. 1, the gate shift register includes a plurality of stages ST connected in a dependent manner, and at least two dummy stages DT.

The plurality of stages ST sequentially output the scan pulse VOUT using a plurality of gate shift clocks CLKs. To this end, a plurality of gate shift clocks (CLKs), at least one start pulse (Vst1, Vst2), and first and second alternating voltages (VDD_O, VDD_E) are externally supplied to each stage (ST).

In particular, in the gate shift register of the present invention, each stage ST itself generates a high-potential voltage (VDD) or a low-potential voltage (VSS) by using a voltage generator (see FIGS. Therefore, the gate shift register of the present invention does not need to separately supply the high-potential voltage VDD and the low-potential voltage VSS from the outside. Therefore, the gate shift register according to the present invention can eliminate the high-potential voltage (VDD) supply line and the low-potential voltage (VSS) supply line. Accordingly, the present invention can easily design the narrow bezel by reducing the design area of the signal line for driving the gate driver in the GIP type flat panel display. In addition, since the timing controller and the power supply unit, which have functioned to supply the high-potential voltage (VDD) or the low-potential voltage (VSS), can reduce the number of output pins, manufacturing cost is reduced. This will be described later in detail with reference to FIG. 2 to FIG.

Each stage ST has two output terminals and outputs two scan pulses VOUT. The scan pulse VOUT is applied to the gate line of the flat panel display device and serves as a carry signal supplied to the front stage and the rear stage.

In the following description, the "front stage" is located above the reference stage. For example, the front stage based on the k-th stage (k) 1) to the first dummy stage DT0 ". Stage is referred to as a " k + 1 stage (STk + 1) " to a second and a third dummy stage " Indicate which one. The first dummy stage DT (0) outputs a carry signal to be inputted to the subsequent stage, and the second and third dummy stages output a carry signal to be inputted to the preceding stage.

Each stage ST has carry signals of two different front end stages applied to the first and third input terminals IN1 and IN3 and carry signals of two different front end stages applied to the second and fourth input terminals IN2 and IN4, And operates in response to the carry signals of the two trailing stages. First and second start pulses Vst1 and Vst2 provided from an external (timing controller) are respectively input to the first and third input terminals IN1 and IN3 of the first stage ST1 instead of the carry signal of the previous stage .

Referring to FIG. 2, gate shift clocks (CLKs) are shifted by one horizontal period, and are implemented in six phases. Each gate shift clock (CLK) has a pulse width of 3 horizontal periods (3H). The gate shift clocks (CLKs) are successively outputted, and the two gate shift clocks (CLK) are overlapped with each other by two horizontal periods. And gate shift clocks (CLKs) repeatedly swing with a gate high voltage (VGH) or a gate low voltage (VGL). The first and second AC voltages VDD_O and VDD_E have a gate high voltage VGH or a gate low voltage VGL and are phase-shifted every frame and are opposite in phase to each other. For example, the first AC voltage VDD_O is the gate high voltage VGH in the odd frame period and the gate low voltage VGL in the even frame period. The second AC voltage VDD_E is the gate low voltage VGL in the odd frame period and the gate high voltage VGH in the even frame period.

Fig. 3 is a configuration diagram of the first stage ST1 shown in Fig. 4 is a configuration diagram of the voltage generator 30 shown in FIG.

The circuit configuration of the first stage ST1 is the same as that of the remaining stages, and the first stage ST1 will be described below as an example.

3, the first stage ST includes a voltage generator (not shown) for generating a high-potential voltage VDD or a low-potential voltage VSS by switching the inputted first and second alternating-current voltages VDD_O and VDD_E 30).

The voltage generator 30 of the present invention uses the characteristic that the first and second alternating voltages VDD_O and VDD_E alternate with each other every frame and has the gate low voltage VGL to lower the gate low voltage VGL And outputs it as the potential voltage VSS. 4, the voltage generator 30 is switched according to the first AC voltage VDD_O and turned on in the odd frame period to turn the second AC voltage VDD_E to the low voltage (VSS); And a second switch SW2 that is switched in accordance with the second AC voltage VDD_E and turned on in the even frame period to output the first AC voltage VDD_O as the low potential voltage VSS.

The first and second switches SW1 and SW2 are turned on alternately in every frame period. Therefore, the voltage generating unit 30 outputs the second AC voltage VDD_E as the low voltage VSS during the odd frame period and the first AC voltage VDD_O as the low voltage VSS during the even frame period Output. Therefore, the voltage generator 30 can output the gate-low voltage VGL as the low-potential voltage VSS every frame period.

The voltage generator 30 generates the gate high voltage VGH using the characteristic that the first and second AC voltages VDD_O and VDD_E alternate with each other every frame and has the gate high voltage VGH. As a high-potential voltage (VDD). 4, the voltage generator 30 is switched in accordance with the first AC voltage VDD_O and turned on in the odd frame period to convert the first AC voltage VDD_O to the high voltage (VDD); And a fourth switch SW4 switched according to the second AC voltage VDD_E and turned on in the even frame period to output the second AC voltage VDD_E as the high potential voltage VDD.

The third and fourth switches SW3 and SW4 are turned on alternately for every frame period. Therefore, the voltage generator 30 outputs the first AC voltage VDD_O as the high-potential voltage VDD in the odd frame period and the second AC voltage VDD_E as the high-potential voltage VDD in the even frame period Output. Therefore, the voltage generating section 30 can output the gate high voltage VGH as the high potential voltage VDD every frame period.

In another embodiment of the present invention, the voltage generator 30 may include only the first and second switches SW1 and SW2 among the first to fourth switches SW1 to SW4. In this case, as shown in Fig. 5, each stage ST receives the high-potential voltage VDD from the outside and generates the low-potential voltage VSS itself.

In still another embodiment of the present invention, the voltage generator 30 may include only the third and fourth switches SW3 and SW4 among the first to fourth switches SW1 to SW4. In this case, as shown in Fig. 6, each stage ST receives the low potential voltage VSS from the outside and generates the high potential voltage VDD itself.

For reference, the gate high voltage VGH is set to a voltage higher than the threshold voltage of the TFTs formed on the display panel, and the gate low voltage VGL is set to a voltage lower than the threshold voltage of the TFTs formed on the display panel. For example, the gate high voltage VGH may be set to 20V to 30V, and the gate low voltage VGL may be set to -5V. The high-potential voltage VDD has a voltage higher than the low-potential voltage VSS. For example, the high potential voltage VDD may be the gate high voltage VGH and the low potential voltage VSS may be the gate low voltage VGL.

The low potential voltage VSS and the high potential voltage VSS generated from the voltage generating unit 30 are supplied to the node control unit so that the node control unit is used to control the discharge of the Q node and the QB node. Further, the low potential voltage VSS generated from the voltage generating section 30 is supplied to the output section, and the output section is used to discharge the output terminal. This will be described in detail as follows.

3, the first stage ST1 includes first and second sub stages 10 and 20 which output the first and second scan pulses VOUT1 and VOUT2 respectively and have the same circuit configuration . Each of the first and second sub stages 10 and 20 has a node control unit and an output unit. Since the first sub stage 10 and the second sub stage 10 have the same circuit configuration, only the configuration of the first sub stage 10 will be described below.

Wherein the node control unit is responsive to at least one preceding carry signal provided from at least one of the previous single stages and at least one subsequent carry signal provided from at least one of the following single stages, And a plurality of TFTs for controlling discharge.

The output section includes at least one pull-up TFT for applying an input gate shift clock to the output terminal in accordance with the voltage state of at least one Q node, at least one pull-up TFT for applying a low potential voltage to the output terminal in accordance with the voltage level of at least one QB Pull-down TFT.

In FIG. 3, the Q node included in the first sub-stage 10 is denoted by Q1 and the Q node of the second sub-stage 20 is denoted by Q2. 3, the first and second QB nodes provided in the first sub-stage 10 are denoted by QB11 and QB12, and the first and second QB nodes provided in the second sub- The nodes are labeled 'QB21' and 'QB22'.

The node controller T1 ~ T10 )

The node control unit includes first to tenth TFTs T1 to T10.

The first TFT T1 applies the high potential voltage VDD provided from the voltage generating section 30 to the Q node Q1 in response to the front carry signal input to the first input terminal IN1. The first start pulse Vst1 is input to the first input terminal IN1 of the first stage ST1 instead of the preceding carry signal. The first TFT T1 provided in the second sub stage 20 operates in response to the front carry signal input to the third input terminal IN3 (different from that input to the first input terminal). A second start pulse Vst2 is input to the third input terminal IN3 of the first stage ST1 instead of the preceding carry signal.

The second TFT T2 applies the low potential voltage VSS provided from the voltage generating section 30 to the Q node Q1 in response to the subsequent carry signal inputted to the second input terminal IN2. The second TFT T2 provided in the second sub stage 20 operates in response to the last carry signal input to the fourth input terminal IN4 (different from that input to the second input terminal).

The third TFT T3 applies the low potential voltage VSS to the Q node Q1 according to the voltage state of the first QB node QB11.

The fourth TFT T4 applies the low potential voltage VSS to the Q node Q1 according to the voltage state of the second QB node QB12.

The fifth TFT T5 applies the low potential voltage VSS to the first QB node QB11 in response to the front carry signal input to the first input terminal IN1.

The sixth TFT T6 applies the first AC voltage VDD_O to the set node SN in accordance with the first AC voltage VDD_O or the second AC voltage VDD_E in accordance with the second AC voltage VDD_E To the set node SN.

The seventh TFT T7 applies the low potential voltage VSS to the set node SN in accordance with the voltage state of the Q node Q1.

The eighth TFT T8 applies the first AC voltage VDD_O_ to the first QB node QB11 according to the voltage state of the set node SN.

The ninth TFT T9 applies the low potential voltage VSS to the first QB node QB11 according to the voltage state of the Q node Q1.

The tenth TFT T10 sets the low potential voltage VSS according to the voltage state of the Q node Q1 of the first sub stage 10 or the voltage state of the Q node Q2 of the second sub stage 20 To the node SN.

Output ( TU , TD1 , TD2 )

The output section includes a pull-up TFT (TU) and first and second pull-down TFTs (TD1, TD2).

The pull-up TFT (TU) applies the input gate shift clock to the output terminal in accordance with the voltage state of the Q node (Q1). Two consecutively outputted gate shift clocks CLK are input to the first and second sub stages 10 and 20, respectively. For example, the first gate shift clock CLK1 may be input to the first sub stage 10, and the second gate shift clock CLK2 may be input to the second sub stage 20. For example,

The first pull-down TFT (TD1) applies the low potential voltage (VSS) to the output terminal in accordance with the voltage state of the first QB node (QB11).

The second pull-down TFT (TD2) applies the low potential voltage (VSS) to the output terminal in accordance with the voltage state of the second QB node (QB12).

On the other hand, the first and second sub-stages 10 and 20 share the first and second QB nodes with each other as shown in Fig. More specifically, the first QB node QB11 of the first sub-stage 10 is connected to the second QB node QB22 of the second sub-stage 20. The second QB node QB12 of the first sub stage 10 is connected to the first QB node QB21 of the second sub stage 20. [ Accordingly, the present invention can reduce the number of TFTs for charging and discharging the first and second QB nodes provided in the first and second sub-stages 10 and 20 by half, The design area of the gate driver is reduced to facilitate the design of the narrow bezel.

Hereinafter, the driving method of the first stage ST1 will be described step by step with reference to FIG. 2 and FIG. 3. FIG. And an odd frame period will be described as an example.

In the odd frame period, the first AC voltage VDD_O is the gate high voltage VGH and the second AC voltage VDD_E is the gate low voltage VGL. The voltage generating unit 30 switches the first and second AC voltages VDD_O and VDD_E using the first to fourth switches SW1 to SW4 and switches between the high potential voltage VDD and the low potential voltage VSS, .

In the first and second periods t1 and t2, the first gate start pulse Vst1 is input as a preceding carry signal via the first input terminal IN1 and the first gate start pulse Vst1 is input as the previous carry signal via the third input terminal IN3. And the two gate start pulses Vst2 are input as the other preceding carry signals. The first and fifth TFTs T1 and T5 are turned on in response to the first gate start pulse Vst1 and the Q nodes Q1 and Q2 of the first and second sub stages 10 and 20 are turned on The high-potential voltage VDD is sequentially applied. The fifth TFT T5 applies a low voltage VSS to the first and second QB nodes QB11, QB12, QB21 and QB22 of the first and second sub stages 10 and 20, And discharges and initializes the first and second QB nodes QB11, QB12, QB21, and QB22.

On the other hand, as the high potential voltage VDD is applied to the Q nodes Q1 and Q2, the ninth and tenth TFTs T9 and T10 are turned on. Then the ninth TFT T9 applies a low potential voltage VSS to the first and second QB nodes QB11, QB12, QB21 and QB22 of the first and second sub stages 10 and 20, And discharges and initializes the first and second QB nodes QB11, QB12, QB21, and QB22. The tenth TFT T10 applies a low potential voltage VSS to the set nodes SN provided in the first and second sub stages 10 and 20 to initialize the set nodes SN.

Subsequently, in the third and fourth periods t3 and t4, the first and second gate shift clocks CLK1 and CLK2 are output in the state of a gate high voltage (VGH) and supplied to the drain of the pull-up TFT TU . Then, the voltage level of the Q nodes Q1 and Q2 is bootstrapped by the parasitic capacitance between the gate and the drain of the pull-up TFT TU, and is raised to a voltage higher than the gate high voltage VGH. Then, the pull-up TFT TU is completely turned on and the first and second gate shift clocks CLK1 and CLK2 in the gate high voltage (VGH) state through the pull-up TFT TU are applied to the scan pulses VOUT1 and VOUT2 .

Next, in the fifth and sixth periods t5 and t6, the carry signal is input through the second input terminal IN2 and the other carry signal is input through the fourth input terminal IN4. Then, the second TFT T2 is turned on in response to the subsequent carry signals, and the low potential voltage VSS is sequentially applied to the Q nodes Q1 and Q2. Then, the pull-up TFTs TU and the ninth and tenth TFTs T9 and T10 are turned off. At this time, the sixth TFT T6 of the first sub-stage 10 applies the first AC voltage VDD_O which is the gate high voltage VGH to the set node SN. Thus, the eighth TFT T8 of the first sub-stage 10 is turned on to supply the first AC voltage VDD_O, which is the gate high voltage VGH, to the first QB node QB11 of the first sub- And the second QB node QB22 of the second sub-stage 20. [ Then, the first pull down TFT (TD1) of the first sub stage (10) and the second pull down TFT (TD2) of the second sub stage (20) are turned on. Thus, the output terminals of the first and second sub-stages 10 and 20 are discharged to the low potential voltage VSS.

The driving method of the first stage ST1 in the even frame is performed by the second pull down TFT TD2 of the first sub stage 10 and the first pull down TFT TD1 of the second sub stage 20, (VOUT1, VOUT2) is controlled.

As described above, in the gate shift register of the present invention, each stage ST itself generates a high-potential voltage (VDD) or a low-potential voltage (VSS) by using a voltage generator (see Figs. 3 and 30) . Therefore, the gate shift register of the present invention does not need to separately supply the high-potential voltage VDD and the low-potential voltage VSS from the outside. Therefore, the gate shift register according to the present invention can eliminate the high-potential voltage (VDD) supply line and the low-potential voltage (VSS) supply line. Accordingly, the present invention can easily design the narrow bezel by reducing the design area of the signal line for driving the gate driver in the GIP type flat panel display. In addition, since the timing controller and the power supply unit, which have functioned to supply the high-potential voltage (VDD) or the low-potential voltage (VSS), can reduce the number of output pins, manufacturing cost is reduced.

Meanwhile, in the embodiment of the present invention described above, each stage provided in the gate shift register is configured to output two scan pulses at a time. However, the present invention is applicable to a dual pull-down type in which each stage is driven by using first and second AC voltages, as disclosed in Korean Patent Laid-Open No. 10-2007-0043079 proposed by the present applicant, Scheme, it can be applied to any shift register.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims and their equivalents. Will be apparent to those of ordinary skill in the art.

30: voltage generating unit VDD_O: first AC voltage
VDD_E: second AC voltage VDD: high potential voltage
VSS: low potential voltage

Claims (10)

A plurality of stages for sequentially outputting scan pulses using a plurality of gate shift clocks;
Each of the stages
A voltage generator for generating a high potential or a low potential by switching the input first and second AC voltages;
A node controller for controlling charge and discharge of the Q node and the QB node using the high potential voltage or the low potential voltage provided from the voltage generator;
And an output unit for outputting the scan pulse according to a voltage level of the Q node and the QB node;
Wherein the first and second AC voltages have a gate high voltage or a gate low voltage and are phase-shifted every frame and are opposite in phase to each other. The method according to claim 1,
The voltage generator
And the second alternating voltage is turned on in an odd frame period in which the second alternating voltage is the gate-low voltage, and the second alternating voltage is switched in accordance with the first alternating voltage, A first switch for outputting as a potential voltage;
The first alternating voltage is switched in accordance with the second alternating voltage and the second alternating voltage is the gate high voltage and the first alternating voltage is turned on in an even frame period in which the gate is low, And a second switch for outputting the potential as a potential voltage. The method of claim 2,
The voltage generator
A third switch which is switched in accordance with the first AC voltage and is turned on in the odd frame period to output the first AC voltage as the high potential voltage;
And a fourth switch which is switched according to the second AC voltage and is turned on in the even frame period to output the second AC voltage as the high potential voltage. The method according to claim 1,
The node control unit
At least one preceding carry signal provided from at least one of the previous single stages and at least one subsequent carry signal provided from at least one of the following single stages to control the charging and discharging of the Q node and the QB node And a plurality of thin film transistors (TFTs) connected in parallel. The method of claim 4,
Each of the stages outputs first and second scan pulses, and has first and second sub stages having the same circuit configuration;
Wherein each of the first and second sub-stages has a node control unit and an output unit;
The node control unit
A first TFT for applying the high potential voltage provided from the voltage generator to the Q node in response to the front carry signal input to the first input terminal;
A second TFT for applying the low potential voltage provided from the voltage generator to the Q node in response to the rear stage carry signal input to the second input terminal;
A third TFT for applying the low potential voltage to the Q node according to a voltage state of the first QB node;
A fourth TFT for applying the low potential voltage to the Q node according to a voltage state of the second QB node;
A fifth TFT for applying the low potential voltage to the first QB node in response to the previous carry signal;
A sixth TFT for applying the first alternating voltage to the set node according to the first alternating voltage or applying the second alternating voltage to the set node according to the second alternating voltage;
A seventh TFT for applying the low potential voltage to the set node according to a voltage state of the Q node;
An eighth TFT for applying the first AC voltage to the first QB node according to a voltage state of the set node;
A ninth TFT for applying the low potential voltage to the first QB node according to a voltage state of the Q node;
And a tenth TFT for applying the low potential voltage to the set node according to a voltage state of the Q node of the first sub stage or a voltage state of the Q node of the second sub stage;
The output
A pull-up TFT for applying the input gate shift clock to an output terminal according to a voltage state of the Q node;
A first pull-down TFT for applying the low potential voltage to the output terminal according to a voltage state of the first QB node;
And a second pull-down TFT for applying the low potential voltage to the output terminal according to a voltage state of the second QB node. The method of claim 5,
Wherein the first QB node of the first sub-stage is connected to the second QB node of the second sub-stage and the second QB node of the first sub-stage is connected to the first QB node of the first sub-stage Feature gate shift register. A driving method of a shift register having a plurality of stages for sequentially outputting scan pulses using a plurality of gate shift clocks, each of the stages including a voltage generating portion, a node control portion, and an output portion,
Switching the first and second AC voltages inputted by the voltage generator to generate a high-potential voltage or a low-potential voltage;
The node control unit controlling charge and discharge of the Q node and the QB node using the high potential voltage or the low potential voltage provided from the voltage generating unit;
And outputting the scan pulse according to a voltage level of the Q node and the QB node;
Wherein the first and second AC voltages have a gate high voltage or a gate low voltage and are phase-shifted every frame and are opposite in phase to each other. The method of claim 7,
Wherein the step of generating the low voltage comprises:
Using the first switch that is switched in accordance with the first alternating voltage in an odd frame period in which the first alternating voltage is the gate high voltage and the second alternating voltage is the gate low voltage, As a low potential voltage;
Wherein the second alternating voltage is switched in accordance with the second alternating voltage in an even frame period in which the second alternating voltage is the gate high voltage and the first alternating voltage is the gate low voltage, And outputting a second switch which outputs the low potential voltage as a low potential voltage. The method of claim 8,
Wherein the step of generating the high voltage comprises:
Outputting the first alternating voltage as the high potential voltage using the third switch which is switched in accordance with the first alternating voltage in the odd frame period;
And outputting the second AC voltage as the high potential voltage by using a fourth switch which is switched in accordance with the second AC voltage in the even frame period. The method of claim 7,
Wherein the node control unit is responsive to at least one preceding carry signal provided from at least one of the previous single stages and at least one subsequent carry signal provided from at least one of the following single stages, And controlling the discharge of the gate shift register.

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