KR20150102526A - Electronic device - Google Patents

Abstract

In an electronic device including a semiconductor memory, the semiconductor memory includes: a storage cell including a variable resistive element; A first selection device coupled to one end of the storage cell, the first selection device having a threshold voltage of a first voltage; And a second selection device coupled to the other end of the storage cell, the second selection device having a threshold voltage greater than the first voltage.

Description

ELECTRONIC DEVICE

This patent document relates to memory circuits or devices and their applications in electronic devices.

Recently, semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices have been demanded for miniaturization, low power consumption, high performance, and diversification of electronic devices, and studies are underway. For example, a semiconductor device such as a Resistive Random Access Memory (RRAM), a Phase-change Random Access Memory (PRAM), or the like can be used as the semiconductor device, , Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), and E-fuse.

The problem to be solved by the embodiments of the present invention is to provide an electronic device in which leakage current is reduced by increasing the margin by reducing the total resistance of the path through which the lead current flows, by varying the threshold voltage of the selection element at both ends of the storage cell.

According to an aspect of the present invention, there is provided an electronic device including a semiconductor memory, including: a storage cell including a variable resistive element; A first selection device coupled to one end of the storage cell, the first selection device having a threshold voltage of a first voltage; And a second selection device coupled to the other end of the storage cell, the second selection device having a threshold voltage greater than the first voltage.

The storage cell comprising: the variable resistive element; And a selection element connected to one end of the variable resistive element and turned on / off in response to a voltage of the word line.

The electronic device may flow a current from the first selecting device to the second selecting device during a read operation.

The variable resistive element may have a first state having a first resistance value or a second state having a second resistance value higher than the first resistance value.

Wherein the variable resistance element is switched to the first state when a first switching current flows from the other end to the one end and switches to the second state when a second switching current larger than the first switching current flows from the one end to the other end, .

The first selection element and the second selection element may be turned on / off in response to a selection signal.

The first selection device may be fabricated such that the threshold voltage is the first voltage, and the second selection device may be fabricated such that the threshold voltage is the second voltage.

The spacing of the gates of the at least one second selection element may be greater than the spacing of the gates of the at least one first selection element.

The doping concentration of the active region of the second selection device may be made higher than the doping concentration of the active region of the first selection device.

The width of the gate of at least one of the second selection elements may be made wider than the width of the gate of the first selection element.

The distance between the contact and the gate connected to the active region of the second selection device may be greater than the distance between the contact and the gate connected to the active region of the first selection device.

The first selection device may be supplied with a back bias voltage such that the threshold voltage is the first voltage, and the second selection device may be applied with a back bias voltage such that the threshold voltage is the second voltage.

The variable resistive element may include at least one of a metal oxide, a phase change material, and a structure in which a tunnel barrier layer is interposed between two magnetic layers.

The electronic device further includes a microprocessor, wherein the microprocessor includes: a control unit that receives a signal including an instruction from outside the microprocessor, and performs extraction or decoding of the instruction or input / output control of a signal of the microprocessor; An operation unit for performing an operation according to a result of decoding the instruction by the control unit; And a storage unit that stores data for performing the operation, data corresponding to a result of performing the operation, or address of data for performing the operation, wherein the semiconductor memory is a part of the storage unit have.

The electronic device further comprising a processor, the processor comprising: a core unit for performing an operation corresponding to the instruction using data in accordance with an instruction input from the outside of the processor; A cache memory unit for storing data for performing the operation, data corresponding to a result of performing the operation, or an address of data for performing the operation; And a bus interface connected between the core portion and the cache memory portion and transferring data between the core portion and the cache memory portion, wherein the semiconductor memory may be part of the cache memory portion within the processor .

The electronic device further comprising a processing system, the processing system comprising: a processor for interpreting a received command and controlling an operation of information according to a result of interpreting the command; A program for interpreting the command and an auxiliary memory for storing the information; A main memory for moving and storing the program and the information from the auxiliary memory so that the processor can perform the calculation using the program and the information when the program is executed; And an interface device for performing communication with at least one of the processor, the auxiliary memory device, and the main memory device, and the semiconductor memory is a part of the auxiliary memory device or the main memory device in the processing system .

The electronic device further includes a data storage system, wherein the data storage system stores data and stores the stored data regardless of the power supplied; A controller for controlling data input / output of the storage device according to an instruction input from the outside; A temporary storage device for temporarily storing data exchanged between the storage device and the outside; And an interface for performing communication with the exterior with at least one of the storage device, the controller, and the temporary storage device, wherein the semiconductor memory is a part of the storage device or the temporary storage device .

The electronic device further includes a memory system, wherein the memory system stores data and maintains stored data regardless of the power supplied; A memory controller for controlling data input / output of the memory in response to a command input from the outside; A buffer memory for buffering data exchanged between the memory and the outside; And an interface for externally communicating with at least one of the memory, the memory controller and the buffer memory, wherein the semiconductor memory may be part of the memory or the buffer memory within the memory system.

According to an aspect of the present invention, there is provided an electronic device including a semiconductor memory, the semiconductor memory including: a first global line; A second global line; One or more cell arrays including a plurality of storage cells including variable resistance elements, a first local line connected to one end of the plurality of storage cells, and a second local line connected to the other end of the plurality of storage cells; At least one first selection element coupled between the first global line and a first local line of a corresponding cell array, the first selection element having a threshold voltage of a first voltage; And a second selection element coupled between the second global line and a second local line of a corresponding cell array and having a threshold voltage greater than the first voltage.

The storage cell comprising: the variable resistive element; And a selection element connected to one end of the variable resistive element and turned on / off in response to a voltage of a corresponding one of the plurality of word lines.

The electronic device may flow current from the first global line to the second global line via a storage cell selected during a read operation.

The variable resistive element may have a first state having a first resistance value or a second state having a second resistance value higher than the first resistance value.

Wherein the variable resistance element is switched to the first state when a first switching current flows from the other end to the one end and switches to the second state when a second switching current larger than the first switching current flows from the one end to the other end, .

The at least one first selection element and the at least one second selection element may be turned on / off in response to a corresponding one of the one or more selection signals.

The first selection device may be fabricated such that the threshold voltage is the first voltage, and the second selection device may be fabricated such that the threshold voltage is the second voltage.

The first selection device may be supplied with a back bias voltage such that the threshold voltage is the first voltage, and the second selection device may be applied with a back bias voltage such that the threshold voltage is the second voltage.

The variable resistive element may include at least one of a metal oxide, a phase change material, and a structure in which a tunnel barrier layer is interposed between two magnetic layers.

The electronic device further includes a microprocessor, wherein the microprocessor includes: a control unit that receives a signal including an instruction from outside the microprocessor, and performs extraction or decoding of the instruction or input / output control of a signal of the microprocessor; An operation unit for performing an operation according to a result of decoding the instruction by the control unit; And a storage unit that stores data for performing the operation, data corresponding to a result of performing the operation, or address of data for performing the operation, wherein the semiconductor memory is a part of the storage unit have.

The electronic device further comprising a processor, the processor comprising: a core unit for performing an operation corresponding to the instruction using data in accordance with an instruction input from the outside of the processor; A cache memory unit for storing data for performing the operation, data corresponding to a result of performing the operation, or an address of data for performing the operation; And a bus interface connected between the core portion and the cache memory portion and transferring data between the core portion and the cache memory portion, wherein the semiconductor memory may be part of the cache memory portion within the processor .

The electronic device further comprising a processing system, the processing system comprising: a processor for interpreting a received command and controlling an operation of information according to a result of interpreting the command; A program for interpreting the command and an auxiliary memory for storing the information; A main memory for moving and storing the program and the information from the auxiliary memory so that the processor can perform the calculation using the program and the information when the program is executed; And an interface device for performing communication with at least one of the processor, the auxiliary memory device, and the main memory device, and the semiconductor memory is a part of the auxiliary memory device or the main memory device in the processing system .

The electronic device further includes a data storage system, wherein the data storage system stores data and stores the stored data regardless of the power supplied; A controller for controlling data input / output of the storage device according to an instruction input from the outside; A temporary storage device for temporarily storing data exchanged between the storage device and the outside; And an interface for performing communication with the exterior with at least one of the storage device, the controller, and the temporary storage device, wherein the semiconductor memory is a part of the storage device or the temporary storage device .

The electronic device further includes a memory system, wherein the memory system stores data and maintains stored data regardless of the power supplied; A memory controller for controlling data input / output of the memory in response to a command input from the outside; A buffer memory for buffering data exchanged between the memory and the outside; And an interface for externally communicating with at least one of the memory, the memory controller and the buffer memory, wherein the semiconductor memory may be part of the memory or the buffer memory within the memory system.

Since the threshold voltages of the selection elements connected to both ends of the storage cell are different from each other, the total resistance of the path through which the read / write current flows can be reduced to increase the margin and reduce the leakage current, Speed, accuracy and reduce current consumption.

FIG. 1 shows an embodiment of a magnetic tunnel junction (MTJ) structure, which is one of structures in which a tunnel barrier layer is interposed between two magnetic layers,
2A and 2B are diagrams for explaining the principle of storing data for the variable resistive element 210,
3 is an example of a configuration diagram of a memory circuit (device) including a storage cell 310 including a variable resistive element 311,
Figures 4A, 4B, and 4C illustrate a portion of the electronic device of Figure 3 to illustrate the effects of the memory of Figure 3;
5 shows an example of a configuration diagram of a memory circuit (device) including a storage cell SC including a variable resistive element R,
6 is an example of a cross-sectional view of a transistor having a buried gate,
7 is an example of a cross-sectional view of a transistor,
8 is a block diagram of a microprocessor embodying a memory device according to an embodiment of the present invention.
Figure 9 is an example of a configuration diagram of a processor that implements a memory device in one embodiment of the present invention,
10 is an example of a configuration diagram of a system for implementing a memory device according to an embodiment of the present invention,
11 is an example of a configuration diagram of a data storage system implementing a memory device according to an embodiment of the present invention;
12 is an example of a configuration diagram of a memory system that implements a memory device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

The semiconductor device according to embodiments of the present invention may include a variable resistive element. Hereinafter, the variable resistance element exhibits a variable resistance characteristic and may include a single film or a multi-film. For example, the variable resistance element may include a material used for RRAM, PRAM, MRAM, FRAM and the like, for example, a chalcogenide-based compound, a transition metal compound, a ferroelectric, a ferromagnetic material and the like. However, the present invention is not limited thereto, and it is only necessary that the variable resistance element has a variable resistance characteristic to switch between different resistance states depending on the voltage or current applied to both ends thereof.

More specifically, the variable resistance element may include a metal oxide. Examples of the metal oxide include oxides of transition metals such as nickel (Ni) oxide, titanium (Ti) oxide, hafnium (Hf) oxide, zirconium (Zq) oxide, tungsten (W) oxide, cobalt ), PCMO (PrCaMnO), and the like. Such a variable resistive element can exhibit a characteristic of switching between different resistance states due to the generation / disappearance of current filaments due to the vacancy behavior.

In addition, the variable resistive element may include a phase change material. The phase change material may be, for example, a chalcogenide-based material such as GST (Ge-Sb-Te) or the like. Such a variable resistance element can exhibit a characteristic of switching between different resistance states by being stabilized in either a crystalline state or an amorphous state by heat.

Further, the variable resistance element may include a structure in which a tunnel barrier layer is interposed between two magnetic layers. The magnetic layer may be formed of a material such as NiFeCo or CoFe, and the tunnel barrier layer may be formed of a material such as Al2O3. Such a variable resistance element can exhibit a characteristic of switching between different resistance states depending on the magnetization direction of the magnetic layer. For example, the variable resistance element may be in a low resistance state when the magnetization directions of the two magnetic layers are parallel, and may be in a high resistance state when the magnetization directions of the two magnetic layers are antiparallel.

1 is an embodiment of a magnetic tunnel junction (MTJ), which is one of structures in which a tunnel barrier layer is interposed between two magnetic layers.

The magnetic tunnel junction element 100 includes a first electrode layer 110 as an upper electrode, a second electrode layer 120 as a lower electrode, a first magnetic layer 112 as a pair of magnetic layers and a second magnetic layer 122 And a tunnel barrier layer 130 formed between the pair of magnetic layers 112 and 122.

Here, the first magnetic layer 112 is a free ferromagnetic layer whose magnetization direction is variable according to the direction of the current applied to the magnetic tunnel junction element 100, and the second magnetic layer 122 has a fixed magnetization direction (Pinned ferromagnetic layer).

This magnetic tunnel junction element 100 changes its resistance value in accordance with the direction of the current to record data "0" or "1 ".

FIGS. 2A and 2B are diagrams for explaining the principle of storing data for the variable resistive element 210. FIG. Here, the variable resistive element 210 may be the magnetic tunnel junction element 100 described in the description of FIG.

2A is a diagram for explaining the principle of writing data having a logical value of 'low' to the variable resistive element 210. FIG. The word line 230 connected to the variable resistive element 210 is activated to turn on the transistor 220 in order to select the variable resistive element 210 in which data is to be stored. When a current flows from the first end 251 to the second end 252, that is, from the first electrode layer 110, which is the upper electrode of the magnetic tunnel junction element 100 to the second electrode layer 120, which is the lower electrode The direction of the first magnetic layer 110 which is a free magnetic layer and the magnetization direction of the second magnetic layer 122 which is a fixed magnetic layer are parallel to each other so that the variable resistance element 210 becomes a low resistance state, Data is stored in the variable resistance element 210 when the resistance element 210 is in a low resistance state.

Meanwhile, FIG. 2B is a diagram for explaining the principle of writing data having a logic high value to the variable resistive element 210. FIG. Likewise, the word line 230 connected to the variable resistive element 210 is activated and the transistor 220 is turned on. When a current flows from the other end 252 to the first electrode layer 110 from the second electrode layer 120 (arrow direction), the direction of the first magnetic layer 112 and the direction of the second magnetic layer The variable resistance element 210 has a high resistance state while the magnetization directions of the variable resistive elements 210 and 122 are anti-parallel to each other, and when the variable resistance element 210 is in a high resistance state, High data is defined as being stored.

3 is an example of a configuration diagram of a memory circuit (device) including a storage cell 310 including a variable resistive element 311. In Fig.

3, the memory includes a storage cell 310, a first select device 320, a second select device 330, an access controller 340, a word line WL, a first line LINE1, A second line LINE2, and a reference resistance element REF_R.

The storage cell 310 may include a variable resistive element 311 and a selection element 312. The variable resistive element 311 is switched in response to the switching currents flowing at both ends, and can have a resistance value corresponding to each state. In more detail, the variable resistive element 311 may have a first state having a first resistance value or a second state having a second resistance value higher than the first resistance value. The variable resistive element 311 is switched to the first state when the first switching current SW_I1 flows from the other end B to the one end A and the first switching current SW_I1 is switched from the first end A to the second end B, Can be switched to the second state when a larger second switching current (SW_I2) flows.

The first state may correspond to the above-described high resistance state, and the second state corresponding to the above-described low resistance state. The first state of the variable resistive element 311 may be defined as a state in which row data is stored and the second state may be defined as a state in which high data is stored. Alternatively, the first state of the variable resistive element 311 may be defined as a state in which high data is stored, and the second state may be defined as a state in which row data is stored. Hereinafter, the former case will be described as an example.

The selection element 312 is connected to the word line WL and can be controlled in response to the voltage of the word line WL. The selection device 312 is turned on in response to the voltage of the word line WL when the word line WL is active and is turned on when the word line WL is precharged And can be turned off in response.

A first selection device 320 and a second selection device 330 may be connected to both ends of the storage cell 310, respectively. The storage cell 310 may be connected to the first line LINE1 through the first selection device 320 and may be connected to the second line LINE2 through the second selection device 330. [ The first line LINE 1 and the second line LINE 2 may be connected to the access control unit 340. The first select element 320 and the second select element 330 may be turned on when the select signal LYSW is activated and may be turned off when the select signal LYSW is inactivated. Here, the threshold voltage of the first selection device 320 may be a first voltage and the second selection device 330 may be a second voltage whose threshold voltage is greater than the first voltage. That is, the first and second selectors 320 and 330 may have different levels of threshold voltage.

The first select element 320 and the second select element 330 may be fabricated to have different levels of threshold voltage. The first selection device 320 may be fabricated such that the threshold voltage is the first voltage and the second selection device is the second voltage whose threshold voltage is greater than the first voltage.

For example, when the first selection device 320 and the second selection device 330 are MOS transistors, the gate width of the transistor may be adjusted, the doping concentration of the drain or the source may be adjusted The first selection device 330 and the second selection device 330 may be formed by a method of diffusing an element doped to a drain or a source, a doping concentration of a substrate on which the transistor is formed, 330 can be adjusted. In addition, the threshold voltages of the first and second selection elements 320 and 330 can be adjusted in various ways in the manufacturing process. Even if the first selection element 320 and the second selection element 330 are other than MOS transistors, they can be manufactured to have different threshold voltages from the beginning by various methods in the manufacturing process.

 Or the voltage of the back bias voltages VBB1 and VBB2 so that the threshold voltage becomes the first voltage and the second selection device 330 becomes the second voltage whose threshold voltage is larger than the first voltage, Can be adjusted.

For example, when the first selection device 320 and the second selection device 330 are NMOS transistors, the first back bias voltage VBB1 applied to the bulk of the first selection device 320 is set to the second The second back bias voltage VBB2 applied to the bulk of the selection element 330 can be set lower than the second back bias voltage VBB2 applied to the bulk of the selection element 330. [ In this case, if the first select element 320 and the second select element 330 are fabricated in the same way (if the threshold voltages are the same), the threshold voltage of the second select element 330 is the same as the threshold voltage of the first select element 320 Can be set higher than the threshold voltage. Even if the first selection element 320 and the second selection element 330 are other than NMOS transistors, they can be set to have different threshold voltages by using various methods after they are manufactured.

The reference resistance element REF_R has a resistance value between the first resistance value and the second resistance value and is connected to the connection element RT which is turned on / off in response to the read enable signal RDEN activated in the read operation And may be connected to the access control unit 340.

The access control unit 340 can pass a switching current to the storage cell 310 in a direction determined by the data W_DATA to be written when the write signal WT is activated. For example, when the row data is written, the access control unit 340 controls the first and second lines LINE1 and LINE2 so that the first switching current SW_I1 flows from the second line LINE2 to the first line LINE1 through the selected storage cell 340, A high voltage can be applied to the first line LINE2 and a low voltage can be applied to the first line LINE1. The access controller 340 controls the first line LINE1 so that the second switching current SW_I2 flows from the first line LINE1 to the second line LINE2 through the selected storage cell 340 when writing high data, And a low voltage can be applied to the second line LINE2.

The access control unit 340 compares the resistance value of the variable resistive element 311 of the storage cell 310 with the resistance value of the reference resistance element REF_R when the read signal RD is activated, Data can be read and output (R_DATA). For example, when the first state stores the row data and the second state stores the high data, the access controller 340 determines whether the resistance value of the variable resistor element 311 is greater than the resistance value of the reference resistor element (R_DATA) when the resistance value of the variable resistive element 311 is smaller than the resistance value of the reference resistance element REF_R and outputs (R_DATA) high data when the resistance value of the variable resistive element 311 is larger than the resistance value of the reference resistance element REF_R.

To this end, when the read signal RD is activated, the access controller 340 applies a high voltage to the first line LINE1 and a low voltage to the second line LINE2 during the read operation, 310 to the second line LINE2 from the first line LINE1 and to flow the reference current REF_I through the reference resistance element REF_R.

In general, when the transistor is turned off, the leakage current flowing through the transistor may cause a malfunction of the memory or increase the consumption current and power consumption of the memory. Thus, by reducing the leakage current by increasing the threshold voltage of the transistor, the accuracy and reliability of the memory can be increased, and the consumption current and power consumption can be reduced. On the other hand, increasing the threshold voltage of the transistor increases the equivalent resistance value of the transistor. The data stored in the storage cell 310 in the memory is determined by the resistance value of the variable resistive element 311 of the storage cell 310. Therefore, in order to increase the read margin, in the path RD_PATH in which the read current RD_I flows The resistance other than the variable resistive element 311 must be reduced as much as possible. Therefore, if the threshold voltages of the first and second selection elements 320 and 330 are both increased to reduce the leakage current, the memory lead margin is reduced.

The memory of FIG. 3 is different from the first embodiment in that the threshold voltage of the first selection device 320 and the second selection device 330 are different from each other but only the threshold voltage of the second selection device 330 is increased to maximize the lead margin, Can be reduced. Since the leakage current flows through the first selection device 320 and the second selection device 330, the threshold voltages of the two selection devices 320 and 330 are increased even if only the threshold voltage of the second selection device 330 is increased Similar effects can be generated. Hereinafter, the effect of the memory of FIG. 3 will be described in detail with reference to FIG.

4A, 4B, and 4C are diagrams illustrating portions of the electronic device of FIG. 3 to illustrate the effect of the memory of FIG.

4A, 4B and 4C, only the storage cell 310, the first selection device 320 and the second selection device 330 of the memory of FIG. 3 are shown. Hereinafter, the case where the selectors 320 and 330 are turned off (FIG. 4A), the case where the read operation is performed (FIG. 4B) and the case where the write operation is performed (FIG. The relationship between the threshold voltage of the variable resistance element 320 and the current flowing through the variable resistance element will be described.

In the following, V _LYSW denotes the voltage of the activated selection signal LYSW, V _WL denotes the voltage of the activated word line WL, V _T1 denotes the threshold voltage of the first selection element 320, V _T2 May represent the threshold voltage of the second select element 330. [

4A, when the first selection element 320 and the second selection element 330 are turned off, the first selection element 320, the variable resistance element 311, the selection element 312, 2 The amount of current flowing in the selection element 330 can be determined by the smallest amount of current flowing among the four elements (four elements are connected in series). Therefore, the amount of leakage current (LK_I) can be reduced by increasing the threshold voltage of the second select element (330). That is, even if only the threshold voltage of the second selection device 330 of the first selection device 320 and the second selection device 330 is increased, the leakage current can be effectively blocked.

4B, when the memory performs the read operation, the first read voltage V _R1 is applied to the drain D1 of the first select element 320 and the source of the second select element 330 The second read voltage V _R2 may be applied to the second switch S2. The may be a first read voltage (V _R1) is a level higher than the second read voltage (V _R2), a second read voltage (V _R2) is a ground voltage (VSS) or a ground voltage (GND). Let the voltage of the source S1 of the first selector 320 be V _S1 and the voltage of the drain D2 of the second selector 330 be V _D2 .

When the word line WL is activated, the selection element 312 is turned on and when the selection signal LYSW is activated, the first selection element 320 and the second selection element 330 are turned on and the first selection element 320 is turned on, The read current RD_I flows from the drain D1 of the second selection element 330 to the source S2 of the second selection element 330. [

In the case of an NMOS transistor, the amount of current (I _D ) flowing through both ends can satisfy the relationship (V _GS - V _T ) ² ? I _D. Where V _GS represents the difference between the voltage at the gate of the transistor and the source voltage, and V _T may represent the threshold voltage. 4, since the read current RD_I flows from the source S1 of the first selection element 320 to the source S2 of the second selection element and a voltage drop occurs, V _S1 > V _S2 , and therefore V _LYSW - V _S1 (V _GS of first select element 320) <V _LYSW - V _S2 (V _GS of the second selection element 330). When the threshold voltage V _T2 of the second selection element 330 having a large value of V _GS is increased to the extent that the amount of the read current RD_I is reduced or the resistance of the variable resistor element 311 ) Can be minimized and the lead margin can be maintained. It is possible to maximize the lead margin while reducing the leakage current by raising the threshold voltage of the selection element to which a low voltage is applied among the read voltages V _R1 and V _R2 .

4C, if the data W_DATA to be written is the row data (CASE1, the variable resistance element 311 is switched to the first state) when the memory performs the write operation, If the data W_DATA to be written is a high data (CASE2, the variable resistance element 311 is switched to the second state) by flowing a first switching current SW_I1 from the first selection element 320 to the first selection element 320, The second switching current SW_I2 may flow from the first switching element 320 to the second selection element 330. [ The amount of current of the second switching current SW_I2 may be larger than the amount of the first switching current SW_I1. As described above in the description of FIG. 4B, it is advantageous to increase the threshold voltage of a selection element to which a relatively low voltage is applied (to reduce the equivalent resistance) to flow a high current. Therefore, in consideration of the second switching current SW_I2 having a large amount of the switching currents SW_I1 and SW_I2, the second selection element 330 having a high threshold voltage when flowing the second switching current SW_I2, When a voltage lower than that of the device 320 is applied, the efficiency of the write operation can be increased.

5 is an example of a configuration diagram of a memory circuit (apparatus) including a storage cell SC including the variable resistive element R.

5, the memory may include one or more cell arrays CA1 - CAN, a first global line GL1, a second global line GL2, one or more first selectors ST1_1 - ST1_N, A plurality of word lines WL1 to WLM, a reference resistive element REF_R, a word line controller 510, and an access controller 520. The second selectors ST2_1 to ST2_N may include a plurality of word lines WL1 to WLM.

The one or more cell arrays CA1 to CAN may each include a plurality of storage cells SC, a first local line L1_1 to L1_N and a second local line L2_1 to L2_N. The storage cell SC may include a variable resistance element R and a selection element S. [ The variable resistive element R is switched in response to a switching current flowing at both ends, and can have a resistance value corresponding to each state. In more detail, the variable resistive element R may have a first state having a first resistance value or a second state having a second resistance value higher than the first resistance value. The variable resistive element R may be switched to the first state when the first switching current SW_I1 is supplied and switched to the second state when the second switching current SW_I2 is greater than the first switching current SW_I1.

The first state may correspond to the above-described high resistance state, and the second state corresponding to the above-described low resistance state. The first state of the variable resistive element R may be defined as a state in which row data is stored and the second state may be defined as a state in which high data is stored. Alternatively, the first state of the variable resistive element R may be defined as a state in which high data is stored, and the second state may be defined as a state in which row data is stored. Hereinafter, the former case will be described as an example.

The selection elements S of each storage cell SC are connected to the corresponding word lines WL1 to WLM and are turned on when the corresponding word lines WL1 to WLM are activated and the corresponding word lines WL1 to WLM ) Is precharged (deactivated). The corresponding first local lines L1_1 to L1_N may be connected to one end of each storage cell SC and the second local lines L2_1 to L2_N may be connected to the other end thereof.

Each of the first local lines L1_1 to L1_N is connected to the first global line GL1 through the corresponding first selectors ST1_1 to ST1_N and each of the second local lines L2_1 to L2_N is connected to the corresponding second And can be connected to the second global line GL2 through the selection devices ST2_1 to ST2_N. Each of the first selectors ST1_1 to ST1_N and the second selectors ST2_1 to ST2_N may be turned on when a corresponding one of the one or more select signals LYSW <1: N> is activated.

The first selectors ST1_1 to ST1_N and the second selectors ST2_1 to ST2_N may be set to have different threshold voltages. 3, the threshold voltages of the first selectors ST1_1-ST1_N and the second selectors ST2_1-ST2_N may be differently manufactured during the process or may be adjusted by adjusting the back bias voltages VBB1 and VBB2 Can be set differently. The threshold voltages of the first selectors ST1_1 to ST1_N may be a first voltage and the threshold voltages of the second selectors ST2_1 to ST2_N may be a second voltage higher than the first voltage.

The word line control unit 510 may activate the selected one of the plurality of word lines WL1 to WLM in response to the word line selection information SEL_WL <0: A>. The word line control unit 510 may apply a voltage to the selected word line to turn on the selection elements S connected to the selected word line.

The reference resistance element REF_R has a resistance value between the first resistance value and the second resistance value and is connected to the connection element RT which is turned on / off in response to the read enable signal RDEN activated in the read operation And may be connected to the access control unit 520.

The access control unit 520 can pass the switching current to the storage cell SC selected in the direction determined by the data W_DATA to be written when the write signal WT is activated. For example, when the row data is written, the access control unit 520 controls the first and second global lines GL1 and GL2 so that the first switching current SW_I1 flows from the second global line GL2 to the first global line GL1 through the selected storage cell SC. 2 can apply a high voltage to the global line GL2 and a low voltage to the first global line GL1. The access control unit 520 controls the first global line GL1 so that the second switching current SW_I2 flows from the first global line GL1 to the second global line GL2 through the selected storage cell SC, It is possible to apply a high voltage to the first global line GL1 and a low voltage to the second global line GL2.

The access control unit 520 compares the resistance value of the variable resistive element R of the selected storage cell SC with the resistance value of the reference resistance element REF_R when the read signal RD is activated, And can output (R_DATA) the read data. For example, when the first state stores the row data and the second state stores the high data, the access control unit 520 determines whether the variable resistance element R of the selected storage cell SC When the resistance value is smaller than the resistance value of the reference resistance element REF_R, the row data is output (R_DATA), and the resistance value of the variable resistance element R of the selected storage cell SC becomes the resistance value of the reference resistance element REF_R High data can be output (R_DATA).

To this end, the access control unit 520 applies a high voltage to the first global line GL1 and a low voltage to the second global line GL2 when the read signal RD is activated, The read current RD_I can flow from the line GL1 to the second global line GL2 and the reference current REF_I can flow through the reference resistance element REF_R.

The read / write operation for the selected storage cell SC may be the same as the read / write operation for the storage cell 310 of FIG. The first global line GL1 and the second global line GL2 of FIG. 5 may correspond to the first line LINE1 and the second line LINE2 of FIG. 3, respectively. In the case of unselected cell arrays, since the second selectors ST2_1 to ST2_N have high threshold voltages, the leakage current can be effectively blocked. In addition, the threshold voltage of the second selection elements ST2_1 to ST2_N connected to the second global line GL2 driven at a lower voltage in the read / write operation is increased to minimize the reduction of the lead margin, Lt; / RTI &gt;

FIGS. 6 and 7 are diagrams for explaining a method of manufacturing a threshold voltage of a selection element differently when the first selection element 320 and the second selection element 330 are MOS transistors.

6 is an example of a cross-sectional view of a transistor having a buried gate.

6 shows a cross-sectional view of two transistors having buried gates 610A and 610B sharing an active region 640B. As shown in FIG. 6, the transistors T1 and T2 may share the active region 640B. Gate insulating films 620A and 620B may be formed around the gates 610A and 610B and gate protective films 630A and 630B may be formed on the gates 610A and 610B. Each of the transistors T1 and T2 may be formed on the substrate 600. [

First, the threshold voltages of the transistors T1 and T2 may vary according to the distance D1 between the gates 610A and 620B. More specifically, the threshold voltages of the transistors T1 and T2 become higher as the distance D1 between the gates 610A and 620B becomes narrower and lower as the distance D1 between the gates 610A and 620B becomes wider have.

Therefore, when the transistors T1 and T2 are the first selection device 320, 'D1' is relatively wider and when the transistors T1 and T2 are the second selection device 330, 'D1' is relatively narrow So that the threshold voltage of the second selection device 330 can be made higher than the threshold voltage of the first selection device 320.

Next, the threshold voltages of the transistors T1 and T2 may be varied depending on the doping concentration of the active regions 640A, 640B, and 640C. More specifically, the threshold voltages of the transistors T1 and T2 decrease as the doping concentration of the active regions 640A, 640B, and 640C increases, and may increase as the doping concentrations of the active regions 640A, 640B, and 640C decrease .

The doping concentration of the active regions 640A, 640B and 640C is relatively increased when the transistors T1 and T2 are the first selection element 320 and the doping concentration of the active regions 640A, 640B and 640C is relatively increased when the transistors T1 and T2 are the second selection element 330 The doping concentration of the active regions 640A, 640B, and 640C may be relatively lowered so that the threshold voltage of the second selection device 330 may be higher than the threshold voltage of the first selection device 320. [

Finally, the threshold voltages of the transistors T1 and T2 may vary depending on the widths W1 and W2 of the gates 610A and 620B. More specifically, the threshold voltages of the transistors T1 and T2 increase as the widths W1 and W2 of the gates 610A and 620B increase, and as the widths W1 and W2 of the gates 610A and 620B decrease, Can be lowered.

Therefore, 'W1' and 'W2' are fabricated relatively narrow when the transistors T1 and T2 are the first selection device 320 and 'W1' and 'W2' when the transistors T1 and T2 are the second selection device 330, And 'W2' may be relatively wider so that the threshold voltage of the second selection device 330 may be higher than the threshold voltage of the first selection device 320. [

7 is an example of a cross-sectional view of a transistor.

FIG. 7 shows a cross-sectional view of one transistor having a general gate 710. FIG. As shown in FIG. 6, a transistor may be formed on the substrate 700. A gate insulating film 730 is formed under the gate 710 and each of the active regions 720A and 720B can be connected to other structures (not shown in FIG. 7) through the corresponding contacts 740A and 740B have.

The threshold voltage of the transistor may vary depending on the distance D1, D2 between the gate 710 and the contacts 740A, 740B. The threshold voltage of the transistor increases as the distance D1 and D2 between the gate 710 and the contacts 740A and 740B increases and the distance D1 and D2 between the gate 710 and the contacts 740A and 740B ) Can be lowered.

D1 'and' D2 'are relatively short when the transistors T1 and T2 are the first selection device 320 and' D1 'and' D1 'when the transistors T1 and T2 are the second selection device 330. Therefore, And 'D2' may be relatively long, so that the threshold voltage of the second selection device 330 can be made higher than the threshold voltage of the first selection device 320.

The memory circuit or semiconductor device of the above embodiments may be used in various devices or systems. Figures 8-12 illustrate some examples of devices or systems capable of implementing a memory circuit or a semiconductor device of the embodiments described above.

8 is a block diagram of a microprocessor for implementing a memory device according to an embodiment of the present invention.

Referring to FIG. 8, the microprocessor 1000 can control and adjust a series of processes of receiving data from various external devices, processing the data, and transmitting the result to an external device. The storage unit 1010, An operation unit 1020, a control unit 1030, and the like. The microprocessor 1000 may be any of a variety of devices such as a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP), an application processor Data processing apparatus.

The storage unit 1010 may be a processor register, a register or the like and may store data in the microprocessor 1000 and may include a data register, an address register, a floating point register, And may include various registers. The storage unit 1010 may temporarily store data for performing operations in the operation unit 1020, addresses for storing execution result data, and data for execution.

The storage unit 1010 may include one or more of the above-described embodiments of the memory device. For example, the storage unit 1010 may include a storage cell including a variable resistive element; A first selection device coupled to one end of the storage cell, the first selection device having a threshold voltage of a first voltage; And a second selection device coupled to the other end of the storage cell, the second selection device having a threshold voltage greater than the first voltage. Thus, the consumption current and the consumption power of the storage unit 1010 can be reduced by increasing the read / write margin of the storage unit 1010 and reducing the leakage current generated in the storage unit 1010. As a result, it is possible to improve the operation speed and stability of the microprocessor 1000 and to reduce the consumed current and power consumption.

The operation unit 1020 can perform various arithmetic operations or logical operations according to the result of decoding the instruction by the control unit 1030. [ The operation unit 1020 may include one or more arithmetic and logic units (ALUs) and the like.

The control unit 1030 receives a signal from a storage unit 1010, an operation unit 1020 and an external device of the microprocessor 1000 and performs extraction and decoding of the instruction and control of signal input / output of the microprocessor 1000 , And can execute the processing represented by the program.

The microprocessor 1000 according to the present embodiment may further include a cache memory unit 1040 that can input data input from an external device or temporarily store data to be output to an external device. In this case, the cache memory unit 1040 can exchange data with the storage unit 1010, the operation unit 1020, and the control unit 1030 through the bus interface 1050.

9 is an example of a configuration diagram of a processor that implements a memory device in an embodiment of the present invention.

9, the processor 1100 includes various functions in addition to the functions of a microprocessor for controlling and adjusting a series of processes of receiving and processing data from various external devices and then transmitting the result to an external device Performance, and versatility. The processor 1100 includes a core unit 1110 serving as a microprocessor, a cache memory unit 1120 serving to temporarily store data, and a bus interface 1430 for transferring data between the internal and external devices . The processor 1100 may include various system on chips (SoCs) such as a multi core processor, a graphics processing unit (GPU), an application processor (AP) have.

The core unit 1110 of the present embodiment is a part for performing arithmetic logic operations on data input from an external apparatus and may include a storage unit 1111, an operation unit 1112, and a control unit 1113. [

The storage unit 1111 may be a processor register, a register or the like and may store data in the processor 1100 and may include a data register, an address register, a floating point register, It may contain various registers. The storage unit 1111 may temporarily store an address in which data for performing an operation, execution result data, and data for execution in the operation unit 1112 are stored. The arithmetic operation unit 1112 performs arithmetic operations in the processor 1100. The arithmetic operation unit 1112 can perform various arithmetic operations and logical operations according to the result of decoding the instructions by the control unit 1113. [ The operation unit 1112 may include one or more arithmetic and logic units (ALUs) and the like. The control unit 1113 receives signals from a storage unit 1111, an operation unit 1112, an external device of the processor 1100, etc., extracts or decodes a command, controls signal input / output by the processor 1100, The processing represented by the program can be executed.

The cache memory unit 1120 temporarily stores data to compensate for a difference in data processing speed between the core unit 1110 operating at a high speed and an external device operating at a low speed. The cache memory unit 1120 includes a primary storage unit 1121, A secondary storage unit 1122, and a tertiary storage unit 1123. In general, the cache memory unit 1120 includes a primary storage unit 1121 and a secondary storage unit 1122, and may include a tertiary storage unit 1123 when a high capacity is required. have. That is, the number of storage units included in the cache memory unit 1120 may vary depending on the design. Here, the processing speeds for storing and discriminating data in the primary, secondary, and tertiary storage units 1121, 1122, and 1123 may be the same or different. If the processing speed of each storage unit is different, the speed of the primary storage unit may be the fastest. One or more of the primary storage unit 1121, the secondary storage unit 1122 and the tertiary storage unit 1123 of the cache memory unit 1120 may include one or more of the embodiments of the above- have. For example, the cache memory unit 1120 may include a storage cell including a variable resistive element; A first selection device coupled to one end of the storage cell, the first selection device having a threshold voltage of a first voltage; And a second selection device coupled to the other end of the storage cell, the second selection device having a threshold voltage greater than the first voltage. The read current and the power consumption of the cache memory unit 1120 can be reduced by increasing the read / write margin of the cache memory unit 1120 and reducing the leakage current generated in the cache memory unit 1120. As a result, the operating speed and stability of the processor 1100 can be improved, and the consumed current and power consumption can be reduced.

9 shows the case where the primary, secondary, and tertiary storage units 1121, 1122, and 1123 are all configured in the cache memory unit 1120. However, the primary, secondary, and tertiary storage units 1121, The tertiary storage units 1121, 1122, and 1123 are all formed outside the core unit 1110 to compensate for the difference in processing speed between the core unit 1110 and the external apparatus. Alternatively, the primary storage unit 1121 of the cache memory unit 1120 may be located inside the core unit 1110, and the secondary storage unit 1122 and the tertiary storage unit 1123 may be located inside the core unit 1110 So that the function of compensating the processing speed difference can be further strengthened. Alternatively, the primary and secondary storage units 1121 and 1122 may be located inside the core unit 1110, and the tertiary storage unit 1123 may be located outside the core unit 1110.

The bus interface 1430 connects the core unit 1110, the cache memory unit 1120, and an external device, thereby enabling efficient transmission of data.

The processor 1100 according to the present embodiment may include a plurality of core units 1110 and a plurality of core units 1110 may share the cache memory unit 1120. The plurality of core units 1110 and the cache memory unit 1120 may be directly connected or may be connected through a bus interface 1430. The plurality of core portions 1110 may all have the same configuration as the core portion described above. When the processor 1100 includes a plurality of core units 1110, the primary storage unit 1121 of the cache memory unit 1120 includes a plurality of core units 1110 corresponding to the number of the plurality of core units 1110, And the secondary storage unit 1122 and the tertiary storage unit 1123 may be configured to be shared within the plurality of core units 1110 through a bus interface 1130. [ Here, the processing speed of the primary storage unit 1121 may be faster than the processing speed of the secondary and tertiary storage units 1122 and 1123. In another embodiment, the primary storage unit 1121 and the secondary storage unit 1122 are configured in the respective core units 1110 corresponding to the number of the plurality of core units 1110, and the tertiary storage unit 1123 May be configured to be shared by a plurality of core units 1110 via a bus interface 1130. [

The processor 1100 according to the present embodiment includes an embedded memory unit 1140 that stores data, a communication module unit 1150 that can transmit and receive data wired or wirelessly with an external apparatus, A memory control unit 1160, a media processing unit 1170 for processing data output from the processor 1100 or data input from an external input device to the external interface device, and the like. Modules and devices. In this case, a plurality of modules added to the core unit 1110, the cache memory unit 1120, and mutual data can be exchanged through the bus interface 1130.

The embedded memory unit 1140 may include a nonvolatile memory as well as a volatile memory. The volatile memory may include a dynamic random access memory (DRAM), a moblie DRAM, a static random access memory (SRAM), and a memory having a similar function. The nonvolatile memory may be a read only memory (ROM) , NAND flash memory, PRAM (Phase Change Random Access Memory), RRAM (Resistive Random Access Memory), STTRAM (Spin Transfer Torque Random Access Memory), MRAM (Magnetic Random Access Memory) .

The communication module unit 1150 may include a module capable of connecting with a wired network, a module capable of connecting with a wireless network, and the like. The wired network module may be connected to a local area network (LAN), a universal serial bus (USB), an Ethernet, a power line communication (PLC), or the like, as well as various devices for transmitting and receiving data through a transmission line. ), And the like. The wireless network module may be implemented as an Infrared Data Association (IrDA), a Code Division Multiple Access (CDMA), a Time Division Multiple Access (CDMA), or the like, as well as various devices that transmit and receive data without a transmission line. (TDMA), Frequency Division Multiple Access (FDMA), Wireless LAN, Zigbee, Ubiquitous Sensor Network (USN), Bluetooth, Radio Frequency Identification (RFID) , Long Term Evolution (LTE), Near Field Communication (NFC), Wireless Broadband Internet (WIBRO), High Speed Downlink Packet Access (HSDPA) Wideband CDMA (WCDMA), Ultra Wide Band (UWB), and the like.

The memory control unit 1160 is used for processing and managing data transmitted between the processor 1100 and an external storage device operating according to a different communication standard. The memory control unit 1160 may include various memory controllers, for example, an IDE (Integrated Device Electronics) Such as Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Redundant Array of Independent Disks (RAID), Solid State Disk (SSD), External SATA, Personal Computer Memory Card International Association (PCMCIA) Universal Serial Bus, Secure Digital (SD), mini Secure Digital (mSD), micro Secure Digital (SD), Secure Digital High Capacity (SDHC) A Memory Stick Card, a Smart Media Card (SM), a Multi Media Card (MMC), an Embedded MMC (eMMC) When card (Compact Flash; CF) may include a controller for controlling the like.

The media processing unit 1170 processes data processed by the processor 1100, data input from an external input device, video data, voice data, and the like, and outputs the data to the external interface device. The media processing unit 1170 may include a graphics processing unit (GPU), a digital signal processor (DSP), a high definition audio (HD Audio), a high definition multimedia interface ) Controller and the like.

10 is an example of a configuration diagram of a system for implementing a memory device according to an embodiment of the present invention.

Referring to FIG. 10, a system 1200 is an apparatus for processing data, and can perform input, processing, output, communication, storage, and the like to perform a series of operations on data. The system 1200 may include a processor 1210, a main memory 1220, an auxiliary memory 1230, an interface device 1240, and the like. The system 1200 of the present embodiment may be a computer, a server, a PDA (Personal Digital Assistant), a portable computer, a web tablet, a wireless phone, a mobile phone A mobile phone, a smart phone, a digital music player, a portable multimedia player (PMP), a camera, a global positioning system (GPS), a video camera, Such as a voice recorder, a telematics, an audio visual system, a smart television, or the like.

The processor 1210 can control the processing of the input instruction and the processing of the data stored in the system 1200. The microprocessor unit includes a microprocessor unit (MPU), a central processing unit (CPU) ), A single / multi core processor, a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and the like .

The main storage unit 1220 is a storage unit that can move and store program codes and data from the auxiliary storage unit 1230 when the program is executed. The stored contents can be preserved even when the power is turned off. Main memory 1220 may include one or more of the embodiments of memory devices described above. For example, the main memory 1220 may include a storage cell including a variable resistive element; A first selection device coupled to one end of the storage cell, the first selection device having a threshold voltage of a first voltage; And a second selection device coupled to the other end of the storage cell, the second selection device having a threshold voltage greater than the first voltage. This increases the read / write margin of the main memory device 1220 and reduces the leakage current generated in the main memory device 1220, thereby reducing the consumption current and power consumption of the main memory device 1220. As a result, the operating speed and stability of system 1200 can be improved and consumed current and power consumption can be reduced.

The main memory 1220 may further include volatile memory type static random access memory (SRAM), dynamic random access memory (DRAM), or the like, all of which are erased when the power is turned off. Alternatively, the main memory 1220 may be a static random access memory (SRAM) of a volatile memory type, a dynamic random access memory (DRAM), or the like, which does not include the semiconductor device of the above- And the like.

The auxiliary storage device 1230 refers to a storage device for storing program codes and data. It is slower than main memory 1220 but can hold a lot of data. The auxiliary storage 1230 may include one or more of the embodiments of the semiconductor device described above. For example, auxiliary memory 1230 may include a storage cell including a variable resistive element; A first selection device coupled to one end of the storage cell, the first selection device having a threshold voltage of a first voltage; And a second selection device coupled to the other end of the storage cell, the second selection device having a threshold voltage greater than the first voltage. Thereby increasing the read / write margin of the auxiliary storage device 1230 and reducing the leakage current generated in the auxiliary storage device 1230, thereby reducing the consumption current and power consumption of the auxiliary storage device 1230. As a result, the operating speed and stability of system 1200 can be improved and consumed current and power consumption can be reduced.

The auxiliary storage device 1230 may be a magnetic tape, a magnetic disk, a laser disk using light, a magneto-optical disk using the two, a solid state disk (SSD), a USB memory (Universal Serial Bus Memory) USB memory, Secure Digital (SD), mini Secure Digital card (mSD), micro Secure Digital (micro SD), Secure Digital High Capacity (SDHC) A Smart Card (SM), a MultiMediaCard (MMC), an Embedded MMC (eMMC), a Compact Flash (CF) (See 1300 in FIG. 9). Alternatively, the auxiliary storage device 1230 may be a magnetic tape, a magnetic disk, a laser disk using light, a magneto-optical disk using both of them, a solid state disk (DVD) SSD), a USB memory (Universal Serial Bus Memory), a Secure Digital (SD) card, a mini Secure Digital card (mSD), a microSecure digital card (microSD) A Secure Digital High Capacity (SDHC), a Memory Stick Card, a Smart Media Card (SM), a Multi Media Card (MMC), an Embedded MMC (eMMC ), And a data storage system (see 1300 in FIG. 10) such as a Compact Flash (CF) card.

The interface device 1240 may be for exchanging commands, data, and the like between the system 1200 and the external device of the present embodiment. The interface device 1240 may include a keypad, a keyboard, a mouse, a speaker, A microphone, a display, various human interface devices (HID), communication devices, and the like. The communication device may include a module capable of connecting with a wired network, a module capable of connecting with a wireless network, and the like. The wired network module may be connected to a local area network (LAN), a universal serial bus (USB), an Ethernet, a power line communication (PLC), or the like, as well as various devices for transmitting and receiving data through a transmission line. ), And the like. The wireless network module may include various devices for transmitting and receiving data without a transmission line, such as an Infrared Data Association (IrDA), a Code Division Multiple Access (CDMA) (TDMA), a frequency division multiple access (FDMA), a wireless LAN, a Zigbee, a Ubiquitous Sensor Network (USN), a Bluetooth ), Radio Frequency Identification (RFID), Long Term Evolution (LTE), Near Field Communication (NFC), Wireless Broadband Internet (Wibro) (HSDPA), Wideband Code Division Multiple Access (WCDMA), Ultra Wide Band (UWB), and the like.

11 is an example of a configuration diagram of a data storage system implementing a memory device according to an embodiment of the present invention.

11, the data storage system 1300 includes a storage device 1310 having a nonvolatile characteristic for storing data, a controller 1320 for controlling the storage device 1310, an interface 1330 for connection to an external device, And temporary storage 1340 for temporary storage of data. The data storage system 1300 may be a disk type such as a hard disk drive (HDD), a compact disk read only memory (CDROM), a digital versatile disk (DVD), a solid state disk (USB) memory, Secure Digital (SD), mini Secure Digital card (mSD), microSecure digital card (micro SD), high capacity secure digital card Digital High Capacity (SDHC), Memory Stick Card, Smart Media Card (SM), Multi Media Card (MMC), Embedded MMC (eMMC) And may be in the form of a card such as a flash card (Compact Flash; CF).

The storage device 1310 may include a non-volatile memory that semi-permanently stores the data. The nonvolatile memory includes a ROM (Read Only Memory), a NOR Flash Memory, a NAND Flash Memory, a PRAM (Phase Change Random Access Memory), a RRAM (Resistive Random Access Memory), a MRAM .

The controller 1320 may control the exchange of data between the storage device 1310 and the interface 1330. To this end, controller 1320 may include a processor 1321 that performs operations, such as operations, to process instructions entered via interface 1330 outside data storage system 1300.

The interface 1330 is for exchanging commands, data, and the like between the data storage system 1300 and an external device. When the data storage system 1300 is a card, the interface 1330 may be a USB (Universal Serial Bus) memory, a Secure Digital (SD) card, a mini Secure Digital card (mSD) A micro SD card, a Secure Digital High Capacity (SDHC) card, a Memory Stick Card, a Smart Media Card (SM), a Multi Media Card (MMC) Compatible with the interfaces used in devices such as a hard disk, an embedded MMC (eMMC), a compact flash (CF), or the like, or compatible with interfaces used in devices similar to these devices . When the data storage system 1300 is in the form of a disk, the interface 1330 may be an Integrated Device Electronics (IDE), a Serial Advanced Technology Attachment (SATA), a Small Computer System Interface (SCSI), an External SATA (eSATA) Memory Card International Association), Universal Serial Bus (USB), and the like, or compatible with interfaces similar to these interfaces. Interface 1330 may be compatible with one or more interfaces having different types.

The temporary storage device 1340 may temporarily store data in order to efficiently transfer data between the interface 1330 and the storage device 1310 in accordance with diversification and high performance of the interface with the external device, . Temporary storage device 1340 may include one or more of the embodiments of the memory device described above. For example, the temporary storage device 1340 may include a storage cell including a variable resistive element; A first selection device coupled to one end of the storage cell, the first selection device having a threshold voltage of a first voltage; And a second selection device coupled to the other end of the storage cell, the second selection device having a threshold voltage greater than the first voltage. This can increase the read / write margin of the temporary storage device 1340 and reduce the leakage current generated in the temporary storage device 1340, thereby reducing the consumption current and the consumed power of the temporary storage device 1340. As a result, it is possible to improve the operation speed and stability of the data storage system 1300 and reduce the consumed current and power consumption.

12 is an example of a configuration diagram of a memory system for implementing a memory device according to an embodiment of the present invention.

12, the memory system 1400 includes a memory 1410 having a nonvolatile characteristic, a memory controller 1420 for controlling the memory 1420, an interface 1430 for connecting to an external device, and the like, . The memory system 1400 may include a solid state disk (SSD), a USB memory (Universal Serial Bus Memory), a Secure Digital (SD), a mini Secure Digital card (mSD) , A micro secure digital card (micro SD), a secure digital high capacity (SDHC), a memory stick card, a smart media card (SM), a multi media card (MMC), an embedded MMC (eMMC), and a compact flash (CF) card.

Memory 1410 for storing data may include one or more of the embodiments of the memory device described above. For example, the memory 1410 may include a storage cell including a variable resistive element; A first selection device coupled to one end of the storage cell, the first selection device having a threshold voltage of a first voltage; And a second selection device coupled to the other end of the storage cell, the second selection device having a threshold voltage greater than the first voltage. Thereby increasing the read / write margin of the memory 1410 and reducing the leakage current generated in the memory 1410, thereby reducing the consumption current and power consumption of the memory 1410. [ As a result, it is possible to improve the operating speed and stability of the memory system 1400 and to reduce the consumed current and power consumption.

In addition, the memory of the present embodiment may be a non-volatile memory such as a ROM (Read Only Memory), a NOR Flash Memory, a NAND Flash Memory, a PRAM (Phase Change Random Access Memory), an RRAM (Resistive Random Access Memory) Memory) and the like.

Memory controller 1420 may control the exchange of data between memory 1410 and interface 1430. [ To this end, the memory controller 1420 may include a processor 1421 for processing instructions entered through the interface 1430 outside the memory system 1400.

The interface 1430 is for exchanging commands and data between the memory system 1400 and an external device and includes a USB (Universal Serial Bus), a Secure Digital (SD) card, a mini Secure Digital card (mSD), microsecure digital card (micro SD), Secure Digital High Capacity (SDHC), Memory Stick Card, Smart Media Card (SM), MultiMediaCard Compatible with interfaces used in devices such as a MultiMediaCard (MMC), an embedded MMC (eMMC), a Compact Flash (CF), and the like, It can be compatible with the interface used. Interface 1430 may be compatible with one or more interfaces having different types.

The memory system 1400 of the present embodiment includes a buffer memory (not shown) for efficiently transmitting and receiving data between the interface 1430 and the memory 1410 in accordance with diversification and high performance of an interface with an external device, a memory controller, 1440). The buffer memory 1440 for temporarily storing data may include one or more of the embodiments of the memory device described above. For example, the buffer memory 1440 may include a storage cell including a variable resistive element; A first selection device coupled to one end of the storage cell, the first selection device having a threshold voltage of a first voltage; And a second selection device coupled to the other end of the storage cell, the second selection device having a threshold voltage greater than the first voltage. Accordingly, the read current and the power consumption of the buffer memory 1440 can be reduced by increasing the read / write margin of the buffer memory 1440 and reducing the leakage current generated in the buffer memory 1440. As a result, it is possible to improve the operating speed and stability of the memory system 1400 and to reduce the consumed current and power consumption.

In addition, the buffer memory 1440 of the present embodiment may be a static random access memory (SRAM) having a characteristic of being volatile, a dynamic random access memory (DRAM), a read only memory (ROM) having nonvolatile characteristics, a NOR flash memory, A flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer random access memory (STTRAM), and a magnetic random access memory (MRAM). Alternatively, the buffer memory 1440 may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and a read only memory (ROM) having nonvolatile characteristics, instead of the semiconductor device of the above- Memory, a NOR flash memory, a NAND flash memory, a PRAM (Phase Change Random Access Memory), a Resistive Random Access Memory (RRAM), a Spin Transfer Torque Random Access Memory (STTRAM), a Magnetic Random Access Memory (MRAM) have.

The features of the illustrations of the electronic device or system of Figs. 8-12 can be implemented in a variety of devices, systems, or applications. For example, a mobile phone or other portable communication device, a tablet computer, a laptop or laptop computer, a game machine, a smart TV set, a TV set-top box, a Multimedia server, a digital camera with wired / Clocks or other wearing devices.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, .

Claims (32)

An electronic device comprising a semiconductor memory,
The semiconductor memory
A storage cell including a variable resistive element;
A first selection device coupled to one end of the storage cell, the first selection device having a threshold voltage of a first voltage; And
And a second selection device coupled to the other end of the storage cell and having a threshold voltage greater than the first voltage,
&Lt; / RTI &gt;
The method according to claim 1,
The storage cell
The variable resistive element; And
A selection element connected to one end of the variable resistive element and being turned on / off in response to a voltage of a word line,
&Lt; / RTI &gt;
The method according to claim 1,
The electronic device
And a current is passed from the first selecting device to the second selecting device during a read operation.
The method according to claim 1,
The variable resistor element
A first state having a first resistance value or a second state having a second resistance value higher than the first resistance value.
5. The method of claim 4,
The variable resistor element
Wherein the switch is switched to the first state when a first switching current flows from the other end to the one end and switches to the second state when a second switching current larger than the first switching current flows from the one end to the other end.
The method according to claim 1,
The first selection element and the second selection element
And turned on / off in response to the selection signal.
The method according to claim 1,
Wherein the first selection device is fabricated such that the threshold voltage is the first voltage and the second selection device is fabricated such that the threshold voltage is the second voltage.
8. The method of claim 7,
Wherein the spacing of the gates of the at least one second selection device is greater than the spacing of the gates of the at least one first selection device.
8. The method of claim 7,
Wherein the doping concentration of the active region of the second selection device is higher than the doping concentration of the active region of the first selection device.
8. The method of claim 7,
Wherein the width of the gate of the at least one second selection device is greater than the width of the gate of the first selection device.
8. The method of claim 7,
Wherein the distance between the contact and the gate connected to the active region of the second selection device is greater than the distance between the contact and the gate connected to the active region of the first selection device.
The method according to claim 1,
Wherein the first selection element is applied with a back bias voltage such that the threshold voltage is the first voltage and the second selection element is applied with a back bias voltage such that the threshold voltage is the second voltage.
The method according to claim 1,
The variable resistor element
A metal oxide, a phase change material, and a structure in which a tunnel barrier layer is interposed between the two magnetic layers.
The method according to claim 1,
The electronic device further includes a microprocessor,
The microprocessor
A control unit for receiving a signal including an instruction from outside the microprocessor and performing extraction or decoding of the instruction or input / output control of a signal of the microprocessor;
An operation unit for performing an operation according to a result of decoding the instruction by the control unit; And
And a storage unit for storing data for performing the operation, data corresponding to a result of performing the operation, or address of data for performing the operation,
Wherein the semiconductor memory is a part of the memory unit in the microprocessor
Electronic device.
The method according to claim 1,
The electronic device further includes a processor,
The processor
A core unit for performing an operation corresponding to the instruction using data according to an instruction input from the outside of the processor;
A cache memory unit for storing data for performing the operation, data corresponding to a result of performing the operation, or an address of data for performing the operation; And
And a bus interface connected between the core unit and the cache memory unit and transmitting data between the core unit and the cache memory unit,
Wherein the semiconductor memory is part of the cache memory unit
Electronic device.
The method according to claim 1,
The electronic device further includes a processing system,
The processing system
A processor for interpreting a received command and controlling an operation of information according to a result of interpreting the command;
A program for interpreting the command and an auxiliary memory for storing the information;
A main memory for moving and storing the program and the information from the auxiliary memory so that the processor can perform the calculation using the program and the information when the program is executed; And
And an interface device for performing communication with at least one of the processor, the auxiliary memory device, and the main memory device,
Wherein the semiconductor memory is a part of the auxiliary memory or the main memory in the processing system
Electronic device.
The method according to claim 1,
The electronic device further includes a data storage system,
The data storage system
A storage device that stores data and maintains stored data regardless of the supplied power;
A controller for controlling data input / output of the storage device according to an instruction input from the outside;
A temporary storage device for temporarily storing data exchanged between the storage device and the outside; And
And an interface for performing communication with at least one of the storage device, the controller, and the temporary storage device,
Wherein the semiconductor memory is a part of the storage device or the temporary storage device in the data storage system
Electronic device.
The method according to claim 1,
The electronic device further includes a memory system,
The memory system
A memory that stores data and maintains stored data regardless of the power supplied;
A memory controller for controlling data input / output of the memory in response to a command input from the outside;
A buffer memory for buffering data exchanged between the memory and the outside; And
And an interface for performing communication with at least one of the memory, the memory controller, and the buffer memory,
Wherein the semiconductor memory is a memory or a part of the buffer memory
Electronic device.
An electronic device comprising a semiconductor memory,
The semiconductor memory
A first global line;
A second global line;
One or more cell arrays including a plurality of storage cells including variable resistance elements, a first local line connected to one end of the plurality of storage cells, and a second local line connected to the other end of the plurality of storage cells;
At least one first selection element coupled between the first global line and a first local line of a corresponding cell array, the first selection element having a threshold voltage of a first voltage; And
A second select line coupled between the second global line and a second local line of a corresponding cell array and having a threshold voltage greater than the first voltage,
&Lt; / RTI &gt;
20. The method of claim 19,
The storage cell
The variable resistive element; And
A selection element connected to one end of the variable resistive element and turned on / off in response to a voltage of a corresponding one of the plurality of word lines,
&Lt; / RTI &gt;
20. The method of claim 19,
The electronic device
And current flows from the first global line to the second global line through a selected storage cell during a read operation.
20. The method of claim 19,
The variable resistor element
A first state having a first resistance value or a second state having a second resistance value higher than the first resistance value.
23. The method of claim 22,
The variable resistor element
Wherein the switch is switched to the first state when a first switching current flows from the other end to the one end and switches to the second state when a second switching current larger than the first switching current flows from the one end to the other end.
20. The method of claim 19,
Wherein the at least one first select element and the at least one second select element
And turned on / off in response to a corresponding one of the one or more selection signals.
20. The method of claim 19,
Wherein the first selection device is fabricated such that the threshold voltage is the first voltage and the second selection device is fabricated such that the threshold voltage is the second voltage.
20. The method of claim 19,
Wherein the first selection element is applied with a back bias voltage such that the threshold voltage is the first voltage and the second selection element is applied with a back bias voltage such that the threshold voltage is the second voltage.
20. The method of claim 19,
The variable resistor element
A metal oxide, a phase change material, and a structure in which a tunnel barrier layer is interposed between the two magnetic layers.
20. The method of claim 19,
The electronic device further includes a microprocessor,
The microprocessor
A control unit for receiving a signal including an instruction from outside the microprocessor and performing extraction or decoding of the instruction or input / output control of a signal of the microprocessor;
An operation unit for performing an operation according to a result of decoding the instruction by the control unit; And
And a storage unit for storing data for performing the operation, data corresponding to a result of performing the operation, or address of data for performing the operation,
Wherein the semiconductor memory is a part of the memory unit in the microprocessor
Electronic device.
20. The method of claim 19,
The electronic device further includes a processor,
The processor
A core unit for performing an operation corresponding to the instruction using data according to an instruction input from the outside of the processor;
A cache memory unit for storing data for performing the operation, data corresponding to a result of performing the operation, or an address of data for performing the operation; And
And a bus interface connected between the core unit and the cache memory unit and transmitting data between the core unit and the cache memory unit,
Wherein the semiconductor memory is part of the cache memory unit
Electronic device.
20. The method of claim 19,
The electronic device further includes a processing system,
The processing system
A processor for interpreting a received command and controlling an operation of information according to a result of interpreting the command;
A program for interpreting the command and an auxiliary memory for storing the information;
A main memory for moving and storing the program and the information from the auxiliary memory so that the processor can perform the calculation using the program and the information when the program is executed; And
And an interface device for performing communication with at least one of the processor, the auxiliary memory device, and the main memory device,
Wherein the semiconductor memory is a part of the auxiliary memory or the main memory in the processing system
Electronic device.
20. The method of claim 19,
The electronic device further includes a data storage system,
The data storage system
A storage device that stores data and maintains stored data regardless of the supplied power;
A controller for controlling data input / output of the storage device according to an instruction input from the outside;
A temporary storage device for temporarily storing data exchanged between the storage device and the outside; And
And an interface for performing communication with at least one of the storage device, the controller, and the temporary storage device,
Wherein the semiconductor memory is a part of the storage device or the temporary storage device in the data storage system
Electronic device.
20. The method of claim 19,
The electronic device further includes a memory system,
The memory system
A memory that stores data and maintains stored data regardless of the power supplied;
A memory controller for controlling data input / output of the memory in response to a command input from the outside;
A buffer memory for buffering data exchanged between the memory and the outside; And
And an interface for performing communication with at least one of the memory, the memory controller, and the buffer memory,
Wherein the semiconductor memory is a memory or a part of the buffer memory
Electronic device.

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