KR20170038258A - Sensing circuit and databus circuit for eeprom - Google Patents

Abstract

The present invention relates to a technique for improving the performance of a sense amplifier and a data bus applied to an EEPROM for an MCU.
For this purpose, a differential amplifier is used to improve the data sensing speed, a distributed data bus structure is applied to improve the switching speed of the data bus, and the bit line switching speed can be improved in the read data switch circuit.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a sensing circuit and a data bus circuit,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier and a data bus circuit applied to an EEPROM for MCU (Micro Controller Unit). More particularly, the present invention relates to a differential amplifier for improving a data sensing speed, The present invention relates to a sensing circuit and a data bus circuit of the I-Pillar that can improve the switching speed of the data bus and improve the bit line switching speed in the read data switch circuit.

In general, non-volatile memory intellectual property (NVM IP) is used in SOC (System On Chip) field of smart card, non-contact card, mobile communication, And a nonvolatile memory having characteristics of a write operation and a low power consumption. It is an embedded non-volatile memory for microcontroller unit (MCU) that performs functions such as updating information in real time, storing security data, and storing instruction code. It is composed of OTP (One-Time Programmable) EEPROM memory is used for non-volatile memory of 1Mb or less.

2. Description of the Related Art In recent years, studies have been actively conducted on the lowering of the EEPROM, lower power consumption, and higher speed. An SSTC-type EEPROM cell has been proposed to reduce the size of the EEPROM. A high-voltage P-well (HPW), which has been separated in word units in an EEPROM cell array, It is possible to reduce the area of the EEPROM cell array by sharing the HPW in units of two adjacent words. In order to reduce the stand-by current, a digital sensing DB (Data Bus) sensing circuit and a low-power DC-DC conversion circuit which do not require a reference voltage generating circuit have been proposed as part of the EEPROM power saving. Also, a divided DB type circuit has been proposed for the EEPROM speed up. To test the EEPROM function, a 32-word (512-bit) page buffer circuit was used to reduce the test time. In addition, in order to guarantee the variable voltage of the EEPROM cell, the drain voltage is shifted during the wafer test, and the read mode for reading the EEPROM cell with the external VRD voltage is used. Verify-Read mode) has been proposed.

The main features of the 256 Kb EEPROM IP designed using the conventional 0.18 탆 EEPROM process are shown in the table below. An EEPROM cell having a SSTC (Side-wall Selective Transistor Cell) structure is used as the EEPROM, where the VDD voltage is 1.8V and the temperature range is -40 ° C to 85 ° C. The operation modes of the EEPROM include a page erase, a page buffer load, a page program, a normal read, and a write-verify-read mode. Here, page erase and page program are performed in 32 word units, and page buffer load and read operations are performed in word units.

FIG. 1 is a block diagram of a conventional EEPROM IP. As shown in FIG. 1, an EEPROM cell array 110, a row decoder 120, a page buffer 130, A buffer 140, a control logic section 150, and a DC-DC converter 160.

The DRAM cell array 110 includes an option memory 111, a data memory 112, and a program memory 113.

The row decoder 120 decodes the row address A [15: 6] and supplies it to the word line WL_OM [1: 0] of the option memory 111, the word line WL_DM [3: 0] of the data memory 112, And activates one of the word lines WL_PM [255: 0] of the word lines WL1 to WL3.

The page buffer 130 is implemented as a page buffer of 32 words in order to reduce the write test time for the erase cell array 110 and has a write data switch.

The data output buffer 140 includes a read data S / A (sense amplifier) and an output data buffer (Dout buffer), and has a read data switch. The word cell data selected in the ROM cell array 110 is sensed by the RD S / A and output to the DOUT [15: 0] port through the output data buffer.

The control logic unit 150 outputs the control signal of the ROM cell array 110 according to the operation mode. For example, in the page buffer load mode, the input word data DIN [15: 0] is loaded into the page buffer 130 using the column address A [4: 0]. The control logic unit 150 outputs the column address A [5: 0] to the data output buffer 140 in the read mode. Accordingly, the data output buffer 140 outputs the data of the selected word cell among the 64 word cells connected to the selected word line WL through the internal RD switch.

The DC-DC converter 160 serves to supply the VRD (read voltage) voltage and the VPP and VPPL voltages required in the read mode for the eroma cell array 110 do.

The address signal A [15: 0], the input data signal DIN [15: 0], and the output signal DIN [15: 0] as the interface signals applied to the EEPROM IP of FIG. 1 as control signals RSTb, PWRDN, RD, ERS, PGM, LOAD and WVRb, And data signal DOUT [15: 0].

FIG. 2 is a circuit diagram of a conventional digital data bus sensing applied to the EEPROM IP. As shown in FIG. 2, a first pull-up transistor unit 210, a second pull-up transistor unit 220, and a sensing amplifier unit 230 are included do.

The first pull-up transistor unit 210 precharges the data bus DB to the power supply voltage VDD when performing a read operation on the EEPROM cell of the EEPROM IP.

The second pull-up transistor unit 220 removes a voltage drop due to a leaking phenomenon of a data bus DB which occurs when data programmed to '1' is read from the EEPROM cell.

The sensing amplifier 230 amplifies and latches data transferred to the data bus DB and outputs the data to a data output terminal.

Since the digital data bus sensing circuit does not require a separate reference voltage, it consumes less power and has a relatively simple circuit configuration, which is advantageous in that it requires a small area.

However, in the conventional digital data bus sensing circuit, since the data sensing method uses V _IH (Input High Voltage) and V _IL (Input Low Voltage) of the inverter as a method of outputting data in synchronization with a clock signal, Data can be accurately sensed only when the bus voltage rises above V _IH or falls below V _IL .

The normalized V _IL and V _IH of the clock inverter in the prior art read data sense amplifier Values are 0.417 and 0.687, respectively. In the case of an EEPROM cell programmed with '0', sensing can be performed only when the normalized data bus voltage falls below 0.417, and sensing is performed at a lower voltage when the sensing margin is considered. In this case, since it takes time until the data bus voltage is sufficiently discharged, there is a problem that it can not be used in an EEPROM requiring a high-speed operation with an access time of 50 ns or less.

A problem to be solved by the present invention is to improve the sensing speed of a data bus using a differential amplifier in an EEPROM for an MCU and to improve the switching speed of the data bus by applying a distributed data bus structure And to improve the bit line switching speed in the read data switch circuit.

According to another aspect of the present invention, there is provided a sensing circuit of an i-ropolumn including a first pull-up transistor unit for precharging a data bus to a power supply voltage in a reading mode of an epromascent cell; A second pull-up transistor unit for preventing a voltage drop due to a leaking phenomenon of a data bus occurring when data programmed from the dipole cell is read; And a differential sense amplifier unit for differentially amplifying and outputting the difference voltage between the voltage of the data bus connected to the dipole cell and the reference voltage.

According to another aspect of the present invention, there is provided a data bus circuit of an I-Pillar, including: an I-PIL cell array; A differential sense amplifier unit including a differential sense amplifier divided into eight for the i-pill cell array; A switch unit for connecting each of a plurality of bit lines divided into eight parts of the i-pill cell array and a plurality of data buses divided into eight parts of the differential sense amplifier part; And an output buffer divided into eight sections between the differential sense amplifier section and the data output terminal.

The present invention improves the sensing speed of the data bus using a differential amplifier, thereby improving the access time.

Further, the present invention has an effect that the access time is shortened by adopting one switch structure without using a switch connected in series to the sense line switch unit in the read data switch circuit.

In addition, the present invention reduces the parasitic capacitance component of the data bus by applying a distributed data bus structure, thereby improving the switching speed.

1 is a block diagram of an EEPROM IP according to the prior art.
2 is a conventional digital data bus sensing circuit diagram applied to EEPROM IP.
3 is a sensing circuit diagram of the i-pill according to an embodiment of the present invention.
FIG. 4 is a block diagram of the data bus circuit of the I-pill according to another embodiment of the present invention.
5 is a circuit diagram of a read data switch included in the switch unit of FIG.
6 is a graph of experimental results for a data bus structure divided into eight and four.
FIG. 7 is a graph of bit line precharging test results according to the switch structure of the bit line switch part.
8A and 8B are graphs showing experimental results on the voltage difference between the sensing voltage of the data bus and the reference voltage.
FIG. 9 is a waveform diagram of an experimental result on an EEPROM IP to which the present invention is applied.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a sensing circuit diagram of the eipulm according to an embodiment of the present invention. As shown in FIG. 3, the first pull-up transistor unit 310, the second pull- up transistor unit 320, and the differential amplifier- ).

The first pull-up transistor unit 310 precharges the data bus DB to the power supply voltage VDD when performing a read operation on the cell of the EEPROM IP.

To this end, the first pull-up transistor unit 310 An inverter I31 for inverting and outputting the precharge voltage; And a MOS transistor MP31 whose both terminals are connected to the power supply voltage VDD and the data bus DB respectively and whose gates are connected to the output terminal of the first inverter I31.

The second pull-up transistor unit 320 prevents a voltage drop due to a leaking phenomenon of a data bus DB that occurs when data programmed with '1' is read from the EEPROM cell.

To this end, the second pull-up transistor unit includes a MOS transistor MP32 whose both terminals are connected to the power supply voltage VDD and the data bus DB, respectively; And a resistor R31 connected between the ground terminal and the MOS transistor MP32. Here, 'MP' means a P-channel MOS transistor (PMOS transistor).

The differential sense amplifier unit 330 includes a D-type flip-flop type differential sense amplifier 331 and a latch unit 332 to amplify and output the differential voltage between the voltage of the data bus DB and the reference voltage VREF_RD It plays a role.

To this end, the differential sense amplifier unit 330 includes a MOS transistor MP33 to which a sense amplifier enable signal SAEN is applied to a gate connected in parallel between a power supply voltage VDD and a set node SN, A MOS transistor MP34 connected to the node RN; A MOS transistor MP35 having a gate connected in parallel between the power supply voltage VDD and the reset node RN and connected to the set node SN and a MOS transistor MP36 having a gate to which a sense amplifier enable signal SAEN is applied; A MOS transistor MN31 having one terminal connected to the set node SN and a gate connected to the reset node RN; A MOS transistor MN32 having a first terminal connected to the reset node RN and a gate connected to the set node SN; A MOS transistor MN33 whose one terminal is connected to the other terminal of the MOS transistor MN31 and whose gate is connected to the data bus DB; A MOS transistor MN34 having a first terminal connected to the other terminal of the MOS transistor MN32 and a gate connected to the reference voltage VREF_RD; An inverter I32 inverting the sense amplifier enable inversion signal SAENb; And a MOS transistor MN35 whose one terminal is commonly connected to the other terminal of the MOS transistors MN33 and MN34 and whose other terminal is connected to the ground terminal and whose gate is connected to the output terminal of the inverter I32 Respectively. Here, 'MP' means a P-channel MOS transistor (PMOS transistor), and 'MN' means an N-channel MOS transistor (NMOS transistor).

To this end, the latch unit 332 is connected to the set node SN and the reset node RN, respectively, and the other terminal thereof is connected to the output terminal of the corresponding NAND gate to form a NAND gate ND31 ), (ND32); And inverters I33 and I34 for inverting and outputting the output signals of the NAND gates ND31 and ND32, respectively.

When the sense amplifier enable signal SAEN is supplied at a high level equal to or higher than a certain level, the transistors MP35 and MP36 are turned off thereby causing the set node SN and the reset node RN to be 'high' The read data RD of the latch unit 332 maintains the original value. When the sensing voltage is input through the data bus DB and the sense amplifier enable signal SAENb transitions to a low level below a certain level, the transistors MP35 and MP36 are turned off while the transistors MN31 and MN33 , MN35) are turned on. As a result, the set node SN is pulled down, the transistor MN32 is turned on, and the transistor MN34 is turned off, thereby keeping the reset node RN 'high'. Therefore, the difference voltage between the data bus DB and the reference voltage VREF_RD is amplified by the differential sense amplifier 331, and then output through the latch unit 332. [ At this time, if the sensing voltage transmitted through the data bus DB is higher than the reference voltage VREF_RD, the latch unit 332 outputs a high level of the VDD level. However, if the sensing voltage is lower than the reference voltage VREF_RD, the set node SN goes high, the reset node RN goes low, Quot; low " Once the reset node RN is pulled down, the transistor MN32 is turned off, so that even if the voltage of the data bus DB changes, the output voltage is not affected. In this state, when the sense amplifier enable inversion signal SAENb transitions to a high level, the set node SN and the reset node RN become high again, and the above amplifying operation is repeated do.

FIG. 4 is a block diagram of a data bus circuit of the I-pill according to another embodiment of the present invention. As shown in FIG. 4, the I-focus cell array 110, the switch unit 410, the differential sense amplifier unit 420 And an output buffer unit 430.

The differential sense amplifier section 420 includes differential sense amplifiers divided into eight for one dipole cell array 110. The differential sense amplifier includes 16 differential sense amplifiers having the structure as shown in FIG. do.

A switch unit 410 is provided between the dipole cell array 110 and the differential sense amplifier unit 420 in correspondence with the differential sense amplifier unit 420 having such a structure. The switch unit 410 includes eight read data switch units, and each of the read data switch units includes 128 read data switches.

An output buffer unit 430 is provided corresponding to the differential sense amplifier unit 420 and includes an output buffer divided into eight parts between the differential sense amplifier unit 420 and the data output terminal DOUT [15: 0] .

The parasitic capacitor component present in the data bus DB affects the operation speed of the differential sense amplifier unit 420. This mainly affects the interconnect capacitance of the DB, the junction capacitance of the NMOS transistor, Gate overlap capacitance) component.

As a result of experiments, it has been found that the parasitic capacitance existing in the differential sense amplifier section 420 is determined according to the number of divided parts of the differential sense amplifier section 420.

According to the experimental results, in the structure in which the differential sense amplifier section 420 is divided into four differential sense amplifiers, there are sixteen 5V NMOS transistors having an interconnect capacitance of 56.6 fF, a junction capacitance of 12.9 fF and a gate overlap capacitance of 0.817 fF And the total parasitic capacitance is about 276.3fF.

In contrast, in the differential sense amplifier section 420 having eight differential sense amplifiers as described above, the interconnect capacitance is reduced to about 32 fF, and the total parasitic capacitance is reduced to 141.816 fF. Accordingly, the DB discharge time is reduced so much that high-speed data sensing is possible.

5 is a circuit diagram of a read data switch included in the switch unit of FIG. 4, and includes a bit line switching control unit 510, a bit line switch unit 520, and a sense line switch unit 530 .

The bit line switching control unit 510 outputs a switching control signal CS according to the control signals RDEN, YPRE0, and YPRE1. The bit line switch unit 520 controls the switching operation of the transistor MN54 according to the switching control signal CS to connect the bit line BL to the data bus DB. The sense line switch unit 530 controls the switching operation of the switch MN55 according to the enable signal SRC_EN to connect the sense line SL to the ground terminal.

When operating in a read mode of EEPROM IP, the bit line switch unit 520 connects the bit line BL selected by the column address to the data bus DB to transfer the data of the dipole cell array to the differential sense amplifier of FIG. To the corresponding sense amplifier of the unit (420).

Since the high voltage such as VPP (14V) or VPPL (11V) is applied to the bit line BL when operating in the write mode of EEPROM IP, the switching transistor MN54 is a Native HV NMOS transistor Was used. The bit line BL to which a voltage of 1.98V (VDD) is applied when the transistor MN54 is driven with a voltage of VDDP (= 3.15V) because it has a low threshold voltage of about 0.3V due to the characteristics of the native transistor. And the data bus (DB) without loss.

(10 pA / 占 퐉 占 8 占 퐉 占 1024EA) through the transistor MN54 turned off when 14V is applied to the bit line BL in the EEPROM IP erase mode and the data bus DB is precharged to the VDD voltage, Off-leakage current flows.

In order to reduce the off-leakage current, a transistor connected in series to the bit line switch unit 520 is provided so as to secure the low power characteristic. The off-set quiescent current is 9.2 nA (3 pA / 탆 x 3 탆 x 1024EA ). ≪ / RTI >

However, in this case, the ON current flowing through the series-connected transistors is reduced, and the precharging time of the bit line BL is increased. As a result, the voltage of the bit line BL within the required pre- The voltage can not be reached. Due to this phenomenon, when reading the EEPROM cell programmed with '1', stable data sensing becomes impossible due to the voltage drop of the database (DB).

Therefore, in this embodiment, only one transistor MN54 is used in the bit line switch unit 520. [ As a result, the precharge time of the bit line BL is shortened and the access time is increased accordingly. In addition, the voltage drop of the data bus (DB) caused by reading the EEPROM cell programmed with '1' is eliminated, and stable data sensing is possible.

FIG. 6 shows a data bus (DB) structure divided into 8 parts as shown in FIG. 4 in a simulation condition of VDD = 1.62V, VDDP = 3.0V, Temp. = 85 ° C and a slow model parameter, (DB) of the data bus structure of FIG. Here, the reference voltage is 0.75 VDD and designed to be sensed by the sense amplifier enable inversion signal (SAENb) at 0.5 VDD voltage to secure the DB sensing voltage (? V). The DB dis- charging time of the four separated structures and the eight separated structures of 0.5 VDD voltage are 43.22 ns and 40.01 ns, respectively, which is about 3.21 ns.

FIG. 7 is a graph illustrating a result of removing one transistor out of two transistors connected in series in the bit line switch unit 520 and comparing the bit line BL free The results of the charging simulation are shown. In the case of using two transistors connected in series to the bit line switch unit 520 during the precharge time and when the bit line BL was removed, the time required for the voltage of the bit line BL to reach 0.75 VDD was 10.7 ns and 2.96 ns, respectively. As a result, when one transistor is used for the bit line switch unit 520 as shown in FIG. 5, it can be confirmed that the voltage of the bit line BL is close to the VDD voltage during the precharge time. In this simulation, VDD = 1.98V, VDDP = 3.0V, Temp. = - 40 ℃, SS model parameters were used in Worst Case.

FIG. 8 shows simulation results of the voltage difference? V between the sensing voltage V_DB of the data bus and the reference voltage VREF_RD in FIG. FIG. 8A shows the sensing voltage V_DB programmed to '0', and FIG. 8B shows the sensing voltage V_DB programmed to '1'. Here, the delay time of the sense amplifier enable inversion signal SAENb is adjusted so as to obtain a normalized? V value of about 0.2 VDD or more. For the removed EEPROM cell, the minimum ΔV was 0.382V for VDD = 1.62V, VDDP = 3.3V, Temp. = - 40 ° C and SF model parameters, and the normalized value was 0.24 VDD. For a programmed EEPROM cell, the minimum ΔV was 0.388V for VDD = 1.98V, VDDP = 3.0V, Temp. = 25 ° C and the SF model parameter simulation condition, and the normalized value was 0.193.

9 shows simulation results of EEPROM IP according to a critical path method in a reading mode of VDD = 1.62V, VDDP = 3.0V, Temp. = 85 ° C, and SS model parameter conditions. The bit line BL is precharged by the read data enable signal RDEN of the read data signal RD. At this time, the data bus DB is precharged to VDD by the precharge signal PRECHARGE activated in the standby mode. When the precharge signal PRECHARGE is disabled, the word line WL is activated by the XDEC_EN signal and the data of the EEPROM cell is transferred to the data bus DB through the transistor MN54 of the bit line switch unit 520. [ After the data is transmitted, the sense amplifier enable signal SAENb is activated by the internal delay, and the data of the data buffer DB is sensed by the data bus sense amplifier DB S / A, . Simulation results show that access time is equal to 45.8 ns for both deleted and programmed cells.

Although the preferred embodiments of the present invention have been described in detail above, it should be understood that the scope of the present invention is not limited thereto. These embodiments are also within the scope of the present invention.

110: a dipole cell array 310: a first pull-up transistor unit
320: second pull-up transistor unit 330: differential sense amplifier unit
410: switch section 420: differential sense amplifier section
430: Output buffer section

Claims (10)

A first pull-up transistor unit for precharging the data bus to a power supply voltage in a read mode of the readout cell;
A second pull-up transistor unit for preventing a voltage drop due to a leaking phenomenon of a data bus occurring when data programmed from the dipole cell is read; And
And a differential sense amplifier unit for differentially amplifying and outputting a voltage difference between a voltage of a data bus connected to the i-focus cell and a reference voltage.
2. The semiconductor memory device according to claim 1, wherein the first pull-
A first inverter for inverting and outputting the precharge voltage; And
And a first PMOS transistor having a gate connected to the output terminal of the first inverter and a gate connected to the output terminal of the first inverter.
2. The semiconductor memory device according to claim 1, wherein the second pull-
A second PMOS transistor having both terminals connected to the power supply voltage and the data bus, respectively; And
And a first resistor connected between the ground terminal and the second PMOS transistor.
The differential amplifier circuit according to claim 1, wherein the differential sense amplifier section
A D-type flip-flop type differential sense amplifier for differentially amplifying a voltage difference between the voltage of the data bus and the reference voltage; And
And a latch for latching the output voltage of the differential sense amplifier.
The differential amplifier circuit according to claim 4, wherein the differential sense amplifier
A third PMOS transistor to which a sense amplifier enable signal is applied to a gate connected in parallel between the power supply voltage and a set node, and a fourth PMOS transistor having a gate connected to a reset node;
A fifth PMOS transistor having a gate connected in parallel between the power supply voltage and the reset node and connected to the set node, and a sixth PMOS transistor having the gate to which the sense amplifier enable signal is applied;
A first NMOS transistor having one terminal connected to the set node and a gate connected to the reset node;
A second NMOS transistor having one terminal connected to the reset node and a gate connected to the set node;
A third NMOS transistor having one terminal connected to the other terminal of the first NMOS transistor and a gate connected to the data bus;
A fourth NMOS transistor having one terminal connected to the other terminal of the second NMOS transistor and a gate connected to the reference voltage;
A second inverter for inverting the sense amplifier enable inverted signal; And
A fifth NMOS transistor having one terminal commonly connected to the other terminal of the third NMOS transistor and the fourth NMOS transistor, the other terminal connected to the ground terminal, and a gate connected to the output terminal of the second inverter, And a sensing circuit for sensing a current flowing through the sensing circuit.
5. The apparatus of claim 4, wherein the latch portion
A first NAND gate and a second NAND gate each having a first terminal connected to a set node and a reset node, and the other terminal connected to an output terminal of the corresponding NAND gate to constitute a latch; And
And a third inverter and a fourth inverter for inverting and outputting the output signals of the first NAND gate and the second NAND gate, respectively. Ion cell array;
A differential sense amplifier unit including a differential sense amplifier divided into eight for the i-pill cell array;
A switch unit for connecting each of a plurality of bit lines divided into eight parts of the i-pill cell array and a plurality of data buses divided into eight parts of the differential sense amplifier part; And
And an output buffer section having an output buffer divided into eight sections between the differential sense amplifier section and the data output terminal.
8. The apparatus according to claim 7, wherein the switch unit
A bit line switching control unit for outputting a switching control signal according to a control signal; And
And a bit line switch unit for controlling an internal switch operation according to the switching control signal to connect the bit line to the data bus.
9. The apparatus of claim 8, wherein the switch
And one of the MOS transistors connected between the bit line and the data bus. 8. The semiconductor memory device according to claim 7, wherein the data bus circuit
Further comprising a sense line switch unit for controlling the switching operation of the switch according to an enable signal to connect the sense line to the ground terminal.

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