KR20200016100A - Double Rate Driving type Display Device And Driving Method Thereof - Google Patents

Abstract

The display device of the double rate driving method according to an exemplary embodiment of the present invention is connected such that a pixel of a first color disposed on one side of a data line and a pixel of a second color disposed on the other side of the data line share the data line. A display panel in which the pixel of the first color and the pixel of the second color are connected to different gate lines; A timing controller for changing a phase between the scan shift clocks at a predetermined period; A gate driver generating scan signals corresponding to the scan shift clocks and applying the scan signals to the gate lines; And a data driver configured to generate data voltages synchronized with the scan signals and to apply the data voltages to the data lines, wherein the data voltages are successively n (n is a positive integer of 2 or more) for pixels of the same color. The order in which the data voltages are applied to the line and written into the pixels is changed from frame to frame according to the phase change between the scan shift clocks.

Description

Double rate driving type display device and driving method thereof {Double Rate Driving type Display Device And Driving Method Thereof}

The present specification relates to an active matrix type display device.

Display devices are widely used in portable computers such as laptop computers, PDAs, mobile phones, and the like, as well as monitors of desktop computers due to the advantages of miniaturization and light weight. Such display devices include liquid crystal displays (LCDs), plasma display panels (PDPs), organic light-emitting diode displays, and the like. In particular, an active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter, referred to as OLED) that emits light by itself, and has an advantage of fast response speed and high luminous efficiency, luminance, and viewing angle.

The OLED display adopts a double rate driving type (DRD) to reduce the number of output channels of the data driver. According to the DRD method, two pixels disposed adjacent to each other with one data line therebetween share the data line, and the two pixels are sequentially driven by the data voltage supplied from the data line. According to the DRD method, the number of data lines and the number of output channels of the data driver connected to the data lines are reduced by one half of the number of pixels belonging to one pixel line. Here, one pixel line refers to a collection of pixels disposed adjacent to each other along one horizontal direction.

According to the DRD method, two pixels sharing one data line implement different colors, for example, a first color and a second color. At this time, the data driver alternately outputs the first color data voltage and the second color data voltage. In the case of the organic light emitting diode display, since the luminous efficiency is different for each color, the data voltage for the first color and the data voltage for the second color that implement the same gray scale may be different from each other. In addition, in the OLED display, similar luminance is often displayed in adjacent pixels. In this case, pixels of the same color may have the same or similar data voltage but different data voltages between pixels of different colors.

For this reason, when the conventional DRD method is adopted, the heat generation of the data driver may be problematic because the transition width of the data voltage continuously output from the data driver is increased. In addition, in the case of adopting the conventional DRD method, since the transition period of other inter-color data voltages continuously output from the data driver is shortened, periodic bright lines / dark lines can be visually recognized.

Accordingly, the present disclosure provides a display device of a double rate driving method and a driving method thereof in which heat generation of the data driver is reduced and the periodic bright / dark lines are less visible.

The display device of the double rate driving method according to an exemplary embodiment of the present invention is connected such that a pixel of a first color disposed on one side of a data line and a pixel of a second color disposed on the other side of the data line share the data line. A display panel in which the pixel of the first color and the pixel of the second color are connected to different gate lines; A timing controller for changing a phase between the scan shift clocks at a predetermined period; A gate driver generating scan signals corresponding to the scan shift clocks and applying the scan signals to the gate lines; And a data driver configured to generate data voltages synchronized with the scan signals and to apply the data voltages to the data lines, wherein the data voltages are successively n (n is a positive integer of 2 or more) for pixels of the same color. The order in which the data voltages are applied to the line and written into the pixels is changed from frame to frame according to the phase change between the scan shift clocks.

According to the embodiments of the present disclosure, the present invention has the following effects.

According to the present invention, the phases of the scan shift clocks may be set to continuously apply data voltages to pixels of the same color, thereby greatly reducing heat generation and power consumption of the data driver.

In addition, the present invention can significantly reduce visibility of periodic dark spots / bright spots by changing the phase of the scan shift clocks every frame every n frame periods so that the color shift pixel positions are not fixed and dispersed.

Further, the present invention can secure the stability of the operation by fixing the phase of the carry shift clocks and / or sense shift clocks irrelevant to the data write operation regardless of the phase change between the scan shift clocks.

Effects according to the present specification are not limited by the contents exemplified above, and more various effects are included in the present specification.

1 illustrates a display device according to an exemplary embodiment of the present invention.
2 and 3 are comparative examples corresponding to the present invention, which illustrate an example of a data writing order in a DRD scheme.
4A to 4D are diagrams illustrating an example of a data writing order in a DRD scheme according to an embodiment of the present invention.
5A and 5B are diagrams illustrating an example of a data writing order in a DRD scheme according to another embodiment of the present invention.
FIG. 6 is a diagram illustrating an example of the pixel array illustrated in FIG. 1.
FIG. 7 is a diagram illustrating a connection structure between stages constituting the gate driver of FIG. 1 and clock wires.
FIG. 8 is a view illustrating an nth stage among stages configuring the gate driver of FIG. 7.
9A through 9D are gate shift clocks applied to the gate driver of FIG. 7 and show operation timings of the gate shift clocks for implementing the data write order of FIGS. 4A through 4D.
10A and 10B are gate shift clocks applied to the gate driver of FIG. 7 and show operation timings of the gate shift clocks for implementing the data write order of FIGS. 5A and 5B.
FIG. 11 is a diagram illustrating another example of the pixel array illustrated in FIG. 1.
FIG. 12 is a diagram illustrating another connection configuration between the stages and the clock wires configuring the gate driver of FIG. 1.
FIG. 13 is a view illustrating an nth stage among stages configuring the gate driver of FIG. 12.
14A through 14D are gate shift clocks applied to the gate driver of FIG. 12 and illustrate operation timings of gate shift clocks for implementing the data write order of FIGS. 4A through 4D.
15A and 15B are gate shift clocks applied to the gate driver of FIG. 12 and illustrate operation timings of gate shift clocks for implementing the data writing order of FIGS. 5A and 5B.

Advantages and features of the present specification, and a method of accomplishing the same will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but may be implemented in various different forms, only the present embodiments are provided to make the disclosure of the present specification complete, and are commonly known in the art. It is provided to fully inform the person having the scope of the invention, and this specification is only defined by the scope of the claims.

Shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present specification are exemplary, and thus the present specification is not limited to the illustrated items. Like reference numerals refer to like elements throughout. When 'comprises', 'haves', 'consists of' and the like mentioned in the present specification are used, other parts may be added unless 'only' is used. In the case where the component is expressed in the singular, the plural includes the plural unless specifically stated otherwise.

In interpreting a component, it is interpreted to include an error range even if there is no separate description.

In the case of the description of the positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on top', 'on bottom', 'next to', etc. Alternatively, one or more other parts may be located between the two parts unless 'direct' is used.

The first, second, etc. may be used to describe various components, but these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component referred to below may be a second component within the spirit of the present specification.

In the present specification, the pixel circuit and the gate driver formed on the substrate of the display panel may be implemented as TFTs having an n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure, but are not limited thereto and may be implemented with TFTs having a p-type MOSFET structure. have. The TFT is a three-electrode element that includes a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. Carriers in the TFT begin to flow from the source. The drain is an electrode from which the carrier exits to the outside. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), since the carrier is an electron, the source voltage has a voltage lower than the drain voltage so that electrons can flow from the source to the drain. Since electrons flow from the source to the drain in the n-type TFT, the direction of the current flows from the drain to the source. In contrast, in the case of the p-type TFT (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In the p-type TFT, current flows from the source to the drain because holes flow from the source to the drain. Note that the source and drain of the MOSFET are not fixed. For example, the source and drain of the MOSFET can be changed according to the applied voltage. Therefore, in the description of the embodiments of the present specification, one of the source and the drain is described as the first electrode, and the other of the source and the drain as the second electrode.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following embodiments, the display device will be described based on an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical spirit of the present disclosure is not limited to an organic light emitting display device, but may be applied to an inorganic light emitting display device including an inorganic light emitting material.

In the following description, when it is determined that a detailed description of known functions or configurations related to the present disclosure may unnecessarily obscure the subject matter of the present disclosure, the detailed description thereof will be omitted.

1 illustrates a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel 10, a timing controller 11, a data driver 12, and a gate driver 13.

The display panel 10 may include a plurality of data lines DL, reference voltage lines RL, and a plurality of gate lines GL. In addition, the pixels PXL may be disposed in the crossing regions of the data lines DL, the reference voltage lines RL, and the gate lines GL. In addition, a pixel array may be formed in the display area AA of the display panel 10 by pixels arranged in a matrix form.

In the pixel array, pixels may be divided line by line based on one direction. For example, the pixels may be divided into a plurality of pixel lines based on the gate line extension direction (or horizontal direction). Herein, the pixel line is not a physical signal line but an aggregate of pixels disposed adjacent to each other along one horizontal direction.

In the pixel array, each of the pixels may be connected to a digital-to-analog converter (hereinafter, referred to as a DAC) through a data line DL, and connected to a sensing unit through a reference voltage line RL. The reference voltage line RL may be further connected to the DAC for supply of the reference voltage. The DAC and the sensing unit may be embedded in the data driver 12, but are not limited thereto. On the other hand, in the pixel array, each of the pixels may be connected to the high potential pixel power supply through the power supply line.

A plurality of pixels for implementing different colors in the pixel array may configure one unit pixel. The unit pixel may be implemented as pixels of three colors or pixels of four colors. The pixels of three colors may include pixels of a first color, pixels of a second color, and pixels of a third color. The first to third colors are different from each other, and may be any one of red, green, and blue. The pixels of four colors may include pixels of a first color, pixels of a second color, pixels of a third color, and pixels of a fourth color. The first to fourth colors are different from each other, and may be any one of red, green, blue, and white. In the following embodiment, although the pixels of four colors are used, it should be noted that the technical idea of the present invention may be applied to the pixels of three colors.

The pixels in the pixel array may be driven in a DRD manner. To this end, a pixel of a first color disposed on one side of the data line DL and a pixel of a second color disposed on the other side of the data line DL may be connected to share the data line DL on the same pixel line. Can be. In this case, the pixel of the first color and the pixel of the second color are connected to different gate lines GL and scanned at different timings, thereby receiving data voltages applied through the same data line DL at a predetermined timing. Can be.

The timing controller 11 is based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE input from the host system 14. The data control signal DDC for controlling the operation timing of the data driver 12 and the gate control signal GDC for controlling the operation timing of the gate driver 13 may be generated. The gate control signal GDC may include a gate start signal, gate shift clocks, pixel line select & release signals, a sensing start timing indication signal, and the like. The data control signal DDC includes a source start pulse, a source sampling clock, a source output enable signal, and the like. The source start pulse controls the data sampling start timing of the data driver 12. The source sampling clock controls the sampling timing of the data based on the rising or falling edge. The source output enable signal controls the output timing of the data driver 12.

The timing controller 11 controls the display driving timing and the sensing driving timing of the pixel lines of the display panel 10 based on the timing control signals GDC and DDC, so that the driving characteristics of the pixels are displayed in real time during image display. Can be sensed.

Here, the sensing driving refers to sensing driving characteristics of pixels by writing sensing data voltages to pixels arranged in a specific pixel line, and updating a compensation value for compensating for driving characteristics change of the pixels based on the sensing result. It is driving. The display driving is a driving for reproducing the input image by writing an image data voltage corresponding to the input image data to pixels arranged in all the pixel lines.

The timing controller 11 may implement display driving in a vertical active period in one frame, and sense driving in a vertical blank period in which no display driving is performed. On the other hand, the sensing driving may be performed during the power-on period from when the system power is applied until the screen is turned on, or may be performed during the power-off period after the screen is turned off until the system power is released.

The timing controller 11 may output gate shift signals and a gate start signal including a carry shift clock, a scan shift clock, and a sense shift clock to the gate driver 13 for display driving and sensing driving. The timing controller 11 may further output the pixel line selection & release signals and the sensing start timing indication signal to the gate driver 13 to drive the specific pixel line to be sensed.

The timing controller 11 may receive input image data DATA from the host system 14 and output the input image data DATA to the data driver 12. The timing controller 11 may output sensing data generated internally (or preset to a specific value) to the data driver 12. The sensing data is for allowing a constant pixel current to flow through the pixels of the pixel line to be sensed during sensing driving. Sensing data to be written in the red, green, blue and white pixels may be different depending on the luminous efficiency of each pixel.

The timing controller 11 may change the phase between the scan shift clocks at a predetermined cycle so that the data driver generates less heat and the periodic bright / dark lines are less visible in the DRD scheme. On the contrary, the timing controller 11 sets the phase of the sense shift clocks irrespective of the phase change between the scan shift clocks, thereby ensuring the stability of the sensing operation.

The gate driver 13 may generate scan signals corresponding to scan shift clocks from the timing controller 11, and apply the scan signals to the gate lines GL. Each stage of the gate driver 13 may generate carry signals corresponding to carry shift clocks from the timing controller 11, and apply the carry signals to another stage. The gate driver 13 may further generate sense signals corresponding to sense shift clocks from the timing controller 11, and further apply the sense signals to the gate lines GL.

The gate driver 13 may be embedded in the non-display area NA of the display panel 10 according to the gate driver GIP. Clock lines connecting the timing controller 11 and the gate driver 13 may be further formed in the non-display area NA of the display panel 10. The clock wires may include scan shift clock wires for applying scan shift clocks from the timing controller 11 to the gate driver 13 and carry shift clock wires for applying the carry shift clocks. The clock wires may further include sense shift clock wires for applying the sense shift clocks from the timing controller 11 to the gate driver 13.

The non-display area NA becomes a bezel area in the display device. To reduce the bezel area, the number of carry shift clock wires may be set to half of the number of scan shift clock wires, and the number of sense shift clock wires may be set to half of the number of scan shift clock wires. For example, when 16 scan shift clock wires are implemented in consideration of input of 16 phase clocks, 8 carry shift clock wires and sense shift clock wires may be implemented in 8 considering input of 8 phase clocks. It doesn't work.

As will be described later, each stage constituting the gate driver 13 may include two scan pull-up elements for outputting two scan signals and one carry pull-up device for outputting one carry signal. In addition, each stage constituting the gate driver 13 may further include one sense pull-up device for outputting one sense signal. In each stage, two scan pull-up elements, one carry pull-up element and one sense pull-up element are connected to the same Q node and operated simultaneously according to the voltage of the Q node. Accordingly, 16 scan shift clocks are divided into two scan pull-up elements, 8 phase carry shift clocks are input to one carry pull-up device, and 8 phase sense shift clocks are input to one sense pull-up device. .

The data driver 12 may include a plurality of DACs and a plurality of sensing units. The DAC converts the input image data DATA into an image data voltage based on the data control signal DDC from the timing controller 11, and converts the sensing data into a sensing data voltage. The DAC then generates a reference voltage to be applied to the pixels.

The DAC may output image data voltages to the data lines DL in synchronization with the scan signal and output reference voltages to the reference lines RL in synchronization with the scan signal. Meanwhile, in order to implement display driving, the DAC may output an image data voltage to the data lines DL in synchronization with the scan signal, and output a reference voltage to the reference lines RL in synchronization with the sense signal. .

The DAC may output sensing data voltages to the data lines DL in synchronization with the scan signal and output reference voltages to the reference lines RL in synchronization with the scan signal. In this case, the sensing unit may sense current flowing through the pixels of the pixel line to be sensed through the reference lines RL in synchronization with the scan signal. Meanwhile, the DAC may output sensing data voltages to the data lines DL in synchronization with the scan signal and output reference voltages to the reference lines RL in synchronization with the sense signal in order to implement sensing driving. . In this case, the sensing unit may sense current flowing through the pixels of the pixel line to be sensed through the reference lines RL in synchronization with the sense signal.

2 and 3 are comparative examples corresponding to the present invention, which illustrate an example of a data writing order in a DRD scheme. 2 and 3, the pixels of the first color are shown as "PXL1", the pixels of the second color are shown as "PXL2", the pixels of the third color are shown as "PXL3", and the pixels of the fourth color. The pixels are shown as "PXL4". In addition, according to the DRD scheme, the pixels of the first color and the pixels of the second color share the first data line DL1, and the pixels of the third color and the pixels of the fourth color include the second data line DL2. ) Are sharing.

Referring to FIG. 2, data voltages are alternately written through the first data line DL1 to pixels of the first and second colors, and pixels of the third and fourth colors through the second data line DL2. Alternately, data voltages are written. In this case, the transition width of the different inter-color data voltages continuously output from the data driver 12 may increase, causing heat generation of the data driver 12. In addition, since the transition period of another inter-color data voltage continuously output from the data driver 12 becomes short, the state of charge of the data voltage becomes unstable in all pixels, and therefore, periodic bright lines / dark lines can be visually recognized in all pixels. have. In Fig. 2, the pixels marked with dashed lines represent color shifting pixels causing periodic bright / dark lines.

Referring to FIG. 3, the data driver 12 continuously outputs the same color data voltages in order to lengthen a transition period of different inter-color data voltages. That is, the data driver 12 continuously writes the data voltages for the first color to four pixels of the first color through the first data line DL1 and continuously writes the data voltages for four pixels of the second color. The data voltages for two colors are being written. Similarly, the data driver 12 continuously writes the data voltages for the third color to the four pixels of the third color through the second data line DL2 and continuously writes the fourth voltages to the four pixels of the fourth color. 4 color data voltages are written.

Since the data writing scheme of FIG. 3 is the same in all the frames, the positions of specific pixels (eg, pixels 2 and 5) that still change color are fixed. That is, in the data writing method of FIG. 3, since the color switching pixel positions (the positions of the pixels enclosed by the dotted lines in FIG. 3) where the data voltages are sequentially written four by four pixels of the same color are fixed, The state of charge of the data voltage becomes unstable at the pixel and the pixel 5, and thus the periodic bright line / dark line can be seen at the pixel 2 and the pixel 5.

Accordingly, in the present invention, in order to reduce heat generation of the data driver 12 and to make the periodic bright lines / dark lines less visible, the data drivers 12 have the same color data voltages n (n is a positive integer of 2 or more) successively. The color conversion pixel positions can be spatially dispersed by applying the data lines to each other by changing the order in which the data voltages are written into the pixels. The present invention effectively changes the color shift pixel positions by changing the phase between the scan shift clocks at a predetermined period in the timing controller 11 and changing the order in which data voltages are written into the pixels from frame to frame according to the phase change between the scan shift clocks. Can be dispersed. When the color shift pixel positions are spatially dispersed, the degree to which the color shift pixels are viewed as periodic bright lines / dark lines by the integration effect can be reduced. Hereinafter, embodiments of the present invention will be described with reference to FIGS. 4A to 4D and FIGS. 5A and 5B.

4A to 4D are diagrams illustrating an example of a data writing order in a DRD scheme according to an embodiment of the present invention.

4A to 4D, the data write method according to an exemplary embodiment of the present invention sequentially outputs four data voltages corresponding to the same color from the data driver 12, but writes the data voltages into pixels. Can be changed every frame.

As shown in FIG. 4A, after the data voltages for the first color are written in succession to the first and third pixels of the first color in the first frame, the second, fourth, sixth, and eighth pixels of the second color are successively written. After the data voltages for the second color are written, the data voltages for the first color may be successively written to pixels 5, 7, 9, and 11 of the first color. In addition, after the data voltages for the third color are written in succession to the first and third pixels of the third color in the first frame, the fourth color is continuously performed in the second, fourth, sixth and eighth pixels of the fourth color. After the data voltages have been written, the data voltages for the third color may be successively written to pixels 5, 7, 9, and 11 of the third color. In FIG. 4A, the color conversion pixel positions at which data voltages start to be written in succession four by four pixels of the same color are pixels 2 and 5.

As shown in FIG. 4B, after data voltages for the second color are written in succession to pixels 2 and 4 of the second color in the second frame, the pixels 1, 3, 5, and 7 of the first color are successively written. After the data voltages for the first color are written, the data voltages for the second color may be written in succession to pixels 6, 8, 10, and 12 of the second color. Further, after the data voltages for the fourth color are written in succession to the pixels 2, 4 of the fourth color in the second frame, the third color is continuously executed in the pixels 1, 3, 5, and 7 of the third color. After the data voltages have been written, the data voltages for the fourth color may be successively written to the pixels 6, 8, 10, and 12 of the fourth color. In FIG. 4B, the color conversion pixel positions at which data voltages are sequentially written four by four pixels of the same color become pixels one and six.

As shown in FIG. 4C, after the data voltage for the second color is written in the second pixel of the second color in the third frame, the data voltages for the first color are continuously applied to the pixels 1, 3, and 5 of the first color. After writing, data voltages for the second color are written in succession to pixels 4, 6, 8, and 10 of the second color, and then sequentially written to pixels 7,9, 11, and 13 of the first color. Data voltages for one color can be written. In addition, after the data voltage for the fourth color is written in the second pixel of the fourth color in the third frame, the data voltages for the third color are sequentially written to the pixels 1, 3, and 5 of the third color. After the data voltages for the fourth color are written in succession to the pixels 4, 6, 8, and 10 of the fourth color, the pixels for the third color are continuously executed in the pixels 7,9, 11, and 13 of the third color. Data voltages can be written. In FIG. 4C, the color conversion pixel positions at which data voltages are sequentially written four by four pixels of the same color are four pixels and seven pixels.

As shown in FIG. 4D, after the data voltage for the first color is written in the first pixel of the first color in the fourth frame, the data voltages for the second color are sequentially applied to the pixels 2, 4, and 6 of the second color. After writing, data voltages for the first color are written in succession to pixels 3, 5, 7, and 9 of the first color, and then sequentially written to pixels 8, 10, 12, and 14 of the second color. Data voltages for two colors can be written. In addition, after the data voltage for the third color is written to the first pixel of the third color in the fourth frame, the data voltages for the fourth color are sequentially written to the pixels 2, 4, and 6 of the fourth color. After the data voltages for the third color are written in succession to the pixels 3, 5, 7, and 9 of the third color, the pixels for the fourth color are continuously applied to the pixels 8, 10, 12, and 14 of the fourth color. Data voltages can be written. In FIG. 4D, the color conversion pixel positions at which data voltages are sequentially written four by four pixels of the same color are pixels 3 and 8.

In the data writing method according to the exemplary embodiment of the present invention, the order of changing the data voltage writing order is repeated every four frames. For example, the fifth to eighth frames may be repeated in the same manner as the first to fourth frames. According to the data writing scheme according to the embodiment of the present invention, the color conversion pixel positions are evenly distributed to all pixels through 4 frames.

5A and 5B are diagrams illustrating an example of a data writing order in a DRD scheme according to another embodiment of the present invention.

5A and 5B, in the data write method according to another exemplary embodiment, the data driver 12 sequentially outputs two data voltages corresponding to the same color, but writes the data voltages into pixels. Can be changed every frame.

As shown in FIG. 5A, after the data voltage for the first color is written in the first pixel of the first color in the first frame, the data voltages for the second color are successively written in the pixels 2 and 4 of the second color. After the data voltages for the first color are written in succession to the pixels 3 and 5 of the first color, and after the data voltages for the second color are continuously written to the pixels 6 and 8 of the second color, The data voltages for the first color may be written in succession to pixels 7,9 of the first color.

Further, after the data voltage for the third color is written to the first pixel of the third color in the first frame, the data voltages for the fourth color are sequentially written to the pixels 2 and 4 of the fourth color. After the data voltages for the third color are written in succession to the pixels 3 and 5 of three colors, the data voltages for the fourth color are sequentially written to the pixels 6 and 8 in the fourth color, and then the third color. The data voltages for the third color may be written in succession to pixels 7,9 of.

In FIG. 5A, the color shift pixel positions at which data voltages start to be written in succession two by two pixels of the same color are pixels 2, 3, 6, and 7.

As shown in FIG. 5B, after the data voltage for the second color is written to the second pixel of the second color in the second frame, the data voltages for the first color are sequentially written to the pixels 1 and 3 of the first color. After the second color data voltages are written in succession to pixels 4 and 6 of the second color, the first color data voltages are written in succession to the pixels 5 and 7 of the first color. Data voltages for the second color may be written in succession to pixels 8 and 10 of the second color.

In addition, after the fourth color data voltage is written to the second pixel of the fourth color in the second frame, the third color data voltages are sequentially written to the first and third pixels of the third color. After the data voltages for the fourth color are written in succession to pixels 4 and 6 of four colors, the data voltages for the third color are sequentially written into pixels 5 and 7 in the third color, and then the fourth color. The data voltages for the fourth color can be written in succession to pixels 8 and 10 of the pixel.

In FIG. 5B, the color conversion pixel positions at which data voltages start to be written in succession two by one with pixels of the same color are pixels 1, 4, 5, and 8.

In the data writing method according to another embodiment of the present invention, the order of changing the data voltage writing order is repeated in every two frame periods. For example, the third and fourth frames may be repeated in the same manner as the first and second frames. According to a data writing scheme according to another embodiment of the present invention, the color conversion pixel positions are evenly distributed to all pixels through two frames.

FIG. 6 is a diagram illustrating an example of the pixel array illustrated in FIG. 1.

Referring to FIG. 6, a pixel array according to an embodiment of the present invention may be implemented with a single scan connection structure connected to one gate line for each pixel. The one scan connection structure has the advantage of widening the opening area of the pixel array. In this case, two gate lines GL1 and GL2 or GL3 and GL4 for the DRD method may be allocated to each pixel line PL # 1 and PL # 2. On each pixel line PL # 1 and PL # 2, the pixels PXL1 of the first color and the pixels PXL2 of the second color share the first data line DL1 and have different gate lines. The third color pixels PXL3 and the fourth color pixels PXL4 share the second data line DL2 and are connected to different gate lines.

In the first pixel line PL # 1, the pixels PXL1 of the first color and the pixels PXL3 of the third color are connected to the first gate line GL1 and from the first gate line GL1. The data write operation and the sensing operation may be performed in response to the first scan signal S1 of FIG. In the first pixel line PL # 1, the pixels PXL2 of the second color and the pixels PXL4 of the fourth color are connected to the second gate line GL2 and from the second gate line GL2. The data writing operation and the sensing operation may be performed in response to the second scan signal S2 of FIG.

In the second pixel line PL # 2, the pixels PXL1 of the first color and the pixels PXL3 of the third color are connected to the third gate line GL3 and from the third gate line GL3. The data writing operation and the sensing operation may be performed in response to the third scan signal S3 of FIG. In the second pixel line PL # 2, the pixels PXL2 of the second color and the pixels PXL4 of the fourth color are connected to the fourth gate line GL4, and from the fourth gate line GL4. The data writing operation and the sensing operation may be performed in response to the fourth scan signal S4 of FIG.

In the first and second pixel lines PL # 1 and PL # 2, the pixels PXL1 to PXL4 of the first to fourth colors may share the reference voltage line RL. The reference voltage line RL may also be used as a path through which the reference voltage Vref is introduced and may also be used as a path through which a sensing voltage (or sensing current) is drawn. For this purpose, the reference voltage line RL may be selectively connected to the DAC and the sensing unit through a switch. As such, when the structure in which the plurality of pixels share the reference voltage line RL is selected, the pixel array is simplified and the number of channels of the data driver is reduced.

The first color data voltage Vdata1 and the second color data voltage Vdata2 are applied to the first data line DL1, and the third color data voltage Vdata3 and the second color data voltage Vdata2 are applied to the second data line DL2. Four-color data voltage Vdata4 may be applied.

The pixels PXL1 of the first color include an OLED emitting light of the first color, and the pixels PXL2 of the second color include OLED emitting light of the second color. The pixels PXL3 of the third color include an OLED emitting light of the third color, and the pixels PXL4 of the fourth color include OLED emitting light of the fourth color.

Each of the pixels PXL1 to PXL4 of the first to fourth colors may have a driving thin film transistor (DT), a storage capacitor (CST), a first switch TFT (ST1), and a second switch TFT (in addition to an OLED). ST2) may be further included. In this case, the first switch TFT ST1 and the second switch TFT ST2 may be connected to the same gate line.

The OLED includes an anode electrode connected to the source node Ns, a cathode electrode connected to the input terminal of the low potential pixel power supply VSS, and an organic compound layer positioned between the anode electrode and the cathode electrode. The driving TFT DT controls the driving current flowing through the OLED according to the voltage difference between the gate node Ng and the source node Ns. The driving TFT DT includes a gate electrode connected to the gate node Ng, a first electrode connected to the input terminal of the high potential pixel power supply VDD, and a second electrode connected to the source node Ns. The storage capacitor CST is connected between the gate node Ng and the source node Ns to store the gate-source voltage of the driving TFT DT.

The first switch TFT ST1 turns on the current flow between the data line and the gate node Ng according to the scan signal, and applies the data voltage charged in the data line to the gate node Ng. The first switch TFT ST1 has a gate electrode connected to the gate line, a first electrode connected to the data line, and a second electrode connected to the gate node Ng. The second switch TFT ST2 turns on the current flow between the reference voltage line RL and the source node Ns according to the scan signal, and supplies the reference voltage charged in the reference voltage line RL to the source node Ns. Or the source node Ns voltage change according to the pixel current is transferred to the reference voltage line RL. The second switch TFT ST2 has a gate electrode connected to the gate line, a first electrode connected to the reference voltage line RL, and a second electrode connected to the source node Ns.

FIG. 7 is a diagram illustrating a connection structure between stages constituting the gate driver of FIG. 1 and clock wires. The gate driver of FIG. 7 generates a scan signal applied to pixels of the one scan connection structure of FIG. 6.

Referring to FIG. 7, the gate driver may be implemented as a gate shift register including a plurality of stages STG1 to STG8. Each of the stages STG1 to STG8 includes a Q node, a plurality of pull-up elements turned on / off according to the voltage of the Q node, a Qb node, and a plurality of pull-down elements turned on / off according to the voltage of the Qb node. can do. The plurality of pullup elements include one carry pullup element and two scan pullup elements. Accordingly, each of the stages STG1 to STG8 includes one carry pull-up element T31 for outputting one carry signal (eg, C1) and two outputs for two scan signals (eg, S1 and S2). The scan pull-up elements T32 and T33 may be included. In each of the stages STG1 to STG8, since the gate electrodes of the carry pull-up element T31 and the scan pull-up elements T32 and T33 are connected to the same Q node, the stage configuration can be simplified.

One of eight phase carry shift clocks CRCLK1 to CRCLK8 may be input to one electrode of the carry pull-up element T31. On one electrode of the first scan pull-up element T32, any one of the scan shift clocks SCCLK1, 3, 5, 7, 9, 11, 13, and 15 of the first group of the 16-phase scan shift clocks SCCLK1 to SCCLK16 is formed. One can be input. In addition, a second group of scan shift clocks SCCLK2, 4, 6, 8, 10, 12, 14, and 16 of the 16-phase scan shift clocks SCCLK1 to SCCLK16 may be provided at one electrode of the second scan pull-up element T33. Any one may be input.

The other electrode of the carry pull-up element T31 is connected to a carry output node NO1 to which a carry signal is output. The carry output node NO1 may be connected to a start terminal or a reset terminal of another stage.

The other electrode of the first scan pull-up element T32 is connected to the first scan output node NO2 to which the first scan signal is output. The first scan output node NO2 is connected to the pixel of the first color through the first gate line.

The other electrode of the second scan pull-up element T33 is connected to the second scan output node NO3 to which the second scan signal is output. The second scan output node NO3 is connected to the pixel of the second color through the second gate line. Here, the pixel of the second color shares the data line with the pixel of the first color.

The gate electrodes of the pull-down devices T41, T42, and T43 are commonly connected to the Qb node, and one electrode of the pull-down devices T41, T42, and T43 is connected to the output nodes NO1 to NO3, respectively. The other electrodes of the pull-down elements T41, T42, and T43 may be connected to the low potential driving power source GVSS. The pull-down elements T41, T42, and T43 serve to stabilize the carry signal and the scan signals.

FIG. 8 is a view illustrating an nth stage among stages configuring the gate driver of FIG. 7.

Referring to FIG. 8, the n-th stage of the gate driver according to the present invention includes an input & reset unit BLK1, an inverter unit BLK2, an output unit BLK3, a stabilizer BLK4, and a line selector / release unit ( BLK5).

The input & reset unit BLK1 charges the Q node to the on voltage according to the front carry signal CR (n-4) and discharges the Q node to the off voltage according to the rear carry signal CR (n + 4). do. The input & reset unit BLK1 supplies the Q node with a low potential power supply voltage according to the transistor T11 which charges the front carry signal CR (n-4) to the Q node and the rear carry signal CR (n + 4). Transistor T12 that discharges to GVSS (i.e., off voltage). The front carry signal CR (n-4) is input to the gate electrode and the first electrode of the transistor T11, and the second electrode of the transistor T11 is connected to the Q node. The rear carry signal CR (n + 4) is input to the gate electrode of the transistor T12, the first electrode of the transistor T12 is connected to the Q node, and the low potential power supply voltage GVSS is input to the second electrode of the transistor T12. do.

The inverter part BLK2 charges / discharges the voltage of the Qb node opposite to the Q node according to the voltage of the Q node. The inverter section BLK2 is configured to supply a transistor T24 which discharges the Qb node to the low potential power voltage GVSS (that is, the off voltage) when the Q node is charged to the on voltage, and the Qb node when the Q node is discharged to the off voltage. Transistors T21 to T23 that charge to the high potential power voltage GVDD (that is, on voltage) and transistors that discharge the Q node to the low potential power voltage GVSS according to the front carry signal CR (n-4). T25. The gate electrode of the transistor T21 is connected to the node N1, the high potential power supply voltage GVDD is input to the first electrode of the transistor T21, and the second electrode of the transistor T21 is connected to the Qb node. The high potential power supply voltage GVDD is input to the gate electrode and the first electrode of the transistor T22, and the second electrode of the transistor T22 is connected to the N1 node. The gate electrode of the transistor T23 is connected to the Q node, the first electrode of the transistor T23 is connected to the N1 node, and the low potential power supply voltage GVSS is input to the second electrode of the transistor T23. The gate electrode of the transistor T24 is connected to the Q node, the first electrode of the transistor T24 is connected to the Qb node, and the low potential power supply voltage GVSS is input to the second electrode of the transistor T24. The front carry signal CR (n-4) is input to the gate electrode of the transistor T25, the first electrode of the transistor T25 is connected to the Qb node, and the low potential power voltage GVSS is input to the second electrode of the transistor T25. do.

The output part BLK3 includes a pull-up element T31 that outputs a carry shift clock CRCLK (n) as a carry signal C (n) while the Q node is bootstrapping to a voltage higher than an on voltage. A pull-up element T32 that outputs the first group scan shift clock SCCLK (2n-1) as the first scan signal S (2n-1) and a second group scan shift clock SCCLK (2n). And a pull-up element T33 that outputs the second scan signal S (2n). The gate electrode of the pull-up element T31 is connected to the Q node, and the carry shift clock CRCLK (n) is input to the first electrode of the pull-up element T31, and the second electrode of the pull-up element T31 is connected to the carry output node NO1. do. The gate electrode of the pull-up element T32 is connected to the Q node, a first group of scan shift clocks SCCLK (2n-1) are input to the first electrode of the pull-up element T32, and the second electrode of the pull-up element T32 is connected to the first node. It is connected to the scan output node NO2. The gate electrode of the pull-up element T33 is connected to the Q node, a second group of scan shift clocks SCCLK (2n) are input to the first electrode of the pull-up element T33, and the second electrode of the pull-up element T33 is a second scan output. It is connected to node NO3. The booster capacitor CY may be further connected between the gate electrode of the pull-up element T32 and the first scan output node NO2, and the booster capacitor CZ is further connected between the gate electrode of the pull-up element T33 and the second scan output node NO3. Can be. The booster capacitors CY and CZ serve to help bootstrap the Q node when the first and second groups of scan shift clocks are input.

The stabilizer BLK4 includes pull-down transistors T41 to T43 that suppress the ripple of the output nodes NO1 to NO3 while the Qb node is charged, and a transistor T44 that suppresses the ripple of the Q node. Gate electrodes of the pull-down transistors T41 to T43 are connected to the Qb node, and a low potential power voltage GVSS is input to the second electrodes of the pull-down transistors T41 to T43. The first electrode of the pull-down transistor T41 is connected to the carry output node NO1, the first electrode of the pull-down transistor T42 is connected to the first scan output node NO2, and the first electrode of the pull-down transistor T43 is the second scan output. It is connected to node NO3. The gate electrode of the transistor T44 is connected to the Qb node, the first electrode of the transistor T44 is connected to the Q node, and the low potential power supply voltage GVSS is input to the second electrode of the transistor T44.

The line selection and release unit BLK5 charges the M node with the front carry signal CR (n-2) according to the pixel line selection and release signal LSP, and the M node according to the sensing start timing indication signal RESET. Charge the Q node with the charging voltage of. The line select & release section BLK5 includes a transistor T51 for charging the M node with the front carry signal CR (n-2) according to the pixel line select & release signal LSP, and a capacitor for maintaining the charge voltage of the M node. CX, transistors T52 that operate according to the voltage of the M node, and transistor T53 that charges the Q node with the charging voltage of the M node according to the sensing start timing indication signal RESET. The pixel line select & release signal LSP is input to the gate electrode of the transistor T51, the front end carry signal CR (n-2) is input to the first electrode of the transistor T51, and the second electrode of the transistor T51 is an M node. Is connected to. The gate electrode of the transistor T52 is connected to the M node, a high potential power supply voltage GVDD is input to the first electrode of the transistor T52, and the second electrode of the transistor T52 is connected to the first electrode of the transistor T53. The sensing start timing instruction signal RESET is input to the gate electrode of the transistor T53, and the second electrode of the transistor T53 is connected to the Q node.

9A through 9D are gate shift clocks applied to the gate driver of FIG. 7 and show operation timings of gate shift clocks for implementing the data write order of FIGS. 4A through 4D.

As shown in Figs. 9A to 9D, the timing controller sets the phase of the scan shift clocks so that the data voltage is continuously applied to the pixels of the same color, but with a period of 4 frames so that the color shift pixel positions are not fixed but dispersed. Change the phase of the scan shift clocks every frame. On the other hand, the timing controller can secure the stability of the operation by fixing the phase of the carry shift clocks irrelevant to the data write operation irrespective of the phase change between the scan shift clocks. That is, the timing controller may set the phases of the carry shift clocks in the order of carry shift clocks 1 to 8 in all frames.

Referring to FIG. 9A, the timing controller sets the phases of the scan shift clocks in the first frame in the order of the scan shift clocks 1, 3, 2, 4, 6, 8, 5, 7, 9, and 11.

As a result, the first color data voltages V1 and V3 are sequentially written to the first and third pixels of the first color in synchronization with the scan shift clocks 1 and 3 in the first frame. Subsequently, in synchronization with the scan shift clocks 2, 4, 6, and 8, the data voltages V2, V4, V6, and V8 for the second color are continuously connected to the pixels 2, 4, 6, and 8 of the second color. Is filled out. Subsequently, in synchronization with the scan shift clocks 5, 7, 9, and 11, the data voltages V5, V7, V9, and V11 for the first color are continuously connected to the pixels 5, 7, 9, 11 of the first color. Can be written.

Similarly, the third color data voltages V1 and V3 are sequentially written to the first and third pixels of the third color in synchronization with the scan shift clocks 1 and 3 in the first frame. Subsequently, in synchronization with the scan shift clocks 2, 4, 6, and 8, the data voltages V2, V4, V6, and V8 for the fourth color are continuously connected to pixels 2, 4, 6, and 8 of the fourth color. Is filled out. Subsequently, in synchronization with the scan shift clocks 5, 7, 9, and 11, the data voltages V5, V7, V9, and V11 for the third color are continuously applied to pixels 5, 7, 9, and 11 of the third color. Can be written.

Referring to FIG. 9B, the timing controller changes the phase of the scan shift clocks differently from the first frame in the second frame. That is, the timing controller sets the phases of the scan shift clocks in the second frame in the order of the scan shift clocks 2, 4, 1, 3, 5, 7, 6, 8, 10, and 12.

As a result, the second color data voltages V2 and V4 are successively written to pixels 2 and 4 of the second color in synchronization with the scan shift clocks 2 and 4 in the second frame. Subsequently, in synchronization with the scan shift clocks 1, 3, 5, and 7, the data voltages V 1, V 3, V 5, and V 7 for the first color are continuously connected to the pixels 1, 3, 5, and 7 of the first color. Is filled out. Subsequently, in synchronization with the scan shift clocks 6, 8, 10, and 12, the data voltages V6, V8, V10, and V12 for the second color are continuously connected to the pixels 6, 8, 10, and 12 of the second color. Can be written.

Similarly, in the second frame, the fourth color data voltages V2 and V4 are sequentially written to pixels 2 and 4 of the fourth color in synchronization with the scan shift clocks 2 and 4. Subsequently, in synchronization with the scan shift clocks 1, 3, 5, and 7, the data voltages V 1, V 3, V 5, and V 7 for the third color are continuously connected to the pixels 1, 3, 5, and 7 of the third color. Is filled out. Subsequently, in synchronization with the scan shift clocks 6, 8, 10, and 12, the data voltages V6, V8, V10, and V12 for the fourth color are continuously applied to the pixels 6, 8, 10, and 12 of the fourth color. Can be written.

Referring to FIG. 9C, the timing controller changes the phase of the scan shift clocks differently from the second frame in the third frame. That is, the timing controller sets the phases of the scan shift clocks in the third frame in the order of the scan shift clocks 2, 1, 3, 5, 4, 6, 8, 10, 7, 9, 11, and 13.

As a result, the second color data voltage V2 is written to the second pixel of the second color in synchronization with the scan shift clock 2 in the third frame. Subsequently, in synchronization with the scan shift clocks 1, 3, and 5, the data voltages V 1, V 3, and V 5 for the first color are successively written to the pixels 1, 3, and 5 of the first color. Subsequently, in synchronization with the scan shift clocks 4, 6, 8, and 10, the data voltages V4, V6, V8, and V10 for the second color are continuously connected to the pixels 4, 6, 8, and 10 of the second color. Can be written. Subsequently, in synchronization with the scan shift clocks 7,9, 11, and 13, the data voltages V7, V9, V11, and V13 for the first color are continuously connected to the pixels 7,9, 11, and 13 of the first color. Can be written.

Similarly, the fourth color data voltage V2 is written to the second pixel of the fourth color in synchronization with the scan shift clock 2 in the third frame. Subsequently, the third color data voltages V1, V3, and V5 are sequentially written to the pixels 1, 3, and 5 of the third color in synchronization with the scan shift clocks 1, 3, and 5. Subsequently, in synchronization with the scan shift clocks 4, 6, 8, and 10, the data voltages V4, V6, V8, and V10 for the fourth color are continuously applied to the pixels 4, 6, 8, and 10 of the fourth color. Can be written. Subsequently, the third color data voltages V7, V9, V11, and V13 are sequentially connected to the pixels 7,9, 11, and 13 of the third color in synchronization with the scan shift clocks 7,9, 11, and 13. Can be written.

9D, the timing controller changes the phase of the scan shift clocks differently from the third frame in the fourth frame. That is, the timing controller sets the phases of the scan shift clocks in the fourth frame in the order of the scan shift clocks 1,2,4,6,3,5,7,9,8,10,12,14.

As a result, the first color data voltage V1 is written to the first pixel of the first color in synchronization with the scan shift clock 1 in the fourth frame. Subsequently, in synchronization with the scan shift clocks 2, 4 and 6, the data voltages V2, V4 and V6 for the second color are successively written to the pixels 2, 4 and 6 of the second color. Subsequently, in synchronization with the scan shift clocks 3, 5, 7, and 9, the data voltages V3, V5, V7, and V9 for the first color are continuously connected to the pixels 3, 5, 7, and 9 of the first color. Can be written. Subsequently, in synchronization with the scan shift clocks 8, 10, 12 and 14, the data voltages V8, V10, V12, and V14 for the second color are continuously connected to the pixels 8, 10, 12 and 14 of the second color. Can be written.

Similarly, in the fourth frame, the third color data voltage V1 is written to the first pixel of the third color in synchronization with the scan shift clock 1. Subsequently, in synchronization with the scan shift clocks 2, 4 and 6, the data voltages V2, V4 and V6 for the fourth color are successively written to the pixels 2, 4 and 6 of the fourth color. Subsequently, in synchronization with the scan shift clocks 3, 5, 7, and 9, the data voltages V3, V5, V7, and V9 for the third color are continuously connected to the pixels 3, 5, 7, and 9 of the third color. Can be written. Subsequently, in synchronization with the scan shift clocks 8, 10, 12, and 14, the data voltages V8, V10, V12, and V14 for the fourth color are continuously applied to the pixels 8, 10, 12, and 14 of the fourth color. Can be written.

10A and 10B are gate shift clocks applied to the gate driver of FIG. 7 and show operation timings of gate shift clocks for implementing the data write order of FIGS. 5A and 5B.

As shown in Figs. 10A and 10B, the timing controller sets the phases of the scan shift clocks so that data voltages are continuously applied to the pixels of the same color, but with two frame periods so that the color shift pixel positions are not fixed but dispersed. Change the phase of the scan shift clocks every frame. On the other hand, the timing controller can secure the stability of the operation by fixing the phase of the carry shift clocks irrelevant to the data write operation irrespective of the phase change between the scan shift clocks.

Referring to FIG. 10A, the timing controller sets the phases of the scan shift clocks in the first frame in the order of the scan shift clocks 1,2,4,3,5,6,8,7,9.

As a result, the first color data voltage V1 is written to the first pixel of the first color in synchronization with the scan shift clock 1 in the first frame. Subsequently, the second color data voltages V2 and V4 are sequentially written to the pixels 2 and 4 of the second color in synchronization with the scan shift clocks 2 and 4. Subsequently, the first color data voltages V3 and V5 are sequentially written to the pixels 3 and 5 of the first color in synchronization with the scan shift clocks 3 and 5. Subsequently, the second color data voltages V6 and V8 are sequentially written to the pixels 6 and 8 of the second color in synchronization with the scan shift clocks 6 and 8. Subsequently, the first color data voltages V7 and V9 are sequentially written to the pixels 7,9 of the first color in synchronization with the scan shift clocks 7,9.

Similarly, the third color data voltage V1 is written to the first pixel of the third color in synchronization with the scan shift clock 1 in the first frame. Subsequently, the fourth color data voltages V2 and V4 are sequentially written to the pixels 2 and 4 of the fourth color in synchronization with the scan shift clocks 2 and 4. Subsequently, the third color data voltages V3 and V5 are sequentially written to the pixels 3 and 5 of the third color in synchronization with the scan shift clocks 3 and 5. Subsequently, the fourth color data voltages V6 and V8 are sequentially written to the pixels 6 and 8 of the fourth color in synchronization with the scan shift clocks 6 and 8. Subsequently, the third color data voltages V7 and V9 are sequentially written to the seventh and seventh pixels of the third color in synchronization with the scan shift clocks 7,9.

Referring to FIG. 10B, the timing controller changes the phase of the scan shift clocks differently from the first frame in the second frame. That is, the timing controller sets the phases of the scan shift clocks in the second frame in the order of the scan shift clocks 2, 1, 3, 4, 6, 5, 7, 8, and 10.

As a result, the second color data voltage V2 is written in the second pixel of the second color in synchronization with the scan shift clock 2 in the second frame. Subsequently, the first color data voltages V1 and V3 are sequentially written to the first and third pixels of the first color in synchronization with the scan shift clocks 1 and 3. Subsequently, the second color data voltages V4 and V6 may be sequentially written to the pixels 4 and 6 of the second color in synchronization with the scan shift clocks 4 and 6. Subsequently, the first color data voltages V5 and V7 are sequentially written to pixels 5 and 7 of the first color in synchronization with the scan shift clocks 5 and 7. Subsequently, the second color data voltages V8 and V10 may be sequentially written to the pixels 8 and 10 of the second color in synchronization with the scan shift clocks 8 and 10.

FIG. 11 is a diagram illustrating another example of the pixel array illustrated in FIG. 1.

Referring to FIG. 11, a pixel array according to another embodiment of the present invention may be implemented with a two scan connection structure connected to two gate lines for each pixel. The two-scan connection structure has the advantage that the load on the gate line is distributed, thereby increasing accuracy in data writing and sensing. In this case, each of the pixel lines PL # 1 and PL # 2 is allocated two gate lines GL1 and GL2 or GL4 and GL5 for the DRD method, and an additional gate line for the two scan connection structure ( GL3 or GL6) can be allocated further. On each pixel line PL # 1 and PL # 2, the pixels PXL1 of the first color and the pixels PXL2 of the second color share the first data line DL1 and have different gate lines. The third color pixels PXL3 and the fourth color pixels PXL4 share the second data line DL2 and are connected to different gate lines.

In the first pixel line PL # 1, the pixels PXL1 of the first color and the pixels PXL3 of the third color are connected to the first and third gate lines GL1 and GL3 and the first gate. The data write operation is performed in response to the first scan signal S1 from the line GL1, and the sensing operation is performed in response to the first sense signal SE (1-2) from the third gate line GL3. Can be done. Also, in the first pixel line PL # 1, the pixels PXL2 of the second color and the pixels PXL4 of the fourth color are connected to the second and third gate lines GL2 and GL3. The data write operation is performed in response to the second scan signal S2 from the second gate line GL2, and is sensed in response to the first sense signal SE (1-2) from the third gate line GL3. You can perform the operation.

In the second pixel line PL # 2, the pixels PXL1 of the first color and the pixels PXL3 of the third color are connected to the fourth and sixth gate lines GL4 and GL6 and the fourth gate. The data write operation is performed in response to the third scan signal S3 from the line GL1, and the sensing operation is performed in response to the second sense signal SE 3-4 from the sixth gate line GL6. Can be done. In addition, in the second pixel line PL # 2, the pixels PXL2 of the second color and the pixels PXL4 of the fourth color are connected to the fifth and sixth gate lines GL5 and GL6. A data write operation is performed in response to the fourth scan signal S4 from the fifth gate line GL5, and sensing is performed in response to the second sense signal SE 3-4 from the sixth gate line GL6. You can perform the operation.

The pixel configuration according to the two scan connection structure is substantially the same as the pixel configuration according to the one scan connection structure, except that the first and second switch TFTs ST1 and ST2 are connected to different gate lines.

FIG. 12 is a diagram illustrating another connection configuration between the stages and the clock wires configuring the gate driver of FIG. 1. The gate driver of FIG. 12 generates a scan signal and a sense signal applied to pixels of the two scan connection structure of FIG. 11.

Referring to FIG. 12, the gate driver may be implemented as a gate shift register including a plurality of stages STG1 to STG8. Each of the stages STG1 to STG8 includes a Q node, a plurality of pull-up elements turned on / off according to the voltage of the Q node, a Qb node, and a plurality of pull-down elements turned on / off according to the voltage of the Qb node. can do. The plurality of pullup elements includes one carry pullup element, two scan pullup elements, and one sense pullup element. Accordingly, each of the stages STG1 to STG8 includes one carry pull-up element T31 for outputting one carry signal (eg, C1) and two outputs for two scan signals (eg, S1 and S2). The scan pull-up elements T32 and T33 and one sense pull-up element T34 for outputting one sense signal (eg, SE (1-2)) may be included. In each of the stages STG1 to STG8, the gate electrodes of the carry pull-up element T31, the scan pull-up elements T32 and T33, and the sense pull-up element T34 are connected to the same Q node, thereby simplifying the stage configuration. It is advantageous to reduce the bezel.

One of eight phase carry shift clocks CRCLK1 to CRCLK8 may be input to one electrode of the carry pull-up element T31. On one electrode of the first scan pull-up element T32, any one of the scan shift clocks SCCLK1, 3, 5, 7, 9, 11, 13, and 15 of the first group of the 16-phase scan shift clocks SCCLK1 to SCCLK16 is formed. One can be input. One electrode of the second scan pull-up element T33 may have any one of the scan shift clocks SCCLK2, 4, 6, 8, 10, 12, 14, and 16 of the 16-phase scan shift clocks SCCLK1 to SCCLK16. One can be input. One of the eight phase sense shift clocks SECLK1 to SECLK8 may be input to one electrode of the sense pull-up element T34.

The other electrode of the carry pull-up element T31 is connected to a carry output node NO1 to which a carry signal is output. The carry output node NO1 may be connected to a start terminal or a reset terminal of another stage.

The other electrode of the first scan pull-up element T32 is connected to the first scan output node NO2 to which the first scan signal is output. The first scan output node NO2 is connected to the pixel of the first color through the first gate line.

The other electrode of the second scan pull-up element T33 is connected to the second scan output node NO3 to which the second scan signal is output. The second scan output node NO3 is connected to the pixel of the second color through the second gate line. Here, the pixel of the second color shares the data line with the pixel of the first color.

The other electrode of the sense pull-up element T34 is connected to the sense output node NO4 to which the sense signal is output. The sense output node NO4 is connected to the pixels of the first and second colors through the third gate line.

Meanwhile, gate electrodes of the pull-down devices T41, T42, T43, and T44 ′ are commonly connected to the Qb node, and one electrodes of the pull-down devices T41, T42, T43, and T44 ′ are output nodes NO1 ˜. Each of the other electrodes of the pull-down devices T41, T42, T43, and T44 ′ may be connected to the low potential driving power source GVSS. The pull-down elements T41, T42, T43, and T44 ′ serve to stabilize the carry signal, the scan signals, and the sense signal.

FIG. 13 is a view illustrating an nth stage among stages configuring the gate driver of FIG. 12.

Referring to FIG. 13, the n-th stage of the gate driver according to the present invention includes an input & reset unit BLK1, an inverter unit BLK2, an output unit BLK3 ′, a stabilizer BLK4 ′, and a line selection & release. It may include a portion BLK5.

The input & reset section BLK1, the inverter section BLK2, and the line select & release section BLK5 are substantially the same as those described with reference to FIG.

The output part BLK3 'is a pull-up element T31 that outputs a carry shift clock CRCLK (n) as a carry signal C (n) while the Q node is bootstrapping to a voltage higher than the on voltage. A pull-up element T32 that outputs the first group scan shift clock SCCLK (2n-1) as the first scan signal S (2n-1), and the second group scan shift clock SCCLK (2n). A pull-up element T33 for outputting a second scan signal S (2n) and a pull-up element T34 for outputting a sense shift clock SECLK (n) as a sense signal SE (2n-1 to 2n). . The gate electrode of the pull-up element T31 is connected to the Q node, and the carry shift clock CRCLK (n) is input to the first electrode of the pull-up element T31, and the second electrode of the pull-up element T31 is connected to the carry output node NO1. do. The gate electrode of the pull-up element T32 is connected to the Q node, a first group of scan shift clocks SCCLK (2n-1) are input to the first electrode of the pull-up element T32, and the second electrode of the pull-up element T32 is connected to the first node. It is connected to the scan output node NO2. The gate electrode of the pull-up element T33 is connected to the Q node, a second group of scan shift clocks SCCLK (2n) are input to the first electrode of the pull-up element T33, and the second electrode of the pull-up element T33 is a second scan output. It is connected to node NO3. The gate electrode of the pull-up element T34 is connected to the Q node, a sense shift clock (SECLK (2n)) is input to the first electrode of the pull-up element T34, and the second electrode of the pull-up element T34 is connected to the sense output node NO4. do.

The booster capacitor CY may be further connected between the gate electrode of the pull-up element T32 and the first scan output node NO2, and the booster capacitor CZ is further connected between the gate electrode of the pull-up element T33 and the second scan output node NO3. Can be. The booster capacitors CY and CZ serve to help bootstrap the Q node when the first and second groups of scan shift clocks are input.

The stabilizer BLK4 'includes pull-down transistors T41 to T44' that suppress the ripple of the output nodes NO1 to NO4 while the Qb node is charged, and a transistor T44 that suppresses the ripple of the Q node. The gate electrodes of the pull-down transistors T41 to T44 'are connected to the Qb node, and the low potential power supply voltage GVSS is input to the second electrodes of the pull-down transistors T41 to T44'. The first electrode of the pull-down transistor T41 is connected to the carry output node NO1, the first electrode of the pull-down transistor T42 is connected to the first scan output node NO2, and the first electrode of the pull-down transistor T43 is the second scan output. It is connected to the node NO3, and the first electrode of the pull-down transistor T44 'is connected to the sense output node NO4. The gate electrode of the transistor T44 is connected to the Qb node, the first electrode of the transistor T44 is connected to the Q node, and the low potential power supply voltage GVSS is input to the second electrode of the transistor T44.

14A through 14D are gate shift clocks applied to the gate driver of FIG. 12 and illustrate operation timings of gate shift clocks for implementing the data write order of FIGS. 4A through 4D.

As shown in Figs. 14A to 14D, the timing controller sets the phases of the scan shift clocks so that data voltages are continuously applied to the pixels of the same color, with a period of 4 frames so that the color shift pixel positions are not fixed but dispersed. The phase of the scan shift clocks is changed every frame. On the other hand, the timing controller can secure the stability of the operation by fixing the phase of the carry shift clocks and sense shift clocks irrelevant to the data write operation irrespective of the phase change between the scan shift clocks. That is, the timing controller sets the phases of the carry shift clocks in the order of the carry shift clocks 1 through 8 in all the frames, and also sets the phases of the sense shift clocks in the order of the sensing shift clocks 1 through 8 in all the frames. have.

The phase change of the scan shift clocks shown in FIGS. 14A through 14D and the write operation of the data voltages according to the present invention are substantially the same as those described with reference to FIGS. 9A through 9D.

15A and 15B are gate shift clocks applied to the gate driver of FIG. 12 and illustrate operation timings of gate shift clocks for implementing the data writing order of FIGS. 5A and 5B.

As shown in Figs. 10A and 10B, the timing controller sets the phases of the scan shift clocks so that data voltages are continuously applied to the pixels of the same color, but with two frame periods so that the color shift pixel positions are not fixed but dispersed. Change the phase of the scan shift clocks every frame. On the other hand, the timing controller can secure the stability of the operation by fixing the phase of the carry shift clocks and sense shift clocks irrelevant to the data write operation irrespective of the phase change between the scan shift clocks.

The phase change of the scan shift clocks shown in FIGS. 15A and 15B and the write operation of the data voltages are substantially the same as those described with reference to FIGS. 10A and 10B.

As described above, the present invention can set the phase of the scan shift clocks so that the data voltage is continuously applied to the pixels of the same color, thereby greatly reducing the heat generation and power consumption of the data driver. In addition, the present invention can significantly reduce visibility of periodic dark spots / bright spots by changing the phase of the scan shift clocks every frame every n frame periods so that the color shift pixel positions are not fixed and dispersed.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present specification. Therefore, the technical scope of the present specification should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

10: display panel 11: timing controller
12: data driver 13: gate driver

Claims (16)

Pixels of the first color disposed on one side of the data line and pixels of the second color disposed on the other side of the data line are connected to share the data line, and the pixels of the first color and the pixels of the second color are connected. A display panel connected to different gate lines;
A timing controller for changing a phase between the scan shift clocks at a predetermined period;
A gate driver generating scan signals corresponding to the scan shift clocks and applying the scan signals to the gate lines;
A data driver generating data voltages synchronized with the scan signals and applying the data voltages to the data lines;
The data voltages are sequentially applied to the data line by n (n is a positive integer of 2 or more) for pixels of the same color,
2. The display device of claim 1, wherein the order in which the data voltages are written in pixels is changed from frame to frame in accordance with a phase change between the scan shift clocks. The method of claim 1,
And the color conversion pixel positions at which the data voltages are started to be written n consecutively into the pixels of the same color are changed from frame to frame. The method of claim 1,
And a phase change between the scan shift clocks is performed every frame every n frame periods. The method of claim 3, wherein
And an order in which the data voltages are written into the pixels is changed every frame, and repeated equally every n frame periods. The method of claim 1,
The gate lines include a first gate line connected to the pixel of the first color and a second gate line connected to the pixel of the second color,
Each stage of the gate driver includes a first pull-up element connected to the first gate line and a second pull-up element connected to the second gate line,
And a gate electrode of the first pull-up element and a gate electrode of the second pull-up element are connected to the same node Q. The method of claim 5, wherein
The scan shift clocks include a scan shift clock of a first group and a scan shift clock of a second group,
One of the scan shift clocks of the first group is input to one electrode of the first pull-up device,
The display device of claim 1, wherein any one of the scan shift clocks of the second group is input to one electrode of the second pull-up device. The method of claim 5, wherein
The gate lines further include a third gate line connected to the pixel of the first color and the pixel of the second color,
Each stage of the gate driver further includes a third pull-up device connected to the third gate line to apply a sense signal to the third gate line,
A gate electrode of the third pull-up element is connected to the node Q,
The display device of claim 1, wherein any one of the sense shift clocks corresponding to the sense signal is input to one electrode of the third pull-up element. The method of claim 7, wherein
And a phase of the sense shift clocks is fixed regardless of a phase change between the scan shift clocks. The method of claim 7, wherein
The display panel,
Scan shift clock wires for applying the scan shift clocks to the gate driver;
Sense shift clock wires for applying the sense shift clocks to the gate driver;
And the number of the sense shift clock wires is half of the number of the scan shift clock wires. The method of claim 1,
The timing controller further generates carry shift clocks necessary for the operation of the gate driver.
And a phase of the sense shift clocks is fixed regardless of a phase change between the scan shift clocks. The method of claim 10,
The display panel,
Scan shift clock wires for applying the scan shift clocks to the gate driver;
A carry shift clock wires for applying the carry shift clocks to the gate driver;
And the number of the carry shift clock wires is half the number of the scan shift clock wires. Pixels of the first color disposed on one side of the data line and pixels of the second color disposed on the other side of the data line are connected to share the data line, and the pixels of the first color and the pixels of the second color are connected. In a driving method of a display device connected to different gate lines,
Changing the phase between the scan shift clocks at a predetermined period;
Generating scan signals corresponding to the scan shift clocks and applying the scan signals to the gate lines;
Generating data voltages synchronized with the scan signals and applying the data voltages to the data lines;
The data voltages are sequentially applied to the data line by n (n is a positive integer of 2 or more) for pixels of the same color,
And an order in which the data voltages are written in pixels is changed from frame to frame according to a phase change between the scan shift clocks. The method of claim 12,
And the color conversion pixel positions at which the data voltages start to be written n consecutively into the pixels of the same color are changed every frame. The method of claim 12,
And a phase change between the scan shift clocks is performed every frame every n frame periods. The method of claim 14,
And the order in which the data voltages are written into the pixels is changed every frame, and is repeated equally with the n frame period. The method of claim 12,
Generating carry shift clocks necessary for generating the scan signals; And
Generating sense shift clocks synchronized with the scan signals and other sense signals;
And a phase of the carry shift clocks and a phase of the sense shift clocks are fixed regardless of a phase change between the scan shift clocks.

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