KR20200052732A - Image display device and method for driving the same - Google Patents

Abstract

Disclosed is a video display device and a driving method thereof. An image display device according to an embodiment of the present invention includes a video display panel having a plurality of pixel areas to display an image, a data driver supplying an analog image signal to data lines of the image display panel, and image data in LVDS format. Converts the data control signal, modulates the phase of the reference frequency signal to generate a plurality of modulated frequency signals having different phases, and outputs the LVDS format image data and data control signal according to the plurality of modulated frequency signals having different phases. Since it includes a timing controller that transmits to the driver, it is possible to reduce the EMI effect by modulating and using at least one of the phase, spectrum, profile, and input / output timing of the reference frequency signal in a timing controller.

Description

IMAGE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present invention relates to an image display device and a driving method capable of reducing the effect of electromagnetic magnetic interference (EMI) by modulating and using a phase of a reference frequency signal.

Flat panel video display devices are used in various types of electronic products, including mobile phones, tablet PCs, and notebook computers. As a flat panel image display device, a liquid crystal display device, an organic light emitting diode display device, an electronic wet display device, and a field emission device are mainly applied.

A liquid crystal display device or an organic light emitting diode display device displays an image by adjusting a light transmittance or an emission amount of each pixel through an image display panel in which a plurality of pixels are arranged in a matrix form. To this end, panel driving circuits for driving the pixels of the image display panel are configured to be mounted or electrically connected to the image display panel.

For example, in the case of the organic light emitting diode display panel, a plurality of gate lines and data lines are arranged to cross each other, and pixels including the organic light emitting diode are configured in each pixel area defined by the gate lines and the data lines crossing each other. do.

The panel driving circuit includes a gate driving circuit that sequentially drives the gate lines, a data driving circuit that supplies data voltages to the data lines, and a timing controller that supplies gates and data control signals to control driving timings of the gate and data driving circuits. It includes.

The timing controller aligns digital image data from the outside according to the resolution characteristics of the image display panel, and transmits the aligned image data to the gate and data driving circuit together with the gate and data control signals. At this time, the timing controller converts the aligned image data and data control signal to a format conforming to the EPI (Embedded Clock Point-Point Interface) protocol and transmits it to the data driving circuit in a low voltage differential signaling (LVDS) interface method. .

The LVDS interface method is a method in which multiple channels are connected between a transmission module (for example, a timing controller and a reception module (for example, a data driving circuit)), and digital data or control signals are converted into LVDS signal levels and transmitted. Accordingly, digital image data and data control signals converted to LVDS signal levels are transmitted through a plurality of preset channels.

To transmit the LVDS signal through multiple channels, the LVDS transmission module receives a preset reference frequency signal, and transmits the LVDS signal according to the frequency size or speed of the reference frequency signal.

However, since the LVDS transmission module configured in the conventional timing controller keeps the data transmission speeds of multiple channels matched with the reference frequency signal, all of them have to increase interference with electromagnetic interference (EMI) due to frequency overlap between channels. There was not.

Accordingly, in the related art, a method of reducing the EMI effect has been proposed by spreading or de-spreading the energy spectrum of the reference frequency signal or by shifting the phase of the reference frequency signal to a timing controller.

However, the conventional EMI reduction scheme has problems in that its design area and manufacturing cost increase because a spectrum modulation unit or a phase modulation unit for spreading or despreading the energy spectrum of the reference frequency signal has to be added separately from the timing controller. .

An object of the present invention is to provide a video display device and a driving method for reducing the EMI effect by modulating and using at least one of the phase, spectrum, profile, and input / output timing of a reference frequency signal in a timing controller. will be.

In addition, it is an object of the present invention to provide an image display device and a driving method that can self-compensate for a data transmission timing asynchronous error that may be caused by changing and using a phase or profile of a reference frequency signal.

An image display device according to an embodiment of the present invention includes a video display panel having a plurality of pixel areas to display an image, a data driver supplying an analog image signal to data lines of the image display panel, and image data in LVDS format. Converts the data control signal, modulates the phase of the reference frequency signal to generate a plurality of modulated frequency signals having different phases, and outputs the LVDS format image data and data control signal according to the plurality of modulated frequency signals having different phases. It includes a timing controller that transmits to the driver.

In addition, the driving method of an image display device according to an embodiment of the present invention converts image data and a data control signal in an LVDS format and modulates the phases of the reference frequency signal to generate a plurality of modulated frequency signals having different phases. , Transmitting LVDS format image data and data control signals to a data driver according to a plurality of modulated frequency signals having different phases, and analog images to data lines of an image display panel according to the LVDS format image data and data control signals. And supplying a signal and sequentially driving a gate line of the video display panel according to the supply time of the analog video signal.

The video display device and the driving method according to the present invention have an effect of reducing the EMI effect by modulating and using at least one of the phase, spectrum, profile, and input / output timing of a reference frequency signal in a timing controller.

In addition, the video display device and the driving method according to the present invention can improve the reliability of the data transmission timing asynchronous error that may be caused by changing the phase or profile of the reference frequency signal by itself. It has an effect.

1 is a configuration diagram specifically showing an image display device according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating the structure of the timing controller and data driver shown in FIG. 1 in more detail.
3 is a configuration block diagram specifically showing a frequency signal modulator according to a first embodiment of the present invention.
FIG. 4 is a configuration block diagram specifically showing the first modulated signal output unit illustrated in FIG. 3.
5 is a waveform diagram showing the first to third modulated frequency signals and the first to third transmission signals of FIG. 3.
6 is a configuration block diagram specifically showing a frequency signal modulator according to a second embodiment of the present invention.
FIG. 7 is a block diagram of a first timing compensator illustrated in FIG. 6 in detail.
8 is a block diagram of a frequency signal modulator according to a third embodiment of the present invention.
FIG. 9 is a block diagram showing the first delay circuit shown in FIG. 8 in detail.
10 is a waveform diagram showing first to third modulated frequency signals and first to third transmission signals of FIG. 8.
11 is a configuration block diagram specifically showing a frequency signal modulator according to a fourth embodiment of the present invention.
12 is a configuration block diagram specifically showing the first rectifying circuit shown in FIG. 11.
13 is a waveform diagram illustrating first to third modulated frequency signals and first to third transmission signals of FIG. 11.

The above-described objects, features, and advantages will be described in detail below with reference to the accompanying drawings, and accordingly, a person skilled in the art to which the present invention pertains can easily implement the technical spirit of the present invention. In the description of the present invention, when it is determined that detailed descriptions of known technologies related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions will be omitted.

An image display device to which the main technology of the present invention is applied includes a liquid crystal display, a field emission display, an organic light emitting display, and a quantum dot display device Dot Display). Hereinafter, an organic light emitting diode display device will be described as an example.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram specifically showing an image display device according to an embodiment of the present invention.

The organic light emitting diode display device illustrated in FIG. 1 includes an organic light emitting diode display panel 100, a gate driver 200, a data driver 300, a power supply unit 400, and a timing controller 500.

A plurality of pixel areas are defined in the organic light emitting diode display panel 100, and a plurality of sub-pixels P are arranged in a matrix form in each pixel area to display an image. Here, the sub-pixel P formed in each pixel area includes an organic light emitting diode and a diode driving circuit that independently drives the light emitting diode. The diode driving circuits supply the analog data voltage from the connected data line DL to the light emitting diodes, while allowing the data voltage to be charged so that the light emission state is maintained.

The timing controller 500 aligns the image data from the outside to the driving of the organic light emitting diode display panel 100 and transmits it to the data driver 300, and also generates data and gate control signals DCS and GCS. The driving timings of the data and gate drivers 300 and 200 are controlled.

Specifically, the timing controller 500 converts the aligned image data and data control signal (DCS) format according to the EPI (Embedded Clock Point-Point Interface) protocol, and a Low Voltage Differential Signaling (LVDS) interface. Data to the data driver 300.

The LVDS interface method allows multiple channels to be connected between a transmitting device (eg, a timing controller 500 and a receiving device (eg, a data driver 300)), and converts digital image data or control signals into an LVDS format. It is a method of transmitting at LVDS level through multiple channels.

The timing controller 500 uses the LVDS interface method, so that the image data (Data) and the data control signal (DCS) are arranged in a preset EPI protocol format, sequentially converted to LVDS level, and the data driver 300 through multiple channels. Transfer to. To this end, the timing controller 500 modulates the phase of the reference frequency signal input from the outside to generate a plurality of modulated frequency signals having different phases. Then, the image data (Data) and the data control signal (DCS) are transmitted to the LVDS level through multiple channels so as to correspond to the phase and frequency level of each modulated frequency signal having different phases.

The data driver 300 restores and uses the data control signal (DCS) received through the LVDS interface in TTL (Transistor Transistor Logic) format. That is, the data driver 300 converts the image data Data to an analog image signal according to the gamma voltage using the data control signal DCS restored in the TTL format, and supplies it to the data lines DL1 to DLm.

Specifically, the data driver 300 uses a source start pulse (SSP) and a source shift clock (SSC) among the data control signals DCS from the timing controller 500 to perform timing. The digital image data (Data) from the controller 500 is converted into an analog image signal. In addition, a video signal is supplied to each data line DL1 to DLm in response to a source output enable (SOE) signal. Specifically, the data driver 300 latches the image data Data from the timing controller according to the SSC, and then every 1 horizontal cycle in which a scan pulse is supplied to each gate line GL1 to GLn in response to the SOE signal. The image data voltage is supplied to each data line DL1 to DLm for each horizontal line.

On the other hand, the gate driver 200 sequentially drives the gate lines GL1 to GLn of the organic light emitting diode display panel 100 every frame period. Specifically, the gate driver 200 responds to a gate control signal (GCS) from the timing controller 500, for example, a gate start pulse (GSP) and a gate shift clock (GSC). The gate-on signal is sequentially generated, and the pulse width of the gate-on signal is controlled according to a gate output enable (GOE) signal. The gate-on signals are sequentially supplied to the gate lines GL1 to GLn.

The power supply unit 400 supplies a first power signal VDD to power lines PL1 to PLn of the organic light emitting diode display panel 100 and a second power signal GND to a ground line.

FIG. 2 is a diagram illustrating the structure of the timing controller and data driver shown in FIG. 1 in more detail.

Referring to FIG. 2, the timing controller 500 includes a frequency signal modulator 510, a data aligner 520, a control signal generator 530, and an LVDS transmitter 540.

The data alignment unit 520 aligns the image data RGB input from the outside according to driving characteristics of the organic light emitting diode display panel 100, for example, resolution or driving frequency characteristics. Then, the aligned image data (Data) is converted to the LVDS format by at least one horizontal line, and transmitted to the LVDS transmitter 540 during the data enable period during each horizontal period.

The control signal generator 530 controls the gate driver 200 to control the gate driver 200 according to the resolution characteristics of the organic light emitting diode display panel 100 by using synchronization signals DCLK, DE, Vsync, and Hsync from the outside. The signal GCS is generated. Then, the generated gate control signal GCS is transmitted to the gate driver 200 during every horizontal period or every frame period.

The control signal generation unit 530 generates the gate control signal GCS in the form of a TTL (Transistor Transistor Logic) format. Accordingly, the control signal generator 530 may transmit the gate control signal GCS to the gate driver 200 using a TTL communication method. If the LVDS interface method is used, the gate control signal GCS may be converted into an LVDS format and transmitted to the LVDS transmitter 540.

In addition, the control signal generation unit 530 generates a data control signal DCS for controlling the data driver 300 according to the driving characteristics of the organic light emitting diode display panel 100. The data control signal (DCS) is converted into an LVDS format and transmitted to the LVDS transmitter 540 during a blank period during each horizontal period.

The frequency signal modulator 510 modulates the phase of the reference frequency signal SCK input from the outside to generate a plurality of modulated frequency signals SCLK1 to SCLK3 having different phases. Then, a plurality of modulated frequency signals SCLK1 to SCLK3 having different phases are transmitted to the LVDS transmitter 540.

The LVDS transmitter 540 transmits image data (Data) and data control signals (DCS) in LVDS format so as to correspond to the phase and frequency levels of the modulated frequency signals SCLK1 to SCLK3 having different phases. Transfer to. To this end, the LVDS transmitter 540 is composed of a plurality of transmission channel groups Tx1 to Tx3 including at least one transmission channel.

Each transmission channel group (Tx1 to Tx3) receives one modulation frequency signal among a plurality of modulation frequency signals (SCLK1 to SCLK3) having different phases. Accordingly, each transmission channel group (Tx1 to Tx3) transmits the LVDS format image data (Data) and data control signal (DCS) to the data driver 300 to correspond to the phase and frequency level of the received modulated frequency signal, respectively. Is done. Specifically, each transmission channel group (Tx1 to Tx3) transmits LVDS format image data (Data) during a data enable period during each horizontal period. In addition, an LVDS format data control signal (DCS) is transmitted during a blank period during each horizontal period.

As illustrated in FIG. 2, the data driver 300 may be composed of a plurality of driving integrated circuits 310 to 330. Further, each of the driving integrated circuits 310 to 330 may be divided into different printed circuit boards or printed circuit films, and mounted.

Each driving integrated circuit (310 to 330) divided and mounted on different printed circuit boards or printed circuit films is configured to receive at least one receive channel group among a plurality of receive channel groups (Rx1 to Rx3) including at least one receive channel. It can be provided.

For example, the first driving integrated circuit 310 may include a first receiving channel group Rx1 including at least one receiving channel, and the second driving integrated circuit 320 may include at least one receiving channel. The included second reception channel group Rx2 may be included. Also, the third driving integrated circuit 330 may include a third reception channel group Rx3 including at least one reception channel.

The receiving channel groups Rx1 to Rx3 of each driving integrated circuit 310 to 330 receive LVDS format image data Data during a data enable period during each horizontal period. In addition, an LVDS format data control signal (DCS) is received during a blank period during each horizontal period.

3 is a configuration block diagram specifically showing a frequency signal modulator according to a first embodiment of the present invention.

The frequency signal modulation unit 510 illustrated in FIG. 3 includes a plurality of modulation output units 511 to 513, and a modulation profile supply unit 514.

The plurality of modulation output units 511 to 513 modulate and output the phases of the reference frequency signal SCK differently using respective different modulation profiles PFS1, PFS2, and PFS3. In addition, the modulation profile supply unit 514 provides respective modulation profiles PFS1, PFS2, and PFS3 to the respective modulation output units 511 to 513.

Specifically, the first modulation output unit 511 of the plurality of modulation output units 511 to 513 uses the first modulation profile PFS1 provided from the modulation profile supply unit 514 to phase the reference frequency signal SCK. Modulate. Then, a first modulated frequency signal SCLK1 having a different phase from the reference frequency signal SCK is generated and transmitted to the first transmission channel group Tx1 of the LVDS transmitter 540.

The second modulation output unit 512 of the plurality of modulation output units 511 to 513 modulates the phase of the reference frequency signal SCK using the second modulation profile PFS2 provided from the modulation profile supply unit 514. . Then, the reference frequency signal SCK and the first modulated frequency signal SCLK1 and the second modulated frequency signal SCLK2 having different phases are generated and transmitted to the second transmission channel group Tx2 of the LVDS transmitter 540.

The third modulation output unit 513 of the plurality of modulation output units 511 to 513 modulates the phase of the reference frequency signal SCK using the third modulation profile PFS3 provided from the modulation profile supply unit 514. . Then, the first and second modulated frequency signals SCLK1 and SCLK2 and third modulated frequency signals SCLK3 having different phases are generated and transmitted to the third transmission channel group Tx3 of the LVDS transmitter 540.

FIG. 4 is a configuration block diagram specifically showing the first modulated signal output unit illustrated in FIG. 3.

4, any one of the plurality of modulation output units 511 to 513, for example, the first modulation output unit 511 is a reference frequency signal input unit 521, a first frequency modulation output unit 522, a modulation profile input unit 523.

Specifically, the reference frequency signal input unit 521 supplies the reference frequency signal SCK input from the outside to the first frequency modulation output unit 522. In addition, the modulation profile input unit 523 supplies the first modulation profile PFS1 input from the modulation profile supply unit 514 to the first frequency modulation output unit 522.

The first frequency modulated output unit 522 changes the phase of the reference frequency signal SCK inputted through the reference frequency signal input unit 521 to correspond to the first modulation profile PFS1, and thus the phase and the reference frequency signal SCK. The different first modulated frequency signals SCLK1 are generated.

The modulation profile input unit 523 changes the phase of the first modulation frequency signal SCLK1 output from the first frequency modulation output unit 522 so as to correspond to the first modulation profile PFS1, so that the first frequency modulation output unit 522 ) As a feedback signal. In this case, the first frequency modulated output unit 522 generates a first modulated frequency signal SCLK1 by changing the phase of the reference frequency signal SCK to correspond to a feedback signal input through the modulation profile input unit 523. Can be.

5 is a waveform diagram showing the first to third modulated frequency signals and the first to third transmission signals of FIG. 3.

Referring to FIG. 5 together with FIG. 4, the first modulation output unit 511 modulates the phase of the reference frequency signal SCK using the first modulation profile PFS1 preset in the modulation profile supply unit 514. . In this case, the first modulation profile PFS1 may be preset as a frequency signal generated from a first time point ST1 different from a time point at which the reference frequency signal SCK is input. In this case, the phases of the frequency signal generated from the reference frequency signal SCK and the first time point ST1 are different, but the amplitude and pulse width may be the same.

Accordingly, the first modulation output unit 511 may generate the first modulated frequency signal SCLK1 by changing the phase of the reference frequency signal SCK to correspond to the phase of the frequency signal generated at the first time point ST1. have.

The first transmission channel group Tx1 that receives the first modulation frequency signal SCLK1 among the plurality of transmission channel groups Tx1 to Tx3 controls image data and data in response to the first modulation frequency signal SCLK1. The signal DCS is output to the first reception channel group Rx1.

On the other hand, the second modulation output unit 512 modulates the phase of the reference frequency signal SCK using the second modulation profile PFS2 preset in the modulation profile supply unit 514. In this case, the second modulation profile PFS2 may be preset as a frequency signal generated from a second time ST2 different from a time at which the reference frequency signal SCK is input. In this case, the phases of the frequency signal generated from the reference frequency signal SCK and the second time point ST2 are different, but the amplitude and pulse width may be the same.

Accordingly, the second modulation output unit 512 may generate a second modulated frequency signal SCLK2 by changing the phase of the reference frequency signal SCK to correspond to the phase of the frequency signal generated at the second time point ST2. have.

The second transmission channel group Tx2 that receives the second modulation frequency signal SCLK2 among the plurality of transmission channel groups Tx1 to Tx3 controls image data and data in response to the second modulation frequency signal SCLK2. The signal DCS is output to the second reception channel group Rx2.

In addition, the third modulation output unit 513 modulates the phase of the reference frequency signal SCK using the third modulation profile PFS3 preset in the modulation profile supply unit 514. In this case, the third modulation profile PFS3 may be preset as a frequency signal generated from a third time ST3 different from a time point at which the reference frequency signal SCK is input.

Accordingly, the third modulated output unit 513 may generate a third modulated frequency signal SCLK3 by changing the phase of the reference frequency signal SCK to correspond to the phase of the frequency signal generated at the third time point ST3. have.

The third transmission channel group Tx3 that receives the third modulation frequency signal SCLK3 among the plurality of transmission channel groups Tx1 to Tx3 controls image data and data in response to the third modulation frequency signal SCLK3. The signal DCS is transmitted to the third reception channel group Rx3.

As illustrated in the first embodiment, the timing controller 500 of the present invention can modulate and use at least one characteristic of a phase, energy spectrum, amplitude profile, and input / output timing of a reference frequency signal SCK. . However, if only a plurality of preset profiles are used for a long time, a data transmission timing asynchronous error may occur in units of each transmission channel group (Tx1, Tx2, Tx3).

6 is a configuration block diagram specifically showing a frequency signal modulator according to a second embodiment of the present invention.

Referring to FIG. 6, the frequency signal modulator 510 of the present invention includes a plurality of timing compensators 531 and 532 to prevent data transmission timing asynchronous errors that may occur in respective transmission channel groups Tx1, Tx2, and Tx3. ).

Specifically, the frequency signal modulator 510 is a 2n-1 th modulated frequency signal SCLK1 output from a 2n-1 th modulated output unit among a plurality of modulated output units 511 to 513, and a 2n th modulated output unit. A plurality of timing compensators 531 and 532 for alternately transmitting and outputting the 2n-th modulation frequency signal SCLK2 to the 2n-th transmission channel group Tx1 and the 2n-th transmission channel group Tx2 in units of preset periods are transmitted. It includes more. Here, n is a natural number excluding zero.

The first timing compensator 531 among the plurality of timing compensators 531 and 532 is a first modulated frequency signal SCLK1 output from the first modulated output part 511 and a second modulated output part 512. 2 The modulated frequency signal SCLK2 is alternately transmitted to the first transmission channel group Tx1 and the second transmission channel group Tx2 in units of a preset period.

Similarly, the second timing compensator 532 uses the third modulated frequency signal SCLK3 output from the third modulated output unit 513 and the fourth modulated frequency signal output from the fourth modulated output unit in a preset period unit. The third transmission channel group (Tx3) and the fourth transmission channel group are alternately transmitted.

FIG. 7 is a block diagram of a first timing compensator illustrated in FIG. 6 in detail.

Referring to FIG. 7, each of the plurality of timing compensation units 531 and 532 is input to the first and second input terminals in response to a high or low logic inversion signal INS that is inverted at a preset period during a preset period. And alternating output circuits that alternately cross and output the first and second modulated frequency signals to the first and second output terminals.

Specifically, the cross output circuit includes first to fourth switching elements T1 to T4 and an inverter IH1. Here, the first switching element T1 outputs the first modulated frequency signal SCLK1 input to the first input terminal to the first output terminal in response to the inverted signal INS input as the high logic signal.

The second switching element T2 outputs the second modulated frequency signal SCLK2 input to the second input terminal to the second output terminal in response to the inversion signal INS input as the high logic signal.

The third switching element T3 outputs the second modulated frequency signal SCLK2 input to the second input terminal to the first output terminal in response to the inverted signal INS input to the high logic through the inverter IH1.

The fourth switching element T4 outputs the first modulated frequency signal SCLK1 input to the first input terminal to the second output terminal in response to the inversion signal INS input to the high logic through the inverter IH1.

When the cross output circuit configured as described above is used, the 2n-1th modulation frequency signal (SCLK1) and the 2nth modulation frequency signal of 2n-1th transmission channel group (Tx1) and 2nth transmission channel group (Tx2) of different spectrums are used. Since (SCLK2) is used alternately, the effect of dispersing the spectrum can be achieved.

8 is a block diagram of a frequency signal modulator according to a third embodiment of the present invention.

Referring to FIG. 8, the frequency signal modulator 510 includes a plurality of modulation output units 511.512, 513, and a plurality of delay circuit units configured to correspond to the number of transmission channel groups Tx1 to Tx3 of the LVDS transmitter 540. 541,542).

Specifically, the first modulation output unit 511 corresponds to the first transmission channel group Tx1 of the LVDS transmission unit 540, and the reference frequency signal SCK input from the outside is converted into the first modulation frequency signal SCLK1. Applied to transmit to the first transmission channel group (Tx1).

The first delay circuit unit 541 receives the first modulation frequency signal SCLK1 transmitted from the first modulation output unit 511 to the first transmission channel group Tx1 in a parallel structure, and receives the received first modulation frequency signal The phase of (SCLK1) is delayed for a preset period and output.

The second modulation output unit 512 corresponds to the second transmission channel group Tx2 of the LVDS transmission unit 540, and the delayed frequency signal dSCLK1 from the first delay circuit unit 541 is the second modulation frequency signal SCLK2. Output as The second modulated frequency signal SCLK2 is transmitted to the second transmission channel group Tx2.

The second delay circuit unit 542 receives the second modulation frequency signal SCLK2 transmitted from the second modulation output unit 512 to the second transmission channel group Tx2 in a parallel structure, and the received second modulation frequency signal The phase of (SCLK2) is delayed for a predetermined period before being output.

The third modulation output unit 513 corresponds to the third transmission channel group Tx3 of the LVDS transmission unit 540, and the delayed frequency signal dSCLK2 from the second delay circuit unit 542 is the third modulation frequency signal SCLK3. Output as The third modulated frequency signal SCLK3 is transmitted to the third transmission channel group Tx3.

FIG. 9 is a block diagram showing the first delay circuit shown in FIG. 8 in detail. 10 is a waveform diagram showing the first to third modulated frequency signals and the first to third transmission signals of FIG. 8.

First, referring to FIG. 9, the first delay circuit unit 541 receives the first modulated frequency signal SCLK1 through the first resistor element R1 to the inverting terminal (-), and receives the first capacitor C. The first modulating frequency signal SCLK1 is received through the non-inverting terminal (+) through the first modulating frequency signal SCLK1 according to the clock signal fed back through the second resistor element R2. It includes an amplifying element (OP1) for delayed output.

The delay period of the first modulation frequency signal SCLK1 of the amplification element OP1 is fed back through the variable resistance value of the third resistance element R3 connected in parallel to the non-inverting terminal + and the second resistance element R2. It can be set by the period of the clock signal. Accordingly, the RC time constant according to the capacities of the first to third resistance elements R1 to R3 and the first capacitor C is a period of a predetermined period (ST1 to ST2) of which the amplifying element OP1 is 1/4 cycle or the like. ) Is set in advance so that the first modulated frequency signal SCLK1 is delayed for output.

Due to the circuit configuration of the first delay circuit unit 541, the first delay circuit unit 541 delays and outputs the first modulated frequency signal SCLK1 for a period of 1/4 period (ST1 to ST2). 10, the phase of the first modulated frequency signal SCLK1 and the phase of the second modulated frequency signal SCLK2 may be output and maintained in a delayed state for a period of 1/4 period (ST1 to ST2). .

Accordingly, the second transmission channel group Tx2 receiving the second modulation frequency signal SCLK2 among the plurality of transmission channel groups Tx1 to Tx3 is the image data Data in response to the second modulation frequency signal SCLK2. And the data control signal DCS are output to the second reception channel group Rx2.

Similarly, the second delay circuit portion 542 has the same circuit configuration as the first delay circuit portion 541. Accordingly, the second delay circuit unit 542 delays and outputs the second modulated frequency signal SCLK2 for a period of 1/4 period (ST2 to ST3). As shown in FIG. 10, the second modulated frequency signal The phase of (SCLK2) and the phase of the third modulated frequency signal (SCLK3) may be output and maintained in a delayed state for a period of 1/4 period (ST2 to ST3).

Accordingly, the third transmission channel group Tx3 receiving the third modulation frequency signal SCLK3 among the plurality of transmission channel groups Tx1 to Tx3 is the image data Data in response to the third modulation frequency signal SCLK3. And the data control signal DCS are output to the third reception channel group Rx3.

11 is a configuration block diagram specifically showing a frequency signal modulator according to a fourth embodiment of the present invention.

Referring to FIG. 11, the frequency signal modulator 510 includes a plurality of modulation output units 511.512 and 513 configured to correspond to the number of transmission channel groups Tx1 to Tx3 of the LVDS transmitter 540, and a plurality of rectifying circuit units ( 551,552).

Specifically, the first modulation output unit 511 corresponds to the first transmission channel group Tx1 of the LVDS transmission unit 540, and the reference frequency signal SCK input from the outside is converted into the first modulation frequency signal SCLK1. Applied to transmit to the first transmission channel group (Tx1).

The first rectifying circuit unit 551 receives the first modulation frequency signal SCLK1 transmitted from the first modulation output unit 511 to the first transmission channel group Tx1 in a parallel structure, and the received first modulation frequency signal The phase of (SCLK1) is rectified to a preset rectified voltage level and output.

The second modulation output unit 512 corresponds to the second transmission channel group Tx2 of the LVDS transmission unit 540, and the frequency signal RSCLK1 rectified from the first rectification circuit unit 551 is the second modulation frequency signal SCLK2. ). The second modulated frequency signal SCLK2 is transmitted to the second transmission channel group Tx2.

The second rectifying circuit unit 552 receives the second modulation frequency signal SCLK2 transmitted from the second modulation output unit 512 to the second transmission channel group Tx2 in a parallel structure, and the received second modulation frequency signal The phase of (SCLK2) is rectified to a preset current voltage level and output.

The third modulation output unit 513 corresponds to the third transmission channel group Tx3 of the LVDS transmission unit 540, and the rectified frequency signal RSCLK2 from the second rectification circuit unit 552 is the third modulation frequency signal SCLK3. ). The third modulated frequency signal SCLK3 is transmitted to the third transmission channel group Tx3.

12 is a configuration block diagram specifically showing the first rectifying circuit shown in FIG. 11. And FIG. 13 is a waveform diagram showing first to third modulated frequency signals and first to third transmission signals of FIG. 11.

First, referring to FIG. 12, the first rectifying circuit unit 551 is connected to the first to fourth diode elements D1 to D4 and the first to fourth diode elements D1 to D4 connected in a bridge structure, It includes a power supply unit for supplying a low potential reference voltage, a stabilization reduction element (RR) connected in parallel with the first to fourth diode elements (D1 to D4) of the bridge structure.

The first rectifying circuit unit 551 rectifies the phase, amplitude, and pulse width of the first modulated frequency signal SCLK1 input to the high potential reference voltage input terminal as the capacitances of the first to fourth diode elements D1 to D4 Rectifies to a voltage level and outputs.

Referring to FIG. 13, the first rectifying circuit unit 551 determines the phase, amplitude, and pulse width of the first modulated frequency signal SCLK1 as the capacitances of the first to fourth diode elements D1 to D4. Rectifies to and outputs the second modulated frequency signal SCLK2 at a high potential level.

Accordingly, the second transmission channel group Tx2 receiving the second modulation frequency signal SCLK2 among the plurality of transmission channel groups Tx1 to Tx3 is the image data Data in response to the second modulation frequency signal SCLK2. And the data control signal DCS are output to the second reception channel group Rx2.

On the other hand, in the case of the second rectifying circuit 552, the phase, amplitude and pulse width of the second modulated frequency signal SCLK2 input to the low potential reference voltage input terminal are the capacities of the first to fourth diode elements D1 to D4. Rectifies to a rectified voltage level determined by and outputs.

At this time, the second rectifying circuit unit 552 rectifies the phase, amplitude, and pulse width of the second modulated frequency signal SCLK2 to a rectified voltage level determined by the capacity of the first to fourth diode elements D1 to D4. The third modulated frequency signal SCLK3 can be output at the potential level.

Accordingly, the third transmission channel group Tx3 receiving the third modulation frequency signal SCLK3 among the plurality of transmission channel groups Tx1 to Tx3 is the image data Data in response to the third modulation frequency signal SCLK3. And the data control signal DCS are output to the third reception channel group Rx3.

As described above, the video display device and the driving method according to an embodiment of the present invention have at least one characteristic of phase, spectrum, profile, and input / output timing of the reference frequency signal CLK in the timing controller 500. It is possible to reduce the EMI effect by modulating and using.

In addition, the image display device and its driving method according to the present invention can be self-compensated for data transmission timing asynchronous errors that may be caused by changing the phase or profile of the reference frequency signal (CLK), thereby ensuring reliability. Can increase.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention pertains that various substitutions, modifications and changes are possible without departing from the technical details of the present invention. It will be clear to those who have the knowledge of Therefore, the scope of the present invention is indicated by the following claims, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted to be included in the scope of the present invention.

100: organic light emitting diode display panel
200: gate driver
300: data driver
400: power supply
500: timing controller
510: frequency signal modulator
520: data alignment unit
530: control signal generation unit
540: LVDS transmitter

Claims (13)

An image display panel having a plurality of pixel areas to display an image;
A data driver that supplies an analog video signal to data lines of the video display panel; And
Converts image data and data control signals into an LVDS format, modulates the phases of a reference frequency signal to generate a plurality of modulated frequency signals having different phases, and the LVDS format according to a plurality of modulated frequency signals having different phases. A timing controller for transmitting image data and data control signals to the data driver,
Video display device.
According to claim 1,
The timing controller
A data alignment unit for aligning the image data according to driving characteristics of the image display panel, converting the aligned image data into an LVDS format, and outputting the converted image data;
A control signal generator configured to generate the data control signal according to the driving characteristics of the video display panel and convert the data control signal into an LVDS format;
A frequency signal modulator for modulating the phase of the reference frequency signal to generate a plurality of modulated frequency signals having different phases and outputting a plurality of modulated frequency signals having different phases;
And an LVDS transmitter for transmitting image data and data control signals of the LVDS format to the data driver through multiple channels so as to correspond to phases and frequency levels of the plurality of modulated frequency signals having different phases.
Video display device.
According to claim 2,
The LVDS transmitter
It comprises a plurality of transmission channel group including at least one transmission channel,
Each transmission channel group receives one modulation frequency signal among a plurality of modulation frequency signals having different phases, and each of the received LVDS format image data and data corresponds to a phase and frequency level of the modulation frequency signal. Transmitting a control signal to the data driver,
Video display device.
According to claim 2,
The frequency signal modulator
A plurality of modulation output units for modulating and outputting phases of the reference frequency signal differently using different modulation profiles; And
And a modulation profile supply unit providing the respective modulation profiles to the respective modulation outputs.
Video display device.
The method of claim 4,
The frequency signal modulator
Of the plurality of modulation outputs, the 2n-1th modulation frequency signal output from the 2n-1th modulation output unit and the 2nth modulation frequency signal output from the 2nth modulation output unit in a preset period unit are 2n-1th A plurality of timing compensators for alternately transmitting the channel group and the 2n th channel group are further included, where n is a natural number excluding zero,
Video display device.
According to claim 2,
The frequency signal modulator
A first modulation output unit outputting the reference frequency signal as a first modulation frequency signal;
A first delay circuit unit delaying the phase of the first modulated frequency signal for a predetermined period;
A second modulation output unit outputting the delayed frequency signal from the first delay circuit unit as a second modulation frequency signal;
A second delay circuit unit for delaying the phase of the second modulated frequency signal for a predetermined period; And
And a third modulation output unit outputting the delayed frequency signal from the second delay circuit unit as a third modulation frequency signal.
Video display device.
According to claim 2,
The frequency signal modulator
A first modulation output unit outputting the reference frequency signal as a first modulation frequency signal;
A first rectifying circuit unit receiving the first modulated frequency signal output from the first modulated output unit in a parallel structure, and rectifying and outputting a phase of the received first modulated frequency signal to a preset rectified voltage level;
A second modulation output unit outputting the rectified frequency signal from the first rectification circuit unit as a second modulation frequency signal;
A second rectifying circuit unit receiving the second modulated frequency signal output from the second modulated output unit in a parallel structure, and rectifying and outputting a phase of the received second modulated frequency signal to a preset current voltage level;
And a third modulation output unit outputting the frequency signal rectified from the second rectification circuit unit as a third modulation frequency signal.
Video display device.
In addition to converting image data and data control signals into an LVDS format, modulating the phases of a reference frequency signal to generate a plurality of modulated frequency signals having different phases, and the LVDS format according to a plurality of modulated frequency signals having different phases. Transmitting the image data and the data control signal of the data driver;
Supplying an analog video signal to data lines of the video display panel according to the LVDS format video data and data control signal;
Sequentially driving a gate line of the video display panel according to the supply time of the analog video signal,
Method of driving a video display device.
The method of claim 8,
The step of transmitting the image data and data control signal in the LVDS format to the data driver is
Aligning the image data according to driving characteristics of the image display panel;
Converting the aligned image data into an LVDS format;
Generating the data control signal according to the driving characteristics of the video display panel and converting the data control signal into an LVDS format;
Modulating a phase of the reference frequency signal by a frequency signal modulator to generate and output a plurality of modulated frequency signals having different phases;
And transmitting image data and data control signals of the LVDS format to the data driver through multiple channels of an LVDS transmitter to correspond to phases and frequency levels of a plurality of modulated frequency signals having different phases.
Method of driving a video display device.
The method of claim 9,
The step of generating and outputting a plurality of modulated frequency signals having different phases is
Providing each modulation profile set in the modulation profile supply to each modulation output; And
Comprising the step of modulating and outputting the phase of the reference frequency signal differently using the different modulation profiles in the plurality of modulation output unit,
Method of driving a video display device.
The method of claim 10,
The step of generating and outputting a plurality of modulated frequency signals having different phases is
Of the plurality of modulation outputs, the 2n-1th modulation frequency signal output from the 2n-1th modulation output unit and the 2nth modulation frequency signal output from the 2nth modulation output unit in a preset period unit are 2n-1th Further comprising the step of transmitting alternately to the channel group and the 2n th channel group,
Method of driving a video display device.
The method of claim 8,
The step of generating and outputting a plurality of modulated frequency signals having different phases is
Outputting the reference frequency signal as a first modulated frequency signal using a first modulated output unit;
Delaying the phase of the first modulated frequency signal for a predetermined period using a first delay circuit unit;
Outputting a delayed frequency signal from the first delay circuit unit as a second modulation frequency signal using a second modulation output unit;
Delaying the phase of the second modulated frequency signal for a predetermined period using a second delay circuit unit; And
And outputting the delayed frequency signal from the second delay circuit unit as a third modulation frequency signal using a third modulation output unit.
Method of driving a video display device.
The method of claim 8,
The step of generating and outputting a plurality of modulated frequency signals having different phases is
Outputting the reference frequency signal as a first modulated frequency signal using a first modulated output unit;
Receiving, by a first rectifying circuit unit, a first modulated frequency signal output from the first modulated output unit in a parallel structure, and rectifying and outputting a phase of the received first modulated frequency signal to a preset rectified voltage level;
Outputting a frequency signal rectified from the first rectifying circuit unit as a second modulation frequency signal using a second modulation output unit;
Receiving a second modulation frequency signal of the second modulation output unit in a parallel structure from a second rectifying circuit unit, and rectifying and outputting a phase of the received second modulation frequency signal to a preset current voltage level; And
And outputting a frequency signal rectified from the second rectifying circuit unit as a third modulation frequency signal using a third modulation output unit.
Method of driving a video display device.

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