KR20200121478A - Thin-Film Transistor Having A Dual Source Layer and A Fabrication Method Of The Same - Google Patents

Abstract

A thin film transistor according to an embodiment of the present invention includes a substrate; A gate electrode disposed on the substrate; A gate insulating layer disposed to cover the gate electrode; An active layer on the gate insulating layer; A first source and a drain disposed on the active layer and spaced apart from each other around the gate electrode; An upper insulating layer filling the space between the first source and the drain, covering a portion of the first source, and covering a portion of the drain; And a second source disposed to contact the first source and cover a portion of the upper insulating layer.

Description

Thin-Film Transistor Having A Dual Source Layer and A Fabrication Method Of The Same}

The present invention relates to a thin film transistor, and more particularly, to a thin film transistor having a double source layer.

Recently, displays are pursuing higher resolution and larger area. The higher the resolution, the shorter the time required to charge the storage capacity capacitor for each scan line, and the RC delay due to the decrease in the width of the TFT (thin film transistor) increases the mobility of the TFT (Thin-Film Transistor). need. In particular, a semiconductor that can replace amorphous silicon (a-Si) or low-temperature polycrystalline silicon (LTPS) with the advent of TFT-LCD (Thin-Film Transistor Liquid Crystal Display) and large AMOLED (Active Matrix Organic Light-Emitting Diode) TVs. Interest in materials is increasing. In the case of high-resolution, large-area displays, a-Si thin film transistors (TFTs) having a charge mobility of ~1 cm ² /(V•s) have limitations. Low-temperature polycrystalline silicon (LTPS) TFT or oxide TFT technology with better mobility is being developed. Among them, as the importance of flexible displays has emerged in recent years, there is great interest in oxide TFTs that have a simpler manufacturing process and relatively low temperature process than LTPS (low temperature polysilicon) TFTs. However, in terms of mobility, it exhibits less performance than LTPS TFTs, so many studies are being conducted.

Therefore, in order to improve mobility, studies using the introduction of metal ions, composition control, and post-annealing have been reported in the early stage studies of oxide TFTs. Recently, research has been conducted to secure high mobility and excellent reliability characteristics by using a multilayer channel structure instead of a single layer channel structure. However, there is also a difficulty in accurately formulating the composition ratio of the material, and thus, improvement is being made through various studies.

Therefore, it is believed that implementing a thin film transistor capable of improving high mobility and reliability while using the existing material-specific processes as it is will have a profound impact not only on the display industry but also on the flexible electronic device industry.

The problem to be solved by the present invention is to implement a second source layer by depositing a source layer with metal up to an upper portion of the active layer (or channel layer) in the structure of a TFT having a first source layer. The gate voltage affects not only the first source layer but also the active layer (or channel layer) at the reference potential point to form a channel more easily. In addition, the second source layer is a conductive layer and may suppress a threshold voltage shift due to external light.

A thin film transistor according to an embodiment of the present invention includes a substrate; A gate electrode disposed on the substrate; A gate insulating layer disposed to cover the gate electrode; An active layer on the gate insulating layer; A first source and a drain disposed on the active layer and spaced apart from each other around the gate electrode; An upper insulating layer filling the space between the first source and the drain, covering a portion of the first source, and covering a portion of the drain; And a second source disposed to contact the first source and cover a portion of the upper insulating layer.

In an embodiment of the present invention, the second source may be disposed on the upper insulating layer to cover a space between the first source and the drain.

In one embodiment of the present invention, the active layer may be a-Si, LTPS, IGZO, or ZnO.

In one embodiment of the present invention, the gate electrode may be doped silicon, ITO, or aluminum.

In one embodiment of the present invention, the first source, the drain, and the second source may be a conductive metal or a metal alloy.

In an embodiment of the present invention, the second source may have a region overlapping the drain.

A method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention includes forming a gate electrode on a substrate; Forming a gate insulating layer to cover the gate electrode; Forming an active layer on the gate insulating layer; Forming a first source and a drain disposed on the active layer and spaced apart from each other around the gate electrode; Forming an upper insulating layer to fill a space between the first source and the drain, cover a portion of the first source, and cover a portion of the drain; And forming a second source disposed to contact the first source and cover a portion of the upper insulating layer.

A thin film transistor according to an embodiment of the present invention includes a substrate; A gate electrode disposed on the substrate; A gate insulating layer disposed to cover the gate electrode; A first source and a drain disposed on the gate insulating layer and spaced apart from each other; An active layer filling the space between the first source and the drain, covering a portion of the first source, and covering a portion of the drain; An upper insulating layer disposed to cover the active layer; And a second source disposed to contact the first source and cover a portion of the upper insulating layer.

In an embodiment of the present invention, the second source may be disposed to cover a space between the first source and the drain.

In one embodiment of the present invention, the active layer may be a-Si, LTPS, IGZO, or ZnO.

In one embodiment of the present invention, the first source, the drain, and the second source may be a conductive metal or a metal alloy.

In an embodiment of the present invention, the second source may have a region overlapping the drain.

A method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention includes forming a gate electrode on a substrate; Forming a gate insulating layer to cover the gate electrode; Forming first sources and drains disposed on the gate insulating layer and spaced apart from each other; Forming an active layer to fill a space between the first source and the drain, cover a portion of the first source, and cover a portion of the drain; Forming an upper insulating layer to cover the active layer; And forming a second source to contact the first source and cover a portion of the upper insulating layer.

The thin film transistor according to an embodiment of the present invention may stably form a channel and suppress a threshold voltage shift due to external light.

1 is a cross-sectional view showing a thin film transistor according to an embodiment of the present invention.
2A to 2F are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.
3 is a cross-sectional view illustrating a thin film transistor according to another embodiment of the present invention.
4A to 4F are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.

The TFT structure basically consists of a source, a conversion layer, a drain, a gate insulating film, and a gate electrode. An etch stop layer may be required during the etching process on the active layer. After fabrication of the TFT, a passivation layer may be required.

In the bottom-gate TFT according to an embodiment of the present invention, a gate electrode having good electrical conductivity is formed on a glass substrate, and a gate insulating film is stacked on the gate electrode. After that, an active layer in which a channel region is formed is formed, and then a first source and a drain are stacked. After depositing an insulating film on the exposed active layer between the first source and the drain, patterning is performed. A second source contacting the first source is formed on the insulating layer.

The thin film transistor according to an exemplary embodiment of the present invention can more easily form a channel in the active layer according to the gate voltage during operation of the TFT. In a typical TFT, the reference potential point of the gate voltage is limited to the source portion. However, in the structure according to an embodiment of the present invention, the reference potential point is connected to the active layer (??). In addition, when the constituent material of the second source is a metal or a metal alloy, the active layer sensitive to light is protected. Accordingly, in the case of a TFT used for a display, reliability with respect to light may be improved.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. Hereinafter, the present invention will be described in more detail with reference to preferred embodiments. However, these examples are intended to illustrate the present invention in more detail, and it will be apparent to those of ordinary skill in the art that the present invention is not limited or limited by experimental conditions, material types, and the like. The present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed contents may be thorough and complete and the spirit of the present invention may be sufficiently conveyed to those skilled in the art. In the drawings, components are exaggerated for clarity. Parts indicated by the same reference numerals throughout the specification represent the same elements.

1 is a cross-sectional view showing a thin film transistor according to an embodiment of the present invention.

Referring to FIG. 1, a thin film transistor 100 includes a substrate 110; A gate electrode 120 disposed on the substrate 110; A gate insulating layer 130 disposed to cover the gate electrode 120; An active layer 140 disposed on the gate insulating layer 130; A first source 150 and a drain 152 disposed on the active layer 140 and spaced apart from each other around the gate electrode 120; An upper insulating layer 160 filling the space between the first source 150 and the drain 152, covering a part of the first source 150, and covering a part of the drain 152; And a second source 170 disposed to contact the first source 150 and cover a portion of the upper insulating layer 160.

The substrate 110 may be a glass substrate, a dielectric substrate, or a plastic substrate. The substrate may serve as a substrate for a display device.

The gate electrode 120 may be silicon, aluminum, molybdenum, or titanium doped with a high concentration. The gate electrode 120 may be patterned to cross the active layer 140.

The gate insulating layer 130 may be disposed on the gate electrode 120. The gate insulating layer 130 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The gate insulating layer 130 may cover an upper surface and a side surface of the gate electrode 120.

The active layer 140 may be formed on the gate insulating layer 130. The active layer 140 may be patterned to be separated from neighboring transistors. The active layer 140 may be an n-type or p-type doped semiconductor. The active layer 140 may be amorphous silicon, polysilicon, IGZO (In-Ga-Zn-Oxide), or ZnO. The active layer 140 may form a channel in the active layer according to a gate voltage applied to the gate electrode 120.

The first source 150 and the drain 152 may be disposed on the active layer 140 to be spaced apart from each other around the gate electrode 120. The first source 150 may be ohmic-bonded with the active layer 140. In addition, the drain 152 may be ohmicly bonded to the active layer 140. The first source 150 and the drain 152 may be formed of a conductive material as electrodes. Specifically, the first source 150 and the drain 152 may be aluminum, molybdenum, or titanium. The first source 150, the drain 152, and the second source 170 may be a conductive metal or a metal alloy.

The upper insulating layer 160 is disposed to cover the exposed active layer 140 between the first source 150 and the drain 152. The upper insulating layer 160 may be patterned to cover a part of the first source 152 and to cover a part of the drain 152. The upper insulating layer 160 may be a silicon oxide layer or a silicon nitride layer. The dielectric constant and thickness of the upper insulating layer 160 may be appropriately adjusted to form a channel.

The second source 170 may extend to cover a portion of the exposed portion of the first source 150 and cover the upper insulating layer 160. The second source 170 may be disposed on the upper insulating layer 160 to cover a space between the first source and the drain. The second source 170 may expose a part of the upper insulating layer 160 to be electrically separated from the drain 152. The second source 170 may be made of the same material as the first source 150. The drain 152 and the second source 170 may have a region d that vertically overlaps. Accordingly, when light enters the second source 170, the second source 170 reflects the light to suppress the light from reaching the active layer 140. Accordingly, the thin film transistor can suppress fluctuations in the threshold voltage due to light.

2A to 2F are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.

2A to 2F, a method of manufacturing a thin film transistor includes forming a gate electrode 120 on a substrate 110; Forming a gate insulating layer 130 to cover the gate electrode 120; Forming an active layer 140 on the gate insulating layer 130; Forming a first source 150 and a drain 152 disposed on the active layer 140 and spaced apart from each other around the gate electrode 120; Forming an upper insulating layer 160 to fill the space between the first source 150 and the drain 152, cover a part of the first source 150, and cover a part of the drain 152; And forming a second source 170 disposed to contact the first source 150 and cover a portion of the upper insulating layer 160.

Referring to FIG. 2A, a gate electrode 120 is patterned on a substrate 110. The substrate 110 may be a glass substrate. The gate electrode 120 may be aluminum or molybdenum. The gate electrode 120 may be performed through a photolithography process and an anisotropic plasma etching process.

Referring to FIG. 2B, a gate insulating layer 130 may be formed on the substrate 110 on which the gate electrode 120 is formed. The gate insulating layer 130 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The gate insulating layer 130 may be formed by a chemical vapor deposition method.

Referring to FIG. 2C, an active layer 140 may be formed on the gate insulating layer 130. The active layer 140 may be amorphous silicon, polysilicon, IGZO (In-Ga-Zn-Oxide), or ZnO. The amorphous silicon may be formed by plasma assisted chemical vapor deposition. The polysilicon may be polycrystallized by laser irradiation of amorphous silicon. The active layer 140 may be patterned. The active layer 140 may be doped through an ion implantation process. Accordingly, the active layer corresponding to the region in which the first source 150 is to be disposed and the active layer corresponding to the region in which the drain 152 is to be disposed may be doped with a high concentration of impurities.

Referring to FIG. 2D, a first source 150 and a drain 152 may be patterned on the active layer 140. The first source 150 and the drain 152 may be disposed on the active layer to be transposed from each other with respect to the gate electrode 120. A gap between the first source and the drain may be smaller than a width of the gate electrode 120. Accordingly, the channel can be stably formed. The first source 150 is grounded, and the drain 152 may be maintained at a drain voltage. The channel may be turned on or off according to the gate voltage applied to the gate electrode. The first source 150 and the drain 152 may be aluminum or molybdenum.

Referring to FIG. 2E, an upper insulating layer 160 is formed on the substrate on which the first source 150 and drain 152 are formed. The upper insulating layer 160 may fill a space between the first source and the drain, cover a portion of the first source, and cover a portion of the drain. The thickness and dielectric constant of the upper insulating layer may control the shape of the channel. The upper insulating layer 160 may be a silicon oxide layer or a silicon nitride layer.

Referring to FIG. 2F, a second source 170 may be formed to contact the first source 150 and cover a part of the upper insulating layer 160. The second source 170 may have a region overlapping the drain 152. The second source 170 may cover a region between the first source 150 and the drain 152. The second source 170 may be formed of the same material as the first source.

3 is a cross-sectional view illustrating a thin film transistor according to another embodiment of the present invention.

Referring to FIG. 3, the thin film transistor 200 includes a substrate 110; A gate electrode 120 disposed on the substrate 110; A gate insulating layer 130 disposed to cover the gate electrode 120; A first source 250 and a drain 252 disposed on the gate insulating layer 130 and spaced apart from each other; An active layer 240 filling the space between the first source 250 and the drain 252, covering a part of the first source 250, and covering a part of the drain 252; An upper insulating layer 260 disposed to cover the active layer 240; And a second source 270 disposed to contact the first source 250 and cover a portion of the upper insulating layer 260.

The gate insulating layer 130 may be disposed on the gate electrode 120. The gate insulating layer 130 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The gate insulating layer 130 may cover an upper surface and a side surface of the gate electrode 120.

The first source 250 and the drain 252 may be disposed on the gate insulating layer 130 to be spaced apart from each other around the gate electrode 120. The first source 250 may be ohmic-bonded with the active layer 240. In addition, the drain 252 may be ohmic-bonded with the active layer 240. The first source 250 and the drain 252 may be formed of a conductive material as electrodes. Specifically, the first source 250 and the drain 252 may be aluminum, molybdenum, or titanium.

The active layer 240 may be formed on the exposed gate insulating layer 130 between the first source 250 and the drain 252. The active layer 240 may be patterned to be separated from neighboring transistors. The active layer 240 may be an n-type or p-type doped semiconductor. The active layer 240 may be amorphous silicon, polysilicon, IGZO (In-Ga-Zn-Oxide), or ZnO. The active layer 240 may form a channel in the active layer according to a gate voltage applied to the gate electrode 120.

The upper insulating layer 260 is disposed to cover the active layer 240. The upper insulating layer 260 may be patterned to cover side surfaces and upper surfaces of the active layer. The upper insulating layer 260 may be a silicon oxide layer or a silicon nitride layer. The dielectric constant and thickness of the upper insulating layer 260 may be appropriately adjusted to form a channel.

The second source 270 may extend to cover a part of the exposed portion of the first source 250 and cover the upper insulating layer 260. The second source 270 may be disposed on the upper insulating layer 260 to cover a space between the first source and the drain. The second source 270 may expose a part of the upper insulating layer 260 to be electrically separated from the drain 252. The second source 270 may be of the same material as the first source 250. The drain 252 and the second source 270 may have a vertically overlapping region d. Accordingly, when light enters the second source 170, the second source 270 reflects the light to suppress the light from reaching the active layer 240. Accordingly, the thin film transistor can suppress fluctuations in the threshold voltage due to light.

4A to 4F are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.

Referring to FIGS. 4A to 4F, a method of manufacturing a thin film transistor 200 includes forming a gate electrode 120 on a substrate 110; Forming a gate insulating layer 130 to cover the gate electrode; Forming a first source 250 and a drain 252 disposed on the gate insulating layer and spaced apart from each other; Forming an active layer 240 to fill a space between the first source 250 and the drain 252, cover a part of the first source 250, and cover a part of the drain 252; Forming an upper insulating layer 260 to cover the active layer 240; And forming a second source 270 to contact the first source 250 and cover a part of the upper insulating layer 260.

Referring to FIG. 4A, a gate electrode 120 is patterned on a substrate 110. The substrate 110 may be a glass substrate. The gate electrode 120 may be aluminum or molybdenum. The gate electrode 120 may be performed through a photolithography process and an anisotropic plasma etching process.

Referring to FIG. 4B, a gate insulating layer 130 may be formed on the substrate 110 on which the gate electrode 120 is formed. The gate insulating layer 130 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The gate insulating layer 130 may be formed by a chemical vapor deposition method.

Referring to FIG. 4C, a first source 250 and a drain 252 may be formed on the gate insulating layer 130. The first source 250 and the drain 252 may be disposed on the gate insulating layer 130 to be transposed from each other with respect to the gate electrode 120. A gap between the first source 250 and the drain 252 may be smaller than a width of the gate electrode 120. Accordingly, the channel can be stably formed. The first source 250 is grounded, and the drain 252 may be maintained at a drain voltage. The channel may be turned on or off according to the gate voltage applied to the gate electrode. The first source 250 and the drain 252 may be aluminum or molybdenum.

Referring to FIG. 4D, an active layer 240 is formed to fill the space between the first source 250 and the drain 252, cover a part of the first source 250, and cover a part of the drain 252. Can be formed. The active layer 240 may be amorphous silicon, polysilicon, IGZO (In-Ga-Zn-Oxide), or ZnO. The amorphous silicon may be formed by plasma assisted chemical vapor deposition. The polysilicon may be polycrystallized by laser irradiation of amorphous silicon. The active layer 240 may be patterned. The active layer 240 may be doped through an ion implantation process. Accordingly, the active layer in contact with the first source 250 and the active layer in contact with the drain 252 may be doped with a high concentration of impurities.

Referring to FIG. 4E, an upper insulating layer 260 is formed on the substrate on which the active layer 240 is formed. The upper insulating layer 260 may cover an upper surface and a side surface of the active layer 240. The thickness and dielectric constant of the upper insulating layer 260 may control the shape of the channel. The upper insulating layer 260 may be a silicon oxide layer or a silicon nitride layer.

Referring to FIG. 4F, a second source 270 may be formed to contact the first source 250 and cover a part of the upper insulating layer 260. The second source 270 may have a region overlapping the drain 252. The second source 270 may cover a region between the first source 250 and the drain 252. The second source 270 may be formed of the same material as the first source.

In the above, the present invention has been illustrated and described with respect to specific preferred embodiments, but the present invention is not limited to these embodiments, and the present invention claimed in the claims by one of ordinary skill in the art to which the present invention pertains. It includes all various types of embodiments that can be implemented without departing from the technical idea.

110: substrate
120: gate electrode
130: gate insulating film
140: active layer
150: first source
152: drain
160: upper insulating film
170: second source

Claims (13)

Board;
A gate electrode disposed on the substrate;
A gate insulating layer disposed to cover the gate electrode;
An active layer on the gate insulating layer;
A first source and a drain disposed on the active layer and spaced apart from each other around the gate electrode;
An upper insulating layer filling the space between the first source and the drain, covering a portion of the first source, and covering a portion of the drain; And
And a second source disposed to contact the first source and cover a portion of the upper insulating layer. The method of claim 1,
And the second source is disposed on the upper insulating layer to cover a space between the first source and the drain. The method of claim 1,
The active layer is a thin film transistor, characterized in that a-Si, LTPS, IGZO, or ZnO. The method of claim 1,
The gate electrode is a thin film transistor, characterized in that the doped silicon, ITO, or aluminum. The method of claim 1,
The first source, the drain, and the second source are a conductive metal or a metal alloy. The method of claim 1,
The second source is a thin film transistor, characterized in that having a region overlapping with the drain. Forming a gate electrode on the substrate;
Forming a gate insulating layer to cover the gate electrode;
Forming an active layer on the gate insulating layer;
Forming a first source and a drain disposed on the active layer and spaced apart from each other around the gate electrode;
Forming an upper insulating layer to fill a space between the first source and the drain, cover a portion of the first source, and cover a portion of the drain; And
And forming a second source disposed to contact the first source and cover a portion of the upper insulating layer. Board;
A gate electrode disposed on the substrate;
A gate insulating layer disposed to cover the gate electrode;
A first source and a drain disposed on the gate insulating layer and spaced apart from each other;
An active layer filling the space between the first source and the drain, covering a portion of the first source, and covering a portion of the drain;
An upper insulating layer disposed to cover the active layer; And
And a second source disposed to contact the first source and cover a portion of the upper insulating layer. The method of claim 8,
Wherein the second source is disposed to cover a space between the first source and the drain. The method of claim 8,
The active layer is a thin film transistor, characterized in that a-Si, LTPS, IGZO, or ZnO. The method of claim 1,
The first source, the drain, and the second source are a conductive metal or a metal alloy. The method of claim 1,
The second source is a thin film transistor, characterized in that having a region overlapping with the drain. Forming a gate electrode on the substrate;
Forming a gate insulating layer to cover the gate electrode;
Forming first sources and drains disposed on the gate insulating layer and spaced apart from each other;
Forming an active layer to fill a space between the first source and the drain, cover a part of the first source, and cover a part of the drain;
Forming an upper insulating layer to cover the active layer; And
And forming a second source to contact the first source and cover a portion of the upper insulating layer.

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