KR20220091376A - Display apparatus - Google Patents

Abstract

A display device according to an exemplary embodiment includes a substrate on which a plurality of sub-pixels are defined, a first insulating layer disposed on the substrate, and at least one metal pattern disposed on the first insulating layer and to which a DC voltage is applied. , a second insulating layer disposed on the metal pattern, and a plurality of light emitting devices disposed to overlap the metal pattern on the second insulating layer and including an anode, an organic layer, and a cathode. Accordingly, by reducing the capacitance variation of the light emitting devices disposed in the plurality of sub-pixels by the metal pattern, it is possible to improve the phenomenon caused by the color shift in the low grayscale.

Description

display device {DISPLAY APPARATUS}

The present invention relates to a display device, and more particularly, to a display device capable of improving a color shift and a color viewing angle in a low grayscale.

The organic light emitting display device is a self-emission type display device, and injects electrons and holes from an electrode for electron injection and an anode for hole injection, respectively, into an emission layer, and the injected electrons It is a display device using an organic light emitting device that emits light when excitons, which are combined with holes and excitons, fall from an excited state to a ground state. The organic light emitting diode display includes a top emission method, a bottom emission method, a dual emission method, etc. depending on a direction in which light is emitted, and a passive matrix type according to a driving method. ) and active matrix type.

Unlike a liquid crystal display (LCD), an organic light emitting display device does not require a separate light source, so it can be manufactured in a lightweight and thin form. In addition, the organic light emitting diode display is being researched as a next-generation display because it is advantageous in terms of power consumption due to low voltage driving and excellent color realization, response speed, viewing angle, and contrast ratio (CR).

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of minimizing color shift in a low grayscale.

Another object of the present invention is to provide a display device having improved light extraction efficiency.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to an exemplary embodiment includes a substrate on which a plurality of sub-pixels are defined, a first insulating layer disposed on the substrate, and at least one metal pattern disposed on the first insulating layer and to which a DC voltage is applied. , a second insulating layer disposed on the metal pattern, and a plurality of light emitting devices disposed to overlap the metal pattern on the second insulating layer and including an anode, an organic layer, and a cathode. Accordingly, it is possible to minimize color shift and improve a color viewing angle during low grayscale driving.

Details of other embodiments are included in the detailed description and drawings.

According to the present invention, the capacitance deviation of the light emitting device can be minimized through the metal pattern.

The present invention can improve a color viewing angle by reducing a color shift when a low grayscale image is displayed.

The present invention can improve light extraction efficiency through a microlens array structure of a light emitting device.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present invention.

1 is an enlarged plan view of a display device according to an exemplary embodiment.
2 is a cross-sectional view schematically illustrating a structure of a light emitting device of a display device according to an exemplary embodiment.
FIG. 3 is a schematic cross-sectional view taken along line III-III' of FIG. 1 .
4 is an enlarged plan view of a display device according to another exemplary embodiment.
FIG. 5 is a cross-sectional view taken along line V-V' of FIG. 4 .
6 is an enlarged plan view of a display device according to another exemplary embodiment.
7 is a cross-sectional view taken along line VII-VII' of FIG. 6 .
8 is a schematic cross-sectional view of a display device according to another exemplary embodiment.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different shapes, only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative and the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When 'includes', 'have', 'consists of', etc. mentioned in the present invention are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is construed as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between two parts unless 'directly' is used.

Reference to a device or layer “on” another device or layer includes any intervening layer or other device directly on or in the middle of the other device or layer.

Also, although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

The area and thickness of each component shown in the drawings are illustrated for convenience of description, and the present invention is not necessarily limited to the area and thickness of the illustrated component.

Each feature of the various embodiments of the present invention can be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments may be independently implemented with respect to each other or implemented together in a related relationship. may be

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an enlarged plan view of a display device according to an exemplary embodiment. In FIG. 1 , only the anode 140 and the metal pattern 130 are illustrated among the configurations disposed in the plurality of sub-pixels SP for convenience of explanation.

The display device 100 according to an exemplary embodiment includes a display area and a non-display area. The display area is an area in which a plurality of pixels are arranged to substantially display an image. A pixel including a light emitting area for displaying an image and a driving circuit for driving the pixel may be disposed in the display area. The non-display area surrounds the display area. The non-display area is an area in which an image is not substantially displayed, and various wirings, driving ICs, printed circuit boards, etc. for driving pixels and driving circuits disposed in the display area are disposed. For example, various ICs, such as a gate driver IC and a data driver IC, and wiring may be disposed in the non-display area.

The plurality of pixels are arranged in a matrix shape, and each of the plurality of pixels includes a plurality of sub-pixels SP. The plurality of sub-pixels SP are individual units that emit light, and a light emitting device is disposed in each of the plurality of sub-pixels SP. The plurality of sub-pixels SP includes a first sub-pixel SP1 , a second sub-pixel SP2 , and a third sub-pixel SP3 that emit light of different colors. For example, the first sub-pixel SP1 may be a blue sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a red sub-pixel.

The plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 may be alternately disposed in the same column or in the same row. For example, the first sub-pixel SP1 and the third sub-pixel SP3 are alternately arranged in the same column, and the first sub-pixel SP1 and the third sub-pixel SP3 are alternately arranged in the same row can be

The plurality of second sub-pixels SP2 are disposed in different columns and different rows from the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 . For example, a plurality of second sub-pixels SP2 are arranged in one row, and a plurality of first sub-pixels SP1 and a plurality of third sub-pixels SP3 are alternately arranged in a row adjacent to one row. can be placed as A plurality of second sub-pixels SP2 may be disposed in one column, and a plurality of first sub-pixels SP1 and a plurality of third sub-pixels SP3 may be alternately disposed in a column adjacent to one column. The plurality of first sub-pixels SP1 and the second sub-pixels SP2 may face each other in a diagonal direction, and the plurality of third sub-pixels SP3 and the second sub-pixels SP2 may also face each other in a diagonal direction. Accordingly, the plurality of sub-pixels SP may be arranged in a grid shape.

However, in FIG. 1 , the plurality of first sub-pixels SP1 and the plurality of third sub-pixels SP3 are disposed in the same column and in the same row, and the plurality of second sub-pixels SP2 includes the plurality of first sub-pixels. Although it is illustrated that the plurality of sub-pixels SP are disposed in different columns and different rows from those of SP1 and the plurality of third sub-pixels SP3, the arrangement of the plurality of sub-pixels SP is not limited thereto.

Referring to FIG. 1 , the area of the first sub-pixel SP1 may be greater than the area of the second sub-pixel SP2 and the area of the third sub-pixel SP3 . In detail, the area of the emission area of the first sub-pixel SP1 may be greater than the area of the emission area of the second sub-pixel SP2 and the area of the emission area of the third sub-pixel SP3 . In addition, the area of the second sub-pixel SP2 may be larger than that of the third sub-pixel SP3 , and the area of the emission area of the second sub-pixel SP2 is that of the emission area of the third sub-pixel SP3 . may be larger than the area.

Hereinafter, the light emitting device ED disposed in the sub-pixel SP of the display device 100 according to an exemplary embodiment will be described in more detail with reference to FIG. 2 .

2 is a cross-sectional view schematically illustrating a structure of a light emitting device of a display device according to an exemplary embodiment.

In the display device according to the exemplary embodiment of the present invention, a light emitting element is disposed in each of the plurality of sub-pixels SP. The light emitting device includes a first light emitting device ED1 disposed in the first sub-pixel SP1 , a second light emitting device ED2 disposed in the second sub-pixel SP2 , and a second light emitting device disposed in the third sub-pixel SP3 . 3 light emitting element ED3 is included. Since the first light emitting device ED1 is disposed in the first sub-pixel SP1 which is a blue sub-pixel, it may be a blue light-emitting device, and the second light emitting device ED2 is disposed in the second sub-pixel SP2 which is a green sub-pixel. Therefore, it may be a green light emitting device, and the third light emitting device ED3 may be a red light emitting device because it is disposed in the third sub pixel SP3 which is a red sub pixel, but is not limited thereto.

The first light emitting device ED1 includes a first anode 141 , an organic layer 150 , and a cathode. Here, the organic layer 150 of the first light emitting device ED1 may include a first hole transport layer 152 , a second hole transport layer 152 , a first emission layer 155_1 , and an electron transport layer 156 .

The second light emitting device ED2 includes a second anode 142 , an organic layer 150 , and a cathode. Here, the organic layer 150 of the second light emitting device ED2 includes a hole injection layer 151 , a first hole transport layer 152 , a third hole transport layer 153 , a second emission layer 155_2 , and an electron transport layer 156 . ) is included.

The third light emitting device ED3 includes a third anode 143 , an organic layer 150 , and a cathode 160 . Here, the organic layer 150 of the third light emitting device ED3 includes a hole injection layer 151 , a first hole transport layer 152 , a fourth hole transport layer 154 , a third emission layer 155_3 , and an electron transport layer 156 . includes

In FIG. 2 , one light emitting layer 155 is disposed for each light emitting device ED, but two light emitting layers may be disposed.

The anode 140 includes a first anode 141 , a second anode 142 , and a third anode 143 . The anode may be composed of a first anode 141, a second anode 142, and a third anode 143 spaced apart by patterning.

The hole injection layer 151 is disposed on the anode 140 as a common layer to correspond to all of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 . The hole injection layer 151 may serve to facilitate hole injection, and may include HATCN (1,4,5,8,9,11-hexaazatriphenylene-hexanitrile), CuPc (cupper phthalocyanine), PEDOT (poly(3) ,4)-ethylenedioxythiophene), PANI (polyaniline) and NPD (N,N-dinaphthyl-N,N'-diphenylbenzidine), TPD (N,N'-Bis(3-methylphenyl)-N,N"-bis(phenyl) )-benzidine), α-NPB(Bis[N-(1-naphthyl)-N-phenyl]benzidine), TDAPB(1,3,5-tris(4-diphenylaminophenyl)benzene), TCTA(Tris(4-carbazoyl) -9-yl)triphenylamine), spiroTAD(2,2',7,7"-Tetrakis(N,N-diphenylamino)-9,9-spirobifluorene) and CBP(4,4'-bis(carbazol-9-yl) ) may be made of at least one material of biphenyl), but is not limited thereto.

The first hole transport layer 152 is disposed on the hole injection layer 151 as a common layer to correspond to all of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 . The first hole transport layer 152 serves to facilitate hole transport, and includes N,N-dinaphthyl-N,N'-diphenylbenzidine (NPD), N,N'-bis-(3-methylphenyl)- N,N'-bis-(phenyl)-benzidine), spiro-TAD(2,2',7,7"-Tetrakis(N,N-diphenylamino)-9,9-spirobifluorene) and MTDATA(4,4' ,4"-Tris(N-3-methylphenyl-N-phenyl-amino)-triphenylamine) may be formed of any one or more, but is not limited thereto.

The second hole transport layer 153 is disposed on the first hole transport layer 152 in the second sub-pixel SP2 . Also, the third hole transport layer 154 is disposed on the first hole transport layer 152 in the third sub-pixel SP3 . The second hole transport layer 153 and the third hole transport layer 154 serve to facilitate hole transport, and NPD (N,N-dinaphthyl-N,N'-diphenylbenzidine), TPD (N,N'- bis-(3-methylphenyl)-N,N'-bis- (phenyl)-benzidine), spiro-TAD(2,2',7,7' and MTDATA(4,4',4"-Tris(N-) 3-methylphenyl-N-phenyl-amino)-triphenylamine), but is not limited thereto.

In addition, the thickness of each of the second hole transport layer 153 and the third hole transport layer 154 may form an optical distance of a micro cavity of the second sub-pixel SP2 and the third sub-pixel SP3. can More specifically, the thickness of the second hole transport layer 153 is a thickness that can form a microcavity structure between the second anode 142 and the cathode 160 of the second sub-pixel, and the third hole transport layer 154 The thickness of may be a thickness capable of forming a microcavity structure between the third anode 143 and the cathode 160 of the third sub-pixel SP3 .

The first emission layer 155_1 is disposed on the first hole transport layer 152 in the first sub-pixel SP1 . The first light emitting layer 155_1 may include a light emitting material emitting blue light, and the light emitting material may be formed using a phosphorescent material or a fluorescent material. More specifically, the blue light emitting layer may include a host material including CBP or mCP, and FIrPic(bis(3,5,-difluoro-2-(2-pyridyl)phenyl-(2-carboxypyridyl)iridium(III)) may be made of a phosphorescent material including a dopant material including (N,N-di-phenyl)amino]styryl-benzene), PFO (polyfluorene)-based polymer, PPV (polyphenylenevinylene)-based polymer may be formed of a fluorescent material including any one, but is not limited thereto.

The second emission layer 155_2 is disposed on the second hole transport layer 152 in the second sub-pixel SP2 . The second light emitting layer 155_2 may include a green light emitting material, and the light emitting material may be formed using a phosphorescent material or a fluorescent material. More specifically, the green light emitting layer may include a host material including CBP or mCP, and Ir(ppy)3(tris(2-phenylpyridine)iridium(III)) or Ir(ppy)2(acaa)(bis(2) - May be made of a phosphorescent material containing a dopant material such as an iridium complex containing phenylpyridine)(acetylacetonate)iridium(III), and, unlike this, a fluorescent material containing Alq3(tris(8-hydroxyquinolino)aluminium) may be made, but is not limited thereto.

The third emission layer 155_3 is disposed on the third hole transport layer 154 of the third sub-pixel SP3 region. The third light emitting layer 155_3 may include a red light emitting material, and the light emitting material may be formed using a phosphorescent material or a fluorescent material. More specifically, the red light emitting layer may include a host material including CBP (carbazole biphenyl) or mCP (1,3-bis(carbazol-9-yl)benzene), and Ir(btp)2(acac)(bis( 2-benzo[b]thiophen-2-ylpyridine)(acetylacetonate)iridium(III)), Ir(piq)2(acac)(bis(1-phenylisoquinoline)(acetylacetonate)iridium(III)), Ir(piq)3 (tris(1-phenylquinoline)iridium(III)) and PtOEP (octaethylporphyrin platinum) may be formed of a phosphor containing a dopant containing any one or more, in contrast to this, PBD:Eu(DBM)3(Phen) or Perylene It may be made of a fluorescent material containing, but is not limited thereto.

The electron transport layer 156 corresponds to all of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 , the first emission layer 155_1 , the second emission layer 155_2 , and the third emission layer It is placed on (155_3). The electron transport layer 156 may serve to transport and inject electrons, and the thickness of the electron transport layer 156 may be adjusted in consideration of electron transport characteristics. The electron transport layer 156 serves to facilitate the transport of electrons, and includes Liq (8-hydroxyquinolinolato-lithium), Alq3 (tris(8-hydroxyquinolinato)aluminium), PBD (2-(4-biphenylyl)-5-( 4-tert-butylpheny)-1,3,4oxadiazole), TAZ(3-(4-biphenyl)4-phenyl-5-tert-butylphenyl-1,2,4-triazole), spiro-PBD and BAlq(bis(bis( 2-methyl-8-quinolinolate)-4-(phenylphenolato)aluminium), but is not limited thereto.

The thickness of the organic layer 150 disposed on each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 is the first sub-pixel SP1 , the second sub-pixel SP2 , It may increase in the order of the third sub-pixel SP3 . As described above, the organic layer 150 disposed in the first sub-pixel SP1 is the hole injection layer 151 , the first hole transport layer 152 , the first emission layer 155_1 , and the electron transport layer 156 . The organic layer 150 disposed in the second sub-pixel SP2 includes a hole injection layer 151 , a first hole transport layer 152 , a second hole transport layer 153 , a second emission layer 155_2 , and an electron transport layer 156 . Therefore, the thickness of the organic layer 150 disposed in the second sub-pixel SP2 may be greater than the thickness of the organic layer 150 disposed in the first sub-pixel SP1 . In addition, the organic layer 150 disposed in the third sub-pixel SP3 includes a hole injection layer 151 , a first hole transport layer 152 , a third hole transport layer 154 , a third emission layer 155_3 and an electron transport layer ( 156), the thickness of the organic layer 150 disposed in the third sub-pixel SP3 may be greater than the thickness of the organic layer 150 disposed in the third sub-pixel SP3.

The cathode 160 is disposed on the electron transport layer 156 to correspond to all of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 . Light is repeatedly reflected in the cavity between the anode 140 and the cathode 160 due to a micro-cavity effect, that is, a micro-resonance effect, in which repeated reflection occurs between the anode 140 and the cathode 160 . This will increase the light efficiency.

Hereinafter, a plurality of sub-pixels SP of the display device 100 according to an exemplary embodiment will be described in more detail with reference to FIG. 3 .

FIG. 3 is a schematic cross-sectional view taken along line III-III' of FIG. 1 .

Referring to FIG. 3 , the display device 100 according to an embodiment of the present invention includes a substrate 110 , a buffer layer 111 , a gate insulating layer 112 , an interlayer insulating layer 113 , a passivation layer 114 , It includes a first insulating layer 115 , a second insulating layer 116 , a bank 117 , a thin film transistor 120 , a metal pattern 130 , and a light emitting device ED. In FIG. 3 , the organic layer 150 of FIG. 2 is illustrated as a single layer for convenience of explanation.

Referring to FIG. 3 , the substrate 110 is a support member for supporting other components of the display device 100 , and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. In addition, the substrate 110 may include a polymer or plastic such as polyimide (PI), or may be made of a material having flexibility.

A buffer layer 111 is disposed on the substrate 110 . The buffer layer 111 may reduce penetration of moisture or impurities through the substrate 110 . The buffer layer 111 may be formed of, for example, a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of the substrate 110 or the type of the transistor, but is not limited thereto.

The thin film transistor 120 is disposed on the buffer layer 111 . The thin film transistor 120 includes an active layer 122 , a gate electrode 121 , a source electrode 124 , and a drain electrode 123 .

The active layer 122 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto. For example, when the active layer 122 is formed of an oxide semiconductor, the active layer 122 includes a channel region, a source region, and a drain region, and the source region and the drain region may be a conductive region, but is limited thereto. doesn't happen

A gate insulating layer 112 is disposed on the active layer 122 . The gate insulating layer 112 is an insulating layer for insulating the active layer 122 and the gate electrode 121 , and may be formed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is limited thereto. doesn't happen

A gate electrode 121 is disposed on the gate insulating layer 112 . The gate electrode 121 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present invention is not limited thereto.

An interlayer insulating layer 113 is disposed on the gate electrode 121 . A contact hole for connecting the source electrode 124 and the drain electrode 123 to the active layer 122 is formed in the interlayer insulating layer 113 . The interlayer insulating layer 113 may be formed of a single layer or a multilayer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

A source electrode 124 and a drain electrode 123 are disposed on the interlayer insulating layer 113 . The source electrode 124 and the drain electrode 123 spaced apart from each other may be electrically connected to the active layer 122 . The source electrode 124 and the drain electrode 123 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or the like. It may be composed of an alloy for, but is not limited thereto. Meanwhile, although not shown in the drawings, the source electrode 124 may be electrically connected to the high potential power wiring to receive the high potential power signal EVDD. The high-potential power wiring may be disposed in the form of a stripe and/or a mesh in the area where the pixels are disposed.

A first insulating layer 115 is disposed on the passivation layer 114 . The first insulating layer 115 is disposed on the transistor 120 , and is an insulating layer for planarizing the upper portion of the substrate 110 , and may be a planarization layer, but is not limited thereto. When the first insulating layer 115 is a planarization layer, the first insulating layer 115 may be made of an organic material, for example, as a single layer or a multilayer of polyimide or photo acryl. may be configured, but is not limited thereto.

A metal pattern 130 is disposed on the first insulating layer 115 . The metal pattern 130 is a configuration for adjusting a variation in capacitance for each light emitting device ED. The metal pattern 130 may be disposed to overlap the anode 140 under the anode 140 of the light emitting device ED to form a capacitor with the anode 140 .

In order to form a capacitor between the metal pattern 130 and the anode 140 , a voltage may be applied to the metal pattern 130 . For example, the metal pattern 130 may be configured to apply a DC voltage. In this case, the DC voltage may be applied from a separate DC power source. In addition, the metal pattern 130 may be configured such that the same voltage as that of the cathode 160 is applied. When the same voltage as that of the cathode 160 is applied to the metal pattern 130 , the metal pattern 130 may be electrically connected to the low potential power wiring to receive the low potential power signal EVSS. In addition, the metal pattern 130 may be electrically connected to a high potential power wiring (not shown) to receive the high potential power signal EVDD. For example, in the organic light emitting diode display, pixels including the light emitting element ED and the thin film transistor 120 are arranged in a matrix form, and the luminance of an image implemented in the pixels is adjusted according to the grayscale of the image data. The thin film transistor 120 is connected to a high potential power line to receive high potential pixel power, and differently generates a driving current flowing through the light emitting device ED according to a voltage applied between its gate electrode and a source electrode. The amount of light emitted from the light emitting device ED and the luminance of the image are determined according to the driving current. The high-potential power wiring may be disposed in a stripe shape and/or a mesh shape in an area in which pixels are disposed.

The area of the metal pattern 130 overlapping the anode 140 disposed in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 is the first sub-pixel SP1, The thickness of the organic layer 150 disposed on each of the second sub-pixel SP2 and the third sub-pixel SP3 may increase as the thickness increases. As described above, the thickness of the organic layer 150 disposed on each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 is equal to the thickness of the first sub-pixel SP1 , the second sub-pixel SP1 , and the second sub-pixel SP3 . Since the pixel SP2 and the third sub-pixel SP3 increase in order, the area of the anode 140 overlapping the metal pattern 130 is the first sub-pixel SP1 , the second sub-pixel SP2 , and the third It may increase in the order of the sub-pixels SP3.

The area of the anode 140 overlapping the metal pattern 130 may be determined by the number of the metal patterns 130 overlapping the anode 140 . Specifically, a plurality of metal patterns 130 having the same upper surface area are metal overlapping the anode 140 of each of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 . The number of patterns 130 may increase in the order of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 . For example, as shown in FIGS. 1 and 3 , the number of metal patterns 130 overlapping the anode 140 of the first sub-pixel SP1 is one, and the anode of the second sub-pixel SP2 is one. The number of metal patterns 130 overlapping with 140 may be two, and the number of metal patterns 130 overlapping with the anode 140 of the third sub-pixel SP3 may be three. However, this is for convenience of description and the number of the metal patterns 130 is not limited thereto.

A second insulating layer 116 is disposed on the metal pattern 130 . The second insulating layer 116 is an insulating layer for planarizing the upper portion of the substrate 110 , and may be a planarization layer, but is not limited thereto. When the second insulating layer 116 is a planarization layer, the second insulating layer 116 may be made of an organic material, for example, as a single layer or a multilayer of polyimide or photo acryl. may be configured, but is not limited thereto.

A plurality of light emitting devices ED are disposed in each of the plurality of sub-pixels SP on the second insulating layer 116 . Each of the light emitting devices ED includes an anode 140 , an organic layer 150 , and a cathode 160 .

The anode 140 is disposed on the second insulating layer 116 . The anode 140 may be electrically connected to the thin film transistor 120 to receive a driving current. Since the anode 140 supplies holes to the organic layer 150 , it may be made of a conductive material having a high work function. The anode 140 may be formed of, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

Meanwhile, the display device 100 may be implemented in a top emission method or a bottom emission method. In the case of the top emission method, a metal material having excellent reflection efficiency is provided under the anode 140 so that light emitted from the organic layer 150 is reflected by the anode 140 and is directed upward, that is, toward the cathode 160 side. , for example, a reflective layer made of a material such as aluminum (Al) or silver (Ag) may be added. Conversely, when the display device 100 is a bottom emission type, the anode 140 may be formed of only a transparent conductive material. Hereinafter, it is assumed that the display device 100 according to an embodiment of the present invention is a top emission type.

The area of the anode 140 of the first sub-pixel SP1 may be greater than the area of the anode 140 of the second sub-pixel SP2 and the area of the anode 140 of the third sub-pixel SP3. Also, the area of the anode 140 of the second sub-pixel SP2 may be larger than the area of the anode 140 of the third sub-pixel SP3.

A bank 117 is disposed on the anode 140 and the second insulating layer 116 . The bank 117 is an insulating layer disposed between the plurality of sub-pixels SP to separate the plurality of sub-pixels SP. Bank 117 includes an opening exposing a portion of anode 140 . The bank 117 may be formed of an organic insulating material disposed to cover an edge or an edge portion of the anode 140 . The bank 117 may be made of, for example, polyimide, acryl, or benzocyclobutene (BCB)-based resin, but is not limited thereto.

An organic layer 150 is disposed on the anode 140 and the bank 117 . Since the organic layer 150 has been described in detail with reference to FIG. 2 above, a redundant description thereof will be omitted.

A cathode 160 is disposed on the organic layer 150 . Since the cathode 160 supplies electrons to the organic layer 150 , it may be made of a conductive material having a low work function. The cathode 160 may be formed as one layer across the plurality of sub-pixels SP. That is, the cathode 160 of each of the plurality of sub-pixels SP may be integrally formed in a shared manner by being connected to each other. The cathode 160 is formed of, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a metal alloy such as MgAg or a ytterbium (Yb) alloy. and may further include a metal doped layer, but is not limited thereto. Meanwhile, although not shown in the drawings, the cathode 160 may be electrically connected to the low potential power wiring to receive the low potential power signal EVSS.

In a display device, a structure for implementing a micro-cavity is applied to improve light efficiency. In this case, the thickness of the organic layer 150 in the third sub-pixel SP3 for emitting red light having a long wavelength is the thickest, and the organic layer 150 in the first sub-pixel SP1 for emitting blue light having a short wavelength. The thickness of the organic layer 150 in the second sub-pixel SP2 for emitting green light may be medium.

In addition, the light emitting efficiency of the light emitting layer for emitting blue light, the light emitting layer for emitting green light, and the light emitting layer for emitting red light may be different. In particular, in the currently used material of the light emitting layer, the light emitting efficiency of the first light emitting layer 155_1, which is the light emitting layer for emitting blue light, is the lowest, and the light emitting efficiency of the third light emitting layer 155_3 which is the light emitting layer for emitting red light is the highest, and green light The light emitting efficiency of the second light emitting layer 155_2, which is a light emitting layer for emitting light, may be medium. Accordingly, in order to match the luminous efficiency of each sub-pixel SP, the size of the sub-pixels in the order of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 , that is, , the size of the anode 140 defining the light emitting region may be reduced.

Accordingly, the magnitude of the capacitance formed between the anode 140 and the cathode 160 in each sub-pixel SP may be different. The magnitude of the capacitance between the electrodes is proportional to the area of the electrodes and inversely proportional to the distance between the electrodes. Accordingly, the capacitance between the anode 140 and the cathode 160 in each sub-pixel SP in the order of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 is decreases. The variation in capacitance between the anode 140 and the cathode 160 in each sub-pixel SP causes a variation in RC delay in each light emitting device ED. Accordingly, a voltage filling deviation in each light emitting element ED may occur, and a color shift phenomenon at a low gray level may occur. For example, in the first sub-pixel SP1 in which the largest capacitance is formed, light emitted as magenta light having a low grayscale instead of blue light may be visually recognized.

Accordingly, in the display device 100 according to an embodiment of the present invention, the metal pattern 130 overlapping the light emitting device ED is disposed in each sub-pixel SP, and the metal pattern 130 is disposed in each sub-pixel SP. An RC delay deviation in the light emitting device ED may be compensated. Specifically, in the first sub-pixel SP1 having the largest capacitance between the anode 140 and the cathode 160 , the number of metal patterns 130 overlapping the anode 140 is the smallest, and the anode 140 and the cathode In the third sub-pixel SP3 having the smallest capacitance between 160 , the number of metal patterns 130 overlapping the anode 140 is the largest, and the capacitance between the anode 140 and the cathode 160 is intermediate. The number of metal patterns 130 overlapping the anode 140 in the second sub-pixel SP2 may be medium. Accordingly, a relatively large additional capacitance may be formed in the anode 140 of the sub-pixel having a relatively small capacitance, thereby compensating for a capacitance value in the light emitting device ED disposed in each of the plurality of sub-pixels SP. . Accordingly, in the display device 100 according to an embodiment of the present invention, the RC delay deviation between the sub-pixels can be compensated by using the metal pattern 130 overlapping the anode 140 in the plurality of sub-pixels SP. and it is possible to improve the color shift phenomenon in the low grayscale.

4 is an enlarged plan view of a display device according to another exemplary embodiment. FIG. 5 is a cross-sectional view taken along line V-V' of FIG. 4 . Compared to the display device 100 of FIGS. 1 to 3 , the display device 200 of FIGS. 4 and 5 has only the metal pattern 230 different, and other configurations are substantially the same, so a redundant description will be omitted.

Referring to FIG. 4 , the area of the metal pattern 230 overlapping the anode 140 may be determined by the area of the anode 140 . The area of the anode 140 overlapping the metal pattern 230 may be determined by the area of the metal pattern 230 overlapping the anode 140 . The metal pattern 230 may extend to overlap the anode 140 of the plurality of sub-pixels SP. Specifically, the metal pattern 230 is a first metal pattern (SP1) disposed to overlap any two sub-pixels SP among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. 231 ) and a second metal pattern 232 disposed to overlap the remaining one sub-pixel SP. Here, the first metal pattern 231 and the second metal pattern 232 are the anodes of any one of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 . An area overlapping the 140 may increase in the order of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 . For example, as illustrated in FIGS. 4 and 5 , the first metal pattern 231 overlapping the first sub-pixel SP1 and the third sub-pixel SP3 and the second sub-pixel SP2 overlapping each other When the second metal pattern 232 is disposed, the area of the metal pattern 230 overlapping the anode 140 of each sub-pixel SP is the smallest in the first sub-pixel SP1 and the third sub-pixel SP3 is the largest, and the second sub-pixel SP2 is the middle.

In the display device 200 according to another embodiment of the present invention, in each sub-pixel SP, the metal pattern 230 overlapping the light emitting element ED has a different area and is disposed in each sub-pixel SP. It is possible to compensate for the RC delay deviation in the light emitting device ED. Specifically, in the first sub-pixel SP1 having the largest capacitance between the anode 140 and the cathode 160, the area of the first metal pattern 231 overlapping the anode 140 is the smallest, and the anode 140 In the third sub-pixel SP3 having the smallest capacitance between the anode and the cathode 160 , the area of the first metal pattern 231 overlapping the anode 140 is the largest, and the capacitance between the anode 140 and the cathode 160 is The area of the second metal pattern 232 overlapping the anode 140 in the second sub-pixel SP2 having a medium size may be medium. Accordingly, a relatively large additional capacitance may be formed in the anode 140 of the sub-pixel having a relatively small capacitance, thereby compensating for a capacitance value in the light emitting device ED disposed in each of the plurality of sub-pixels SP. . Accordingly, it is possible to compensate for the RC delay deviation between sub-pixels and to improve the color shift phenomenon in the low grayscale.

In order to form a capacitor between the first and second metal patterns 231 and 232 and the anode 140 , a voltage may be applied to the first and second metal patterns 231 and 232 . For example, the first metal pattern 231 and the second metal pattern 232 may be configured to apply a DC voltage. In this case, the DC voltage may be applied from a separate DC power source. Also, the first metal pattern 231 and the second metal pattern 232 may be configured such that the same voltage as that of the cathode 160 is applied. When the same voltage as that of the cathode 160 is applied to the first metal pattern 231 and the second metal pattern 232 , the first metal pattern 231 and the second metal pattern 232 are electrically connected to the low potential power wiring. connected to can receive a low potential power signal (EVSS). Also, the first metal pattern 231 and the second metal pattern 232 may be electrically connected to a high potential power line (not shown) to receive the high potential power signal EVDD. For example, in the organic light emitting diode display, pixels including the light emitting element ED and the thin film transistor 120 are arranged in a matrix form, and the luminance of an image implemented in the pixels is adjusted according to the grayscale of the image data. The thin film transistor 120 is connected to a high potential power line to receive high potential pixel power, and differently generates a driving current flowing through the light emitting device ED according to a voltage applied between its gate electrode and a source electrode. The amount of light emitted from the light emitting device ED and the luminance of the image are determined according to the driving current. The high-potential power wiring may be disposed in a stripe shape and/or a mesh shape in an area in which pixels are disposed.

6 is an enlarged plan view of a display device according to another exemplary embodiment. 7 is a cross-sectional view taken along line VII-VII' of FIG. 6 . Compared to the display device 100 of FIGS. 1 to 3 , the display device 300 of FIGS. 6 and 7 has only a different metal pattern 330 , and other configurations are substantially the same, and thus a redundant description thereof will be omitted.

Referring to FIG. 6 , the area of the anode 140 overlapping the metal pattern 330 may be determined by the sum of the areas of the plurality of holes 331 of the metal pattern 330 overlapping the anode 140 . The metal pattern 330 may be disposed in a layer shape to overlap the anode 140 of the plurality of sub-pixels SP.

Referring to FIG. 7 , the metal pattern 330 is disposed on the entire upper surface of the first insulating layer 115 to overlap all of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 . It may be a single metal pattern 330 . An area overlapping the anode 140 of each sub-pixel SP may be changed according to the sum of the areas of the plurality of holes 331 . The sum of the areas of the plurality of holes 331 may decrease in the order of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 .

For example, as shown in FIG. 6 , when the area of each of the plurality of holes 331 is the same so that the sum of the areas of the plurality of holes 331 is proportional to the number of the plurality of holes 331 , the first sub-pixel The number of the plurality of holes 331 overlapping with SP1 is the largest, the number of the plurality of holes 331 overlapping with the third sub-pixel SP3 is the smallest, and the number of the plurality of holes overlapping with the second sub-pixel SP2 is the smallest. The number of holes 331 is medium. Accordingly, when the sum of the areas of the plurality of holes 331 increases in the order of the first sub-pixel SP1 , the second sub-pixel SP2 , and the third sub-pixel SP3 , the metal overlapping each anode 140 . The area of the pattern 330 may be reduced. However, this is for convenience of description, and the area and number of each of the plurality of holes 331 are not limited thereto.

In the display device 300 according to another embodiment of the present invention, the metal pattern 330 overlapping the light emitting element ED in each sub-pixel SP includes a plurality of holes 331 , and the plurality of holes By disposing the area sum of 331 differently, the RC delay deviation in the light emitting device ED disposed in each sub-pixel SP may be compensated for. Specifically, in the first sub-pixel SP1 having the largest capacitance between the anode 140 and the cathode 160 , the area of the metal pattern 330 overlapping the anode 140 is the smallest, and the anode 140 and the cathode In the third sub-pixel SP3 having the smallest capacitance between 160 , the area of the metal pattern 330 overlapping the anode 140 is the largest, and the capacitance between the anode 140 and the cathode 160 is intermediate. The area of the metal pattern 330 overlapping the anode 140 in the second sub-pixel SP2 may be in the middle. Accordingly, a relatively large additional capacitance may be formed in the anode 140 of the sub-pixel having a relatively small capacitance, thereby compensating for a capacitance value in the light emitting device ED disposed in each of the plurality of sub-pixels SP. . Accordingly, it is possible to compensate for the RC delay deviation between sub-pixels and to improve the color shift phenomenon in the low grayscale.

8 is a schematic cross-sectional view of a display device according to another exemplary embodiment. Compared to the display device 100 of FIGS. 1 to 3 , the display device 400 of FIG. 8 differs only in the second insulating layer 416 and the light emitting device ED, and other configurations are substantially the same and overlap. A description is omitted.

Referring to FIG. 8 , the second insulating layer 416 and the plurality of light emitting devices ED are arranged in a non-planar shape by the metal pattern 130 overlapping each of the light emitting devices ED. Accordingly, concave or convex portions may be formed in the plurality of light emitting devices ED to form a micro lens array (MLA) structure. Specifically, concave or convex portions are formed in the second insulating layer 416 , the anode 460 , the organic layer 450 , and the cathode 460 overlapping the metal pattern 130 . Accordingly, among the light incident on the anode 440 , the light incident with an incident angle equal to or less than the total reflection critical angle is reflected by the reflective layer and extracted out of the cathode 460 as it is. And, the light incident at an angle of incidence greater than or equal to the critical angle of total reflection is not trapped in the organic layer 450, but hits the concave or convex portion to change the optical path, so that the propagation angle of light becomes smaller than the critical angle of total reflection, and is extracted out of the cathode 460 do. That is, when the second insulating layer 416 and the plurality of light emitting devices ED are flat, the incident angle is greater than the total reflection critical angle and thus light that cannot be extracted to the outside may be extracted by the concave or convex portions. , the light extraction efficiency of the display device 400 may be improved.

In the display device 400 according to another embodiment of the present invention, the metal pattern 130 overlapping the light emitting device ED is disposed in each sub-pixel SP, and the light emission disposed in each sub-pixel SP is disposed. It is possible to compensate for the RC delay deviation in the device ED and to improve the color shift phenomenon in the low grayscale.

In addition, in the display device 400 according to another exemplary embodiment of the present invention, a microlens array structure is formed in the plurality of light emitting devices ED overlapping the metal pattern 130 to reduce the amount of light trapped inside the light emitting devices ED. It is possible to reduce the amount, so that the light extraction efficiency can be improved.

A display device according to various embodiments of the present disclosure may be described as follows.

A display device according to an embodiment of the present invention includes a substrate on which a plurality of sub-pixels are defined, a first insulating layer disposed on the substrate, at least one metal pattern disposed on the first insulating layer and to which a DC voltage is applied; A second insulating layer disposed on the metal pattern, and a plurality of light emitting devices disposed on the second insulating layer to overlap the metal pattern and including an anode, an organic layer, and a cathode.

According to another feature of the present invention, the metal pattern may be disposed to overlap the anode to form the anode and the capacitor.

According to another feature of the present invention, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel disposed in each of the sub-pixels. The area of the metal pattern overlapping the anode may increase as the thickness of the organic layer disposed in each of the first sub-pixel, the second sub-pixel, and the third sub-pixel increases.

According to another feature of the present invention, the first sub-pixel is a blue sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a red sub-pixel, and the first sub-pixel, the second sub-pixel and the second sub-pixel are The thickness of the organic layer disposed in each of the three sub-pixels may increase in the order of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

According to another feature of the present invention, the area of the anode of the first sub-pixel may be larger than the area of the anode of the second sub-pixel and the third sub-pixel.

According to still another feature of the present invention, the metal pattern includes a first metal pattern overlapping two sub-pixels among the first sub-pixel, the second sub-pixel, and the third sub-pixel, and a second metal pattern overlapping the remaining one sub-pixel. It may include patterns.

According to another feature of the present invention, the display device, wherein the area of the first metal pattern and the second metal pattern overlapping the anode of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel is different.

According to another feature of the present invention, the number of metal patterns is plural, and the number of metal patterns overlapping the anodes of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel is the number of the first sub-pixel, the second sub-pixel, It may increase in the order of the third sub-pixel.

According to another feature of the present invention, the second insulating layer may have a non-flat shape due to a metal pattern, and each of the plurality of light emitting devices may include a concave portion or a convex portion.

According to another feature of the present invention, the metal pattern is a single metal pattern overlapping all of the first sub-pixel, the second sub-pixel and the third sub-pixel, the metal pattern including a plurality of holes, the first sub-pixel; The sum of the area of the hole overlapping the anode of each of the second sub-pixel and the third sub-pixel may decrease in the order of the first sub-pixel, the second sub-pixel, and the third sub-pixel.

According to another feature of the present invention, the metal pattern may be configured such that the same voltage as that of the cathode is applied.

According to another feature of the present invention, it further comprises a transistor disposed on the substrate, the first insulating layer may be disposed on the transistor.

Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made within the scope without departing from the technical spirit of the present invention. . Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to illustrate, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100, 200, 300, 400: display device
110: substrate
111: buffer layer
112: gate insulating layer
113: interlayer insulating layer
114: passivation layer
115: first insulating layer
116, 416: second insulating layer
117: bank
120: thin film transistor
121: gate electrode
122: active layer
123: drain electrode
124: source electrode
130, 230, 330: metal pattern
231: first metal pattern
232: second metal pattern
140, 440: anode
141: first anode
142: second anode
143: third anode
150, 450: organic layer
151: hole injection layer
152: first hole transport layer
153: second hole transport layer
154: third hole transport layer
155: light emitting layer
155_1: first light emitting layer
155_2: second light emitting layer
155_3: third light emitting layer
156: electron transport layer
160, 460: cathode
331: Hall
ED: light emitting element
ED1: first light emitting element
ED2: second light emitting element
ED3: third light emitting element
SP: sub pixel
SP1: first sub-pixel
SP2: second sub-pixel
SP3: third sub-pixel

Claims (13)

a substrate on which a plurality of sub-pixels are defined;
a first insulating layer disposed on the substrate;
at least one metal pattern disposed on the first insulating layer and to which a DC voltage is applied;
a second insulating layer disposed on the metal pattern; and
and a plurality of light emitting devices disposed on the second insulating layer to overlap the metal pattern and including an anode, an organic layer, and a cathode. According to claim 1,
The metal pattern is disposed to overlap the anode to form a capacitor with the anode. According to claim 1,
The plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel;
An area of the metal pattern overlapping an anode disposed in each of the first sub-pixel, the second sub-pixel, and the third sub-pixel is in each of the first sub-pixel, the second sub-pixel, and the third sub-pixel. A display device, which increases as the thickness of the disposed organic layer increases. According to claim 1,
the first sub-pixel is a blue sub-pixel;
the second sub-pixel is a green sub-pixel;
the third sub-pixel is a red sub-pixel;
The thickness of the organic layer disposed on each of the first sub-pixel, the second sub-pixel, and the third sub-pixel increases in the order of the first sub-pixel, the second sub-pixel, and the third sub-pixel. 5. The method of claim 4,
An area of an anode of the first sub-pixel is larger than an area of an anode of the second sub-pixel and the third sub-pixel. 6. The method of claim 5,
An area of an anode of the second sub-pixel is larger than an area of an anode of the third sub-pixel. According to claim 1,
the metal pattern includes a first metal pattern overlapping two sub-pixels of the first sub-pixel, the second sub-pixel, and the third sub-pixel, and a second metal pattern overlapping the remaining one sub-pixel;
and areas of the first metal pattern and the second metal pattern overlapping an anode of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel are different from each other. According to claim 1,
The metal pattern is plural,
The number of the metal patterns overlapping the anodes of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel increases in the order of the first sub-pixel, the second sub-pixel, and the third sub-pixel. , display. 9. The method of claim 8,
The second insulating layer has a non-flat shape by the metal pattern,
Each of the plurality of light emitting elements includes a concave portion or a convex portion. According to claim 1,
the metal pattern is a single metal pattern overlapping all of the first sub-pixel, the second sub-pixel, and the third sub-pixel;
The metal pattern includes a plurality of holes,
The sum of the area of the hole overlapping the anode of each of the first sub-pixel, the second sub-pixel, and the third sub-pixel decreases in the order of the first sub-pixel, the second sub-pixel, and the third sub-pixel. , display. According to claim 1,
The metal pattern is configured such that the same voltage as that of the cathode is applied. According to claim 1,
Further comprising a transistor disposed on the substrate,
and the first insulating layer is disposed on the transistor. 13. The method of claim 12,
and a high-potential power wiring disposed on the substrate to supply high-potential power to the plurality of sub-pixels;
The Sanggi metal pattern is configured such that high potential power is applied from the high potential power wiring.

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