KR20220127113A - Encoding and decoding apparatus and method for implementing maximum transition-avoidance coding with minimum overhead - Google Patents

Abstract

An encoding and decoding apparatus and method for implementing maximum transition-avoidance coding with minimum overhead are described. An exemplary apparatus includes subblock lookup tables indicating correlations with symbols with some bit values in a data burst, a combination lookup table for selectively concatenating subblock lookup tables based on remaining bit values of the data burst, and receiving Encoding and/or decoding is performed using a codeword decoding lookup table that designates subblock lookup tables corresponding to symbols of each of the codewords.

Description

{Apparatuses and methods for encoding and decoding to implement maximun transition avoidance (MTA) coding with minimum overhead}

The present invention relates to applications and methods, and more particularly to an encoding and decoding apparatus and method for implementing maximum transition-avoidance coding with minimum overhead.

Efforts to make computing systems more powerful and more power efficient are advancing interface communications, improving throughput while not increasing power consumption, ideally reducing it. Some systems implement Pulse-Amplitude Modulation 4-Level (PAM-4) signaling. PAM-4 can be used to convert a 2-bit stream into a single multi-level signal having 4-levels. The PAM-4 signaling system may use Maximum Transition Avoidance (MTA) coding to remove a maximum voltage transition between PAM-4 symbols on an interface line. MTA coding may reduce inter-symbol interference (ISI) and crosstalk that cause signal distortion.

Among operations performed in a computing system, a memory access operation for writing and/or reading data is important. The memory access operation is performed based at least in part on the input/output structure of the memory, and when the memory bandwidth is increased to 32-bit or more, the memory may be accessed using a data modulation method. For example, if PAM-4 signaling is used, a large overhead may be generated due to an increase in the number of signal lines and/or a chip area required for MTA coding. Accordingly, there is a need for an apparatus and method that can be implemented with minimal overhead in order to transmit and receive 32-bit data through PAM-4 signaling to which MTA is applied.

It is an object of the present invention to provide an encoding and decoding apparatus and method for implementing maximum transition-avoidance coding with minimum overhead.

An apparatus according to embodiments of the present invention comprises a transmitter for a data bus, the transmitter comprising an encoder for converting data bursts to be transmitted over the data bus into codewords composed of symbols. The encoder includes logic circuitry for correlating the data bursts with the symbols. the logic circuit comprises a plurality of sub-block lookup tables sorted according to the number of codeword mappings, the codeword mappings representing the correlation of some bit values in the data bursts with the symbols; and a combination lookup table for selectively concatenating encoding results according to the plurality of subblock lookup tables based on the remaining bit values of each of the data bursts. The encoder is configured to provide the codeword corresponding to the data bursts to the data bus using the combinational lookup table and the plurality of subblock lookup tables.

A method of transmitting data according to embodiments of the present invention includes receiving data bursts of m bits to be transmitted on a data line; sending the value of p(m>p) bits of the m bits of each data burst to a data bus inversion (DBI) signal line; generating a codeword of the DBI signal line by performing q:(q+k) bit encoding on q bits that are the sum of the p bits on the DBI signal line; and performing (m-p):m bit encoding on the remaining (m-p) bits of each of the data bursts to generate a codeword of the data line.

An apparatus according to embodiments of the present invention comprises a receiver for a data bus, said receiver comprising a decoder for converting codewords composed of symbols received over said data bus into data bursts. The decoder includes logic circuitry that indicates a correlation between the symbols and the data bursts. The logic circuit comprises: a codeword decoding lookup table configured to provide a lookup table mapping specifying subblock lookup tables corresponding to the symbols of each of the codewords; the sub-block lookup tables classified according to the number of codeword mappings, the codeword mappings indicate the correlation between the symbols and some bit values in the data bursts; and a combination lookup table for selectively concatenating subblock lookup tables designated by the lookup table mapping. The decoder restores the data bursts corresponding to the codeword using the codeword decoding lookup table, the subblock lookup tables and the combination lookup table.

The present invention can reduce the overhead by reducing the chip area by selectively concatenating a plurality of sub-block lookup tables for storing codeword mappings used for encoding and/or decoding. In addition, since an additional signal line for MTA coding is not required, the additional signal line can be used for data error detection, thereby improving encoding and/or decoding performance.

1 is a block diagram conceptually illustrating a transmitter and a receiver according to embodiments of the present invention.
FIG. 2 is a diagram for explaining 7-8 bit encoding used in the PAM-4 encoder of FIG. 1 .
FIG. 3 is a diagram illustrating lookup tables of the PAM-4 encoder of FIG. 1 .
4 and 5A to 5C are diagrams illustrating codeword encoding using the combination lookup table and subblock lookup tables of FIG. 3 .
6 is a flowchart illustrating an operation method of the PAM-4 encoder of FIG. 1 .
FIG. 7 is a diagram illustrating lookup tables of the PAM-4 decoder of FIG. 1 .
FIG. 8 is a view for explaining a codeword decoding lookup table of FIG. 7 .
9 is a flowchart illustrating an operation method of the PAM-4 decoder of FIG. 1 .
FIG. 10 is a diagram for explaining an encoding method of a 32-bit data burst using the 7:8-bit encoding of FIG. 2 .
11 is a diagram for explaining a data burst encoding method according to an embodiment of the present invention.
12 to 14 are diagrams for explaining a 32-bit data burst structure according to the encoding method of FIG. 11 .
15 is a block diagram of a first example of a memory system including an encoding and decoding apparatus according to embodiments of the present invention.
16 is a block diagram illustrating a part of a memory device according to an embodiment of the present invention.
17 is a block diagram of a second example of a memory system including an encoding and decoding apparatus according to embodiments of the present invention.

1 is a block diagram conceptually illustrating a transmitter and a receiver according to embodiments of the present invention.

Referring to FIG. 1 , a receiver 120 may communicate with a transmitter 110 through a channel line 130 . The channel line 130 is a plurality of signal lines that physically or electrically connect the transmitter 110 and the receiver 120 . Transmitter 110 , receiver 120 , and channel line 130 may support PAM-4 signaling, which converts 2-bit streams into a single multi-level signal having 4-levels.

The transmitter 110 may include a PAM-4 encoder 112 that converts data bursts to be transmitted to the receiver 120 into PAM-4 symbols. The PAM-4 encoder 112 may perform encoding on the data bursts to generate PAM-4 symbols. The transmitter 110 may further include a driver for driving the PAM-4 symbols onto the channel line 130 . The transmitter 110 may transmit PAM-4 symbols to the receiver 120 through the channel line 130 .

The PAM-4 encoder 112 may include logic circuitry 114 for correlating the data bursts with the PAM-4 symbols. Logic circuitry 114 may include lookup tables configured to have minimal overhead. The lookup tables may be implemented with registers (or storage elements) that store the correlation between data bursts and PAM-4 symbols. The PAM-4 encoder 112 may convert data bursts into PAM-4 symbols using lockup tables.

The receiver 120 may include a PAM-4 decoder 122 that receives the PAM-4 symbols and decodes the received PAM-4 symbols. The PAM-4 decoder 122 may include a logic circuit 124 configured to decode the PAM-4 symbols to recover data bursts of two bit streams. Logic circuitry 124 may include lookup tables configured to decode PAM-4 symbols to recover data bursts of two-bit streams. Lookup tables may be implemented with registers that store correlations of PAM-4 symbols with data bursts. The PAM-4 decoder 122 may reconstruct the PAM-4 symbols into data bursts using the lockup tables. Some of the lockup tables of the PAM-4 decoder 122 may be configured the same as the lockup tables of the PAM-4 encoder 112 .

FIG. 2 is a diagram for explaining 7-8 bit encoding used in the PAM-4 encoder of FIG. 1 .

Referring to FIG. 2 , a 7:8 bit encoding 200 between user data 202 and encoded data 204 is shown. User data 202 may be referred to as original data. For user data 202 and encoded data 204, each row DQ[i] represents a serial data line.

In user data 202, 16-bit data bursts are organized on each DQ[i] serial data line, and columns are organized into sequential 2-bit positions within the 16-bit data bursts. For example, the second and third bits of each data burst are denoted by column labeled d[2:3]. Each 16-bit data burst is represented by each of 2 1/2 data bursts of 8 bits. For example, on the serial data line DQ[0], the 16-bit data burst is the 1st 1/2 data burst d0[0]:d0[7:1] and the 2nd 1/2 data burst d0[8]: It is divided by d0[15:9]. Each half data burst is further divided into 1-bit:7-bit pairs. For example, on serial data line DQ[0], the first 1/2 data burst d0[0]:d0[7:1] is a 1-bit value of d0[0] and a 7-bit value of d0[7 : 1].

In encoded data 204, DQ[i] rows represent serial data lines, DBI rows represent data bus inversion (DBI) signal lines, and columns represent bit columns (s[i]) representing symbols (s[i]). bit strings). For example, s[0] represents the first 2-bit PAM4 symbol on each serial data line, and s[1] represents the second 2-bit PAM4 symbol.

The 7:8 bit encoding 200 may encode a pair of 1-bit data values at any bit position of one serial data line into a PAM-4 symbol on a DBI signal line. For example, data d0[0] and d0[8] on serial data line DQ[0] are encoded as 2-bit PAM-4 symbols on the DBI signal line, and data d1[ on serial data line DQ[1] 0] and d1[8] may be encoded as 2-bit PAM-4 symbols on the DBI signal line.

According to an embodiment, in 7:8 bit encoding 200, a 2-bit PAM-4 symbol on a DBI signal line converts a pair of 1-bit data values of other serial data lines into a PAM-4 symbol on a DBI signal line. can code For example, data d0[0] of serial data line DQ[0] and data d1[0] of serial data line DQ[1] are encoded as 2-bit PAM-4 symbols on the DBI signal line. Similarly, data d2[0] of serial data line DQ[2] and data d3[0] of serial data line DQ[3] are encoded as 2-bit PAM-4 symbols on the DBI signal line.

In the 7:8 bit encoding 200, the remaining 7 bits not used as PAM-4 symbols of the DBI signal line of each 1/2 data burst are encoded as 4 PAM-4 symbols on the corresponding serial data line. The four PAM-4 symbols consist of 8 bits and may be referred to as a codeword. For example, user data d0[7:1] is encoded into codeword c0[7:0] on serial data line DQ[0]. A codeword for each 7 bits of user data may be represented by 4 PAM-4 symbols. User data d0[7:1] is encoded into codeword c0[7:0] consisting of symbols s[0], s[1], s[2] and s[3].

In 7:8 bit encoding 200, codeword ci[7:0] for 7 bits of the 1st 1/2 data burst on each DQ[i] serial data line and 7 of the 2nd 1/2 data burst The codeword ci[15:8] for bits may be referred to as a block boundary (BB).

7:8 bit encoding 200 may use lockup tables to map a 7-bit data value to a corresponding codeword. The lookup tables may include a lookup table set 320 including a combination lookup table 310 and a plurality of subblock lookup tables 321-324, as shown in FIG. 3 . The combination lookup table 310 may selectively concatenate encoding results according to the plurality of subblock lookup tables 321-324.

On the other hand, in 7:8 bit encoding 200, there may be 256 patterns according to 8 bit encoding of PAM-4 symbols s[0], s[1], s[2] and s[3], these Among them, 128 patterns required for 7-bit encoding of user data can be selected. The selected 128 patterns may be provided as codewords of 7-bit user data. Registers related to 128 patterns that are not selected from the lookup tables are not used and may act as overhead of the lookup table.

In the following embodiments, in order to reduce the overhead of the lookup tables, a plurality of subblock lookup tables 321-324 are arranged adjacent to each other, that is, an example in which one lookup table set 320 is concatenated is described. will be Each of the subblock lookup tables 321-324 may include a plurality of subblock lookup tables A1 to A5, B1 to B4, and to B classified according to the number of codeword mappings. The combination lookup table 310 may be configured as a lookup table mapping that selectively combines the subblock lookup tables A1 to A5, B1 to B4, and to B according to the type of the 7-bit user data value. The lookup tables are configured to support the MTA, and the mapping between PAM-4 symbols and symbol bits will be described based on Table 1. Table 1 is a non-limiting example for illustrative purposes.

PAM-4 Symbol Levels 0 One 2 3 symbol bits 00 01 11 10 voltage level
(% of supply voltage (VDD)) 0% 27% 44% 50%

Referring to Table 1, a 2-bit PAM-4 symbol may be transmitted on the channel line 130 (FIG. 1) at four voltage levels, denoted as level 0, 1, 2, or 3. Exemplarily, the PAM-4 symbol of level 3 may be set to have the highest voltage level, and the PAM-4 symbol of level 0 may be configured to have the lowest voltage level.

3 illustrates the lookup tables of the PAM-4 encoder of FIG. 1, and FIGS. 4 and 5A to 5C are the combination lookup table and subblock lookup tables A1 to A5, B1 to B4, and to B of FIG. It is a diagram for explaining codeword encoding using 3-5C illustrate lookup tables used in a 7:8 bit encoder and/or decoder, but this is a non-limiting example for illustrative purposes. According to an embodiment, a 29:32 bit encoder and/or decoder may be implemented using the lookup tables of FIGS. 3 to 5C .

Referring to FIG. 3 , the logic circuit 114 of the PAM-4 encoder 112 includes a combination lookup table 310 and first to fourth subblock lookup tables 321 - concatenated in a lookup table set 320 . 324) may be included. The first subblock lookup table 321 may be composed of subblock lookup tables B1 and B1 including the largest number of codeword mappings, for example, 8 codeword mappings. The ~B1 subblock lookup table may be configured to provide an inverted codeword mapping corresponding to the B1 subblock lookup table. The ~B1 subblock lookup table may be configured to support MTA between the last symbol and the first symbol of a codeword in the combined subblock lookup tables. The second subblock lookup table 322 may be composed of, for example, subblock lookup tables A1 and B2 including four codeword mappings. The third subblock lookup table 323 may be composed of, for example, subblock lookup tables A2, A3, A5, B3, and B4 including two codeword mappings. The fourth subblock lookup table 324 may be composed of, for example, subblock lookup tables A4 including one codeword mapping. The sub-block lookup tables A1 to A5, B1 to B4, and B will be described in detail with reference to FIGS. 5A to 5C.

3 and 4 , the combination lookup table 310 is combined according to the type of user data b[6:0] to provide a codeword mapping corresponding to the 7-bit user data b[6:0]. Subblock lookup tables A1 to A5, B1 to B4, and to B can be set. User data b[6:0] may correspond to user data d0[7:1] of the 1/2 data burst described in FIG. 2 .

For example, when the b5:b6 bit value of the 7-bit user data b[6:0] is 00, the A1 subblock lookup table and the B1 subblock lookup table may be set to be combined. The A1 subblock lookup table may provide a codeword mapping corresponding to the b0:b1 bit values. The A1 subblock lookup table includes 4 codeword mappings corresponding to 2-bits, and may be included in the second subblock lookup table 322 . The B1 subblock lookup table may provide a codeword mapping corresponding to the b2:b3:b4 bit values. The B1 subblock lookup table includes 8 codeword mappings corresponding to 3-bits, and may be included in the first subblock lookup table 321 . Accordingly, codewords (4*8=32) constructed by the combinatorial symbol encoding A1xB1 for the b5:b6 bit value 00 of the 7-bit user data b[6:0] can be provided.

When the b4:b5:b6 bit value of the 7-bit user data b[6:0] is 001, the A1 subblock lookup table and the B2 subblock lookup table may be set to be combined. The A1 subblock lookup table may provide a codeword mapping corresponding to the b0:b1 bit values. The B2 subblock lookup table may provide a codeword mapping corresponding to the b2:b3 bit values. The B2 subblock lookup table includes 4 codeword mappings corresponding to 2-bits, and may be included in the second subblock lookup table 322 . Accordingly, codewords (4*4=16) constructed by the combinatorial symbol encoding A1xB2 for the b4:b5:b6 bit value 001 of the 7-bit user data b[6:0] can be provided.

When the b4:b5:b6 bit value of the 7-bit user data b[6:0] is 101, the A2 subblock lookup table and the B1 subblock lookup table may be set to be combined. The A2 subblock lookup table may provide a codeword mapping corresponding to the b0 bit value. The A2 subblock lookup table includes two codeword mappings corresponding to 1-bit, and may be included in the third subblock lookup table 323 . The B1 subblock lookup table may provide a codeword mapping corresponding to the b1:b2:b3 bit values. Accordingly, codewords (2*8=16) constructed by the combinatorial symbol encoding A2xB1 for the b4:b5:b6 bit value 101 of the 7-bit user data b[6:0] can be provided.

When the b4:b5:b6 bit value of the 7-bit user data b[6:0] is 010, the A3 subblock lookup table and the B1 subblock lookup table may be set to be combined. The A3 subblock lookup table may provide a codeword mapping corresponding to the b0 bit value. The A3 subblock lookup table includes two codeword mappings corresponding to 1-bit, and may be included in the third subblock lookup table 323 . The B1 subblock lookup table may provide a codeword mapping corresponding to the b1:b2:b3 bit values. Accordingly, codewords (2*8=16) constructed by the combinatorial symbol encoding A3xB1 for the b4:b5:b6 bit value 010 of the 7-bit user data b[6:0] can be provided.

If the b4:b5:b6 bit value of the 7-bit user data b[6:0] is 110, the A5 subblock lookup table and the ~B1 subblock lookup table may be set to be combined. The A5 subblock lookup table may provide a codeword mapping corresponding to the b0 bit value. The A5 subblock lookup table includes two codeword mappings corresponding to 1-bit, and may be included in the third subblock lookup table 323 . The ~B1 subblock lookup table may provide a codeword mapping corresponding to the b1:b2:b3 bit values. The ~B1 subblock lookup table includes 8 codeword mappings corresponding to 3-bits, and may be included in the first subblock lookup table 321 . Accordingly, codewords (2*8=16) constructed by combinatorial symbol encoding A5x to B1 for the b4:b5:b6 bit value 110 of the 7-bit user data b[6:0] may be provided. .

When the b3:b4:b5:b6 bit value of the 7-bit user data b[6:0] is 0011, the A1 subblock lookup table and the B3 subblock lookup table may be set to be combined. The A1 subblock lookup table may provide a codeword mapping corresponding to the b0:b1 bit values. The B3 subblock lookup table may provide a codeword mapping corresponding to the b2 bit value. The B3 subblock lookup table includes two codeword mappings corresponding to 1-bit, and may be included in the third subblock lookup table 323 . Accordingly, codewords (4*2=8) constructed by the combinatorial symbol encoding A1xB3 for the b3:b4:b5:b6 bit value 0011 of the 7-bit user data b[6:0] can be provided .

When the b3:b4:b5:b6 bit value of the 7-bit user data b[6:0] is 1011, the A2 subblock lookup table and the B2 subblock lookup table may be set to be combined. The A2 subblock lookup table may provide a codeword mapping corresponding to the b0 bit value. The B2 subblock lookup table may provide a codeword mapping corresponding to the b1:b2 bit values. Accordingly, codewords (2*4=8) constructed by the combinatorial symbol encoding A2xB2 for the b3:b4:b5:b6 bit value 1011 of the 7-bit user data b[6:0] can be provided. .

If the b3:b4:b5:b6 bit value of the 7-bit user data b[6:0] is 0111, the A4 subblock lookup table and the B1 subblock lookup table may be set to be combined. The A4 subblock lookup table includes one codeword mapping, and may be included in the fourth subblock lookup table 324 . The B1 subblock lookup table may provide a codeword mapping corresponding to the b0:b1:b2 bit values. Accordingly, codewords (1*8=8) constructed by the combinatorial symbol encoding A4xB1 for the b3:b4:b5:b6 bit value 0111 of the 7-bit user data b[6:0] can be provided. .

When the b2:b3b4:b5:b6 bit value of the 7-bit user data b[6:0] is 01111, the A2 subblock lookup table and the B3 subblock lookup table may be set to be combined. The A2 subblock lookup table may provide a codeword mapping corresponding to the b0 bit value. The B3 subblock lookup table may provide a codeword mapping corresponding to the b1 bit value. Accordingly, codewords (2*2=4) constructed by the combinatorial symbol encoding A2xB3 for the b2:b3b4:b5:b6 bit value 01111 of the 7-bit user data b[6:0] can be provided. .

When the b2:b3b4:b5:b6 bit value of the 7-bit user data b[6:0] is 11111, the A3 subblock lookup table and the B4 subblock lookup table may be set to be combined. The A3 subblock lookup table may provide a codeword mapping corresponding to the b0 bit value. The B4 subblock lookup table may provide a codeword mapping corresponding to the b1 bit value. The B4 subblock lookup table includes two codeword mappings corresponding to 1-bit, and may be included in the third subblock lookup table 323 . Accordingly, codewords (2*2=4) constructed by the combinatorial symbol encoding A3xB4 for the b2:b3b4:b5:b6 bit value 11111 of the 7-bit user data b[6:0] can be provided. .

Referring to FIG. 5A , each of the A1 and A2 subblock lookup tables may be selectively combined with the B1, B2 and B3 subblock lookup tables. The A1 sub lookup table is code such that the 2-bit value is converted to symbol level 01 when it is 00, converted to symbol level 11 when it is 01, converted to symbol level 02 when it is 10, and converted to symbol level 21 when it is 11 It can be word encoded. The A2 sub lookup table may be codeword-encoded so that when the 1-bit value is 0, it is converted to symbol level 12, and when the 1-bit value is 1, it is converted to symbol level 22. The A1 and A2 subblock lookup tables may consist of a combination of the first symbol level 0, 1, or 2 and the last symbol level 1 or 2.

B1 sub lookup table is converted to symbol level 00 when the 3-bit value is 000, converted to symbol level 01 when 001, converted to symbol level 10 when 010, converted to symbol level 11 when 011, When it is 100, it is converted to symbol level 02, when it is 101, it is converted to symbol level 20, when it is 110, it is converted to symbol level 21, and when it is 111, it can be codeword-encoded. The B2 sub lookup table is code such that when the 2-bit value is 00, it is converted to symbol level 22, when it is 01, it is converted to symbol level 31, when it is 10, it is converted to symbol level 13, when it is 11, it is converted to symbol level 23. It can be word encoded. The B3 sub lookup table may be codeword-encoded so that when the 1-bit value is 0, it is converted to symbol level 32, and when it is 1, it is converted to symbol level 33. The B1 to B3 subblock lookup tables may consist of a combination of the first symbol level 0, 1, 2, or 3.

In FIG. 5A , the A1 and A2 subblock lookup tables and the B1, B2 and B3 subblock lookup tables Maximum transition (MT) from level 0 to level 3 or level 3 to level 0 between symbols within each codeword It can support the MTA in which no event occurs. In addition, it may be configured to support an MTA in which an MT event does not occur even between the last symbol of the codewords of the A1 and A2 subblock lookup tables and the first symbol of the codewords of the B1, B2 and B3 subblock lookup tables.

Referring to FIG. 5B , each of the A3 and A4 subblock lookup tables may be selectively combined with the B1 and B4 subblock lookup tables. The A3 sub lookup table may be codeword-encoded so that when the 1-bit value is 0, it is converted to symbol level 00, and when the 1-bit value is 1, it is converted to symbol level 10. The A4 sub lookup table may provide one symbol level 20. The A3 and A4 subblock lookup tables may consist of a combination of the first symbol level 0, 1, or 2 and the last symbol level 1.

The B1 subblock lookup table is the same as described with reference to FIG. 5A. The B4 subblock lookup tables may be codeword-encoded so that when a 1-bit value is 0, it is converted to symbol level 22, and when it is 1, it is converted to symbol level 13. The B1 and B4 subblock lookup tables may consist of a combination of the first symbol level 0, 1, or 2.

In FIG. 5B , the A3 and A4 subblock lookup tables and the B1 and B4 subblock lookup tables may support MTA between symbols within each codeword. In addition, it may be configured to support an MTA in which an MT event does not occur even between the last symbol of the codewords of the A1 and A2 subblock lookup tables and the first symbol of the codewords of the B1, B2 and B3 subblock lookup tables.

Referring to FIG. 5C , the A5 subblock lookup table may be selectively combined with the ~B1 subblock lookup tables. The A5 sub lookup table may be codeword-encoded so that when the 1-bit value is 0, it is converted to symbol level 13, and when it is 1, it is converted to symbol level 23. The A5 subblock lookup table may consist of a combination of the first symbol level 0, 1, or 2 and the last symbol level 3.

The ~B1 sub lookup table may provide a codeword in which the symbol level of the B1 subblock lookup table described with reference to FIG. 5A is inverted. ~B1 sub lookup table, the 3-bit value is converted to symbol level 33 when it is 000, converted to symbol level 32 when it is 001, converted to symbol level 23 when it is 010, and converted to symbol level 22 when it is 011 When it is 100, it is converted to symbol level 31, when it is 101, it is converted to symbol level 13, when it is 110, it is converted to symbol level 12, and when it is 111, it can be codeword-encoded. The ~B1 subblock lookup table consists of a combination of the first symbol level 1, 2, or 3, and there is no level 0. This is to support the MTA by removing level 0 from the first symbol of the ~B1 subblock lookup table because the last symbol of the A5 subblock lookup table is level 3.

The 7-bit user data may be decoded into a codeword with reference to FIGS. 3-5C. For example, if the 7-bit user data b0:b1:b2:b3b4:b5:b6 bit value is 0010000, the combination symbol encoding A1xB1 may be selected from the combination lookup table 310 according to the b5:b6 bit value 00. have. The symbol level 01 of the subblock lookup table A1 may be selected according to the b0:b1 bit value 00, and the symbol level 02 of the subblock lookup table B1 may be selected according to the b2:b3:b4 bit value 100. Accordingly, the 7-bit user data 0010000 may be converted into a codeword of the combination symbol 0102.

For example, assume that the 7-bit user data b0:b1:b2:b3b4:b5:b6 bit value is 0101011. According to the b3:b4:b5:b6 bit value 1011 , the combination symbol encoding A2xB3 may be selected from the combination lookup table 310 . The symbol level 12 of the subblock lookup table A2 may be selected according to the b0 bit value 0, and the symbol level 13 of the subblock lookup table B3 may be selected according to the b1:b2 bit value 10. Accordingly, the 7-bit user data 0101011 may be converted into a codeword of the combination symbol 1213 .

For example, if the 7-bit user data b0:b1:b2:b3b4:b5:b6 bit value is 1101010, according to the b4:b5:b6 bit value 010, the combination symbol encoding A3xB1 in the combination lookup table 310 is can be selected. The symbol level 10 of the subblock lookup table A3 may be selected according to the b0 bit value 1, and the symbol level 20 of the subblock lookup table B1 may be selected according to the b1:b2:b3 bit value 101. Accordingly, the 7-bit user data 1101010 may be converted into a codeword of the combination symbol 1020 .

For example, when the 7-bit user data b0:b1:b2:b3b4:b5:b6 bit value is 0000110, according to the b4:b5:b6 bit value 110, the combination symbol encoding A5x in the combination lookup table 310 is B1 may be selected. The symbol level 13 of the subblock lookup table A5 may be selected according to the b0 bit value 0, and the symbol level 33 of the ~B1 subblock lookup table may be selected according to the b1:b2:b3 bit value 000. Accordingly, the 7-bit user data 0000110 may be converted into a codeword of the combination symbol 1333 .

6 is a flowchart illustrating a method 600 of operation of the PAM-4 encoder of FIG. 1 .

Referring to FIG. 6 in conjunction with FIGS. 1 to 5C , the PAM-4 encoder 112 may receive user data 16-bit data bursts to be transmitted through the serial data line DQ[i] (S601). The PAM-4 encoder 112 divides the 16-bit data burst into 1 1/2 data bursts d0[0]d0[7:1] and 2 1/2 data bursts d0[8]d0[15:9] (S602), one bit of each 1/2 data burst, for example, d0[0] and d0[8] may be transferred to the DBI signal line (S603). The PAM-4 encoder 112 may combine the bit pairs d0[0] and d0[8] into a PAM-4 symbol (S604), and transmit the PAM-4 symbol to a DBI signal line (S605).

The PAM-4 encoder 112 may perform 7:8-bit encoding by converting the remaining 7 bits not used as PAM-4 symbols of the DBI signal line of each 1/2 data burst into a codeword (S606). 7:8 bit encoding may be performed using the combinatorial lookup table 310 and the first to fourth subblock lookup tables 321-324 concatenated in the lookup table set 320 . A codeword corresponding to 7-bit data may be generated by the sub-block lookup tables A1 to A5, B1 to B4, and to B combined according to the 7-bit data type provided from the combination lookup table 310. have. The PAM-4 encoder 112 may transmit the codeword on the channel line 130 (S607).

FIG. 7 is a diagram illustrating lookup tables of the PAM-4 decoder of FIG. 1 , and FIG. 8 is a diagram illustrating a codeword decoding lookup table of FIG. 7 .

1 and 7 , the logic circuit 124 of the PAM-4 decoder 122 may include a combinational lookup table 310 , a lookup table set 320 , and a codeword decoding lookup table 710 . . The combination lookup table 310 and the lookup table set 320 of the PAM-4 decoder 122 may have the same configuration as the combination lookup table 310 and the lookup table set 320 of FIG. 3 described above. The PAM-4 decoder 122 may receive the codeword encoded by the PAM-4 encoder 112 through the channel line 130 and perform 8:7 bit decoding corresponding to the codeword using lookup tables. have. The codeword decoding lookup table 710 may be combined with the combinational lookup table 310 and the subblock lookup tables 321-324 to recover a data burst corresponding to the codeword.

Referring to FIG. 8 , the codeword decoding lookup table 710 may be configured to provide lookup table mappings designating a lookup table corresponding to a codeword and a user data bit value corresponding to the designated lookup table. One of the A1 to A5 subblock lookup tables may be designated according to a combination of the first symbol levels 0, 1, 2, and 3 of the codeword and the second symbol levels 0, 1, 2, and 3 of the codeword. For example, codeword 00 may be specified in the A3 subblock lookup table, and a corresponding user data bit value may be set to 0. Codeword 12 may be specified in the A2 subblock lookup table, and a corresponding user data bit value may be set to 0.

Codeword decoding lookup table 710 may provide lookup table mappings 801-803 representing ˜B1, B1 through B4 subblock lookup tables that are combined with A1 through A5 subblock lookup table.

The lookup table mapping 801 indicates the B1 to B3 subblock lookup tables combined with each of the A1 and A2 subblock lookup tables, and corresponding to each of the B1 to B3 subblock lookup tables combined with the A1 or A2 subblock lookup table. Indicates the user data bit value.

For example, codeword 0102 may be decoded into 7-bit user data bits with reference to lookup table mapping 801 . The A1 subblock lookup table is specified in the previous codeword 01, and the corresponding user data bit value may be set to 00. The current codeword 02 refers to the lookup table mapping 801 to designate the B1 subblock lookup table combined with the A1 subblock lookup table, and a corresponding user data bit value may be set to 100. Codeword 0102 may be converted to 00100 in which the user data bit value 00 and 100 are combined. The combined subblock lookup table A1xB1 may be converted into the user data bit value 00 with reference to the combined lookup table 310 ( FIG. 4 ). Accordingly, the codeword 0102 may be restored to the 7-bit user data bit 0010000 in which the user data bit values 00100 and 00 are combined.

For example, in the case of codeword 1213, when the A2 subblock lookup table is specified in the previous codeword 12, the corresponding user data bit value is set to 0. The current codeword 13 is assigned to the B2 subblock lookup table combined with the A2 subblock lookup table with reference to the lookup table mapping 801 , and a corresponding user data bit value may be set to 10 . Codeword 1213 may be converted to 010 by combining user data bit values 0 and 10. The combined subblock lookup table A2xB2 may be converted into a user data bit value 1011 with reference to the combined lookup table 310 ( FIG. 4 ). Accordingly, the codeword 1213 may be restored to the 7-bit user data bit 0101011 in which the user data bit values 010 and 1011 are combined.

The lookup table mapping 802 represents the B1 and B4 subblock lookup tables combined with the A3 and A5 subblock lookup tables, respectively, and the corresponding of each of the B1 through B3 subblock lookup tables combined with the A1 or A2 subblock lookup table. Indicates the user data bit value.

For example, codeword 1020 may be decoded into 7-bit user data bits with reference to lookup table mapping 802 . The A3 subblock lookup table is specified in the previous codeword 10, and the corresponding user data bit value may be set to 1. For the current codeword 20, the B1 subblock lookup table combined with the A3 subblock lookup table is designated with reference to the lookup table mapping 802 , and a corresponding user data bit value may be set to 101 . Codeword 1020 may be converted into user data bit value 1101. The combined subblock lookup table A3xB1 may be converted into a user data bit value 010 with reference to the combined lookup table 310 ( FIG. 4 ). Accordingly, the codeword 1020 may be restored as the 7-bit user data bit 1101010 in which the user data bit values 1101 and 010 are combined.

The lookup table mapping 803 represents the ˜B1 subblock lookup table combined with each of the A3 and A4 subblock lookup tables.

For example, it can be decoded into 7-bit user data bits with reference to lookup table mapping 803 of codeword 1333 . When the A5 subblock lookup table is specified in the previous codeword 13, the corresponding user data bit value is set to 0. The current codeword 33 is assigned to the ~B1 subblock lookup table combined with the A5 subblock lookup table with reference to the lookup table mapping 803 , and the corresponding user data bit value may be set to 000. Codeword 1333 may be converted to a user data bit value of 0000. The combined subblock lookup tables A5x to B1 may be converted into a user data bit value 110 with reference to the combined lookup table 310 ( FIG. 4 ). Accordingly, the codeword 1333 may be restored to the 7-bit user data bit 0000110 in which the user data bit values 0000 and 110 are combined.

9 is a flowchart illustrating a method 900 of operation of the PAM-4 decoder of FIG. 1 .

Referring to FIG. 9 in conjunction with FIGS. 1 to 8 , the PAM-4 decoder 122 may receive a codeword through the serial data line DQ[i] (S901). The PAM-4 decoder 122 may perform 8:7 bit decoding that converts the codeword into 7-bit user data (S902). 8:7 bit decoding is performed using the codeword decoding lookup table 710, the combination lookup table 310 and the first to fourth subblock lookup tables 321-324 concatenated in the lookup table set 320. can be performed. 7-bit user data corresponding to the codeword may be generated by 8:7-bit decoding.

The PAM-4 decoder 122 receives the user data 1-bit of the PAM-4 symbol through the DBI signal line (S903), combines the received user data 1-bit with the decoded 7-bit user data to obtain the first 1/2 data burst can be restored (S904). The PAM-4 decoder 122 may recover the 2 1/2 data bursts for the serial data line DQ[i], and combine the first and 2 1/2 data bursts to recover complete data bursts ( S905).

FIG. 10 is a diagram for explaining an encoding method of a 32-bit data burst using the 7:8-bit encoding of FIG. 2 .

2 and 10, 32-bit data bursts are constructed on each DQ[i] serial data line, and each 32-bit data burst is represented by each of 4 1/4 data bursts of 8 bits. Each quarter data burst is further divided into 1-bit:7-bit pairs, and can perform the 7:8-bit encoding 200 described in FIG. 2 to support the MTA. The 1-bit value of each quarter data burst can be encoded as a PAM-4 symbol on the DBI signal line, where the 1-bit of the four quarter data bursts on each of the eight DQ[i] serial data lines is DBI When sent over the signal line, a total of 32 bits can be transmitted over the DBI signal line.

To support MTA even on DBI signal lines, only 28 bits out of 32 bits can be used for 7:8 bit encoding. The 4 bits not used for 7:8 bit encoding on the DBI signal line can be symbolically encoded through a separate signal line, for example, an Error Detection Code (EDC) signal line. Accordingly, the encoding method of the 32-bit data burst of FIG. 10 has an overhead that requires an additional signal line.

11 is a diagram for explaining a data burst encoding method according to an embodiment of the present invention.

1 and 11 , the PAM-4 encoder 112 may perform (m-p):m-bit encoding on m-bit data bursts to be transmitted on a data line. The PAM-4 encoder 112 sends the value of p(n>p) bits among m bits to the DBI signal line, and q:(q+k)(k) for q bits, which is the sum of p bits on the DBI signal line. ≥1) Bit encoding may be performed to generate codewords of DBI signal lines. The PAM-4 encoder 112 may perform (m-p):m bit encoding on the remaining (m-p) bits of each of the data bursts to generate a codeword of the data line.

The PAM-4 encoder 112 determines the total number of codewords corresponding to m bits of data bursts, the number of codewords in which the last symbol is the highest symbol level among codewords without an MT event between symbols, and the last symbol is The p bits may be determined based on the number of codewords with intermediate symbol levels, the number of codewords with the last symbol being the lowest symbol level, and the number of codewords having the first symbol with the highest symbol level and the lowest symbol level. . Accordingly, (m-p):m bit encoding and q:(q+k) bit encoding can be implemented with maximum transition prevention (MTA) coding in which a maximum transition (MT) event does not occur between symbols.

Specifically, the PAM-4 encoder 112 may be designed to have a minimum overhead of 3-bit when encoding a PAM-4 symbol for a 32-bit data burst. If a 29:32 bit encoder and/or decoder is directly designed based on a lookup table, a table with a capacity of several GB is required. In order to reduce the size of such a table, it can be applied to a 29:32 bit encoder and decoder based on the embodiments described in FIGS. 3 to 5C , 7 and 8 . Accordingly, the size of a table included in the 29:32 bit encoder and/or decoder can be greatly reduced. The PAM-4 encoder 112 calculates the number of overhead bits according to the codeword length (or the number of PAM-4 symbols) n when performing PAM-4 symbol encoding using Equations 1 to 7, for example. can For a 32-bit data burst, the codeword length (or number of PAM-4 symbols) n will be 16.

,

,

을 정의할 수 있다.

은 마지막 심볼이 레벨 3인 MT 이벤트가 없는 심볼 n의 코드워드 개수이고,

은 마지막 심볼이 레벨 1 또는 2인 MT 이벤트가 없는 심볼 n의 코드워드 개수이고,

은 마지막 심볼이 레벨 0인 MT 이벤트가 없는 심볼 n의 코드워드 개수이다. 변수들

,

,

사이의 관계를 나타내는 점화식(recurrence relation)을 구하면 수학식 1과 같다.PAM-4 encoder 112 calculates patterns without MT event for codeword length n, variable

,

,

can be defined.

is the number of codewords in symbol n without an MT event where the last symbol is level 3,

is the number of codewords in symbol n without an MT event where the last symbol is level 1 or 2,

is the number of codewords of symbol n without an MT event in which the last symbol is level 0. variables

,

,

Equation 1 is obtained when a recurrence relation representing the relationship between the two is obtained.

=1,

=2,

=1 으로 나타내고, n은 현재 심볼을 나타내고, n+1은 다음 심볼을 나타낼 수 있다. From here,

=1,

=2,

=1, n may indicate the current symbol, and n+1 may indicate the next symbol.

를 계산하면 수학식 2 및 3과 같다.Using Equation 1, the total number of codewords for codeword length n

is calculated as in Equations 2 and 3.

Here, n may indicate a current symbol, and n-1 may indicate a previous symbol.

은 블록 바운더리(BB, 도 2)에서의 MTA를 고려하지 않은, 즉 첫번째 심볼에 올 수 있는 심볼 레벨에 제약이 없는 경우에 해당한다. 블록 바운더리(BB)에서도 이전 코드워드 n-1의 마지막 심볼과 현재 코드워드 n의 첫번째 심볼 사이의 MT 이벤트를 방지하기 위해 MTA를 지원할 필요가 있다. 이를 위하여, 현재 코드워드 n의 첫번째 심볼에 레벨 3 (또는 레벨 0)이 없는 조건을 추가하면, 수학식 2 및 3은 수학식 4 및 5로 변형될 수 있다. Total number of codewords according to Equations 2 and 3

is a case in which MTA in the block boundary (BB, FIG. 2 ) is not considered, that is, there is no restriction on the symbol level that can come in the first symbol. Even at the block boundary (BB), it is necessary to support the MTA in order to prevent an MT event between the last symbol of the previous codeword n-1 and the first symbol of the current codeword n. To this end, if the condition that there is no level 3 (or level 0) is added to the first symbol of the current codeword n, Equations 2 and 3 may be transformed into Equations 4 and 5.

및 수학식 5의

을 기초로 하고 수학식 6 및 7을 이용하여 오버헤드 비트 수 x를 계산할 수 있다.of Equation 3

and Equation 5

Based on , the number of overhead bits x can be calculated using Equations 6 and 7.

The number of overhead bits x having an integer value for the codeword length n obtained using Equations 6 and 7 may be expressed as the graph line 1100 of FIG. 11 . As shown in the graph line 1100, it can be seen that the codeword length (or the number of PAM-4 symbols) n=16 corresponds to the number of overhead bits 3 ( 1103 ).

In the graph line 1100 of FIG. 11 , it can be seen that the codeword length (or the number of PAM-4 symbols) n=4 according to the 7:8 bit encoding 200 of FIG. 2 has an overhead bit number of 1 ( 1101), the number of overhead bits of 1 corresponds to one bit in each 1/2 data burst carried on the DBI signal line. And, if 7:8 bit encoding 200 is applied to the 32-bit data burst described in FIG. 10 , it can be seen that the number of overhead bits is 4 ( 1101 ). In contrast, when PAM-4 symbol encoding is performed on a 32-bit data burst using Equations 1 to 7, the number of overhead bits can be reduced to 3 (1103). Accordingly, if 3-bits of a 32-bit data burst on each of the 8 DQ[i] serial data lines are sent on the DBI signal line, a total of 24 bits can be transmitted on the DBI signal line.

12 to 14 are diagrams for explaining a 32-bit data burst structure according to the encoding method of FIG. 11 .

1 and 12, the PAM-4 encoder 112 performs the encoding method described in FIG. 11 to convert 3-bits of a 32-bit data burst in each of 8 DQ[i] serial data lines to a DBI signal. Sending on the line, a total of 24 bits can be transmitted on the DBI signal line. The PAM-4 encoder 112 may transmit the first bit values 1201 of 3-bits of each of the DQ[i] serial data lines on the DBI signal line. Thereafter, the second of the 3-bit values 1202 of each of the DQ[i] serial data lines may be sent on the DBI signal line, followed by the third bit values 1203 being sent on the DBI signal line. The PAM-4 encoder 112 may divide the 24 bits on the DBI signal line into 8 3-bit groups, and perform 3:4 bit encoding for each 3-bit group. The 3,4 bit encoding will be described in FIG. 14 .

Referring to FIG. 13, when the PAM-4 encoder 112 performs the encoding method of FIG. 11 to send 3-bits of a 32-bit data burst in each of the 8 DQ[i] serial data lines onto the DBI signal line, A total of 24 bits can be transmitted on the DBI signal line. The PAM-4 encoder 112 may transmit 3-bit values 1300-1307 of each of the DQ[i] serial data lines on the DBI signal line. The PAM-4 encoder 112 may perform 3:4-bit encoding on the 3-bit values 1300 to 1307 on the DBI signal line.

Referring to FIG. 14 , the 3:4-bit encoding 1400 may convert symbol bits 0000 and a codeword of symbol level 00 when the 3-bit value on the DBI signal line is 000. 3:4 bit encoding 1400 converts the 3-bit value 001 on the DBI signal line to symbol bits 0001 and symbol level 01, converts the 3-bit value 010 to symbol bits 0100 and symbol level 10, 3 - convert bit value 011 to symbol bits 0101 and symbol level 11, convert 3-bit value 100 to symbol bits 0011 and symbol level 02, and convert 3-bit value 101 to symbol bits 1100 and symbol level 20 codeword encoding to convert the 3-bit value 110 to symbol bits 1101 and symbol level 21, and to convert the 3-bit value 111 to symbol bits 0111 and symbol level 12. In 3:4 bit encoding 1400, no PAM-4 symbol of level 3 with the highest voltage level is present in the codeword. Accordingly, 3:4 bit encoding 1400 can support MTA on DBI signal lines.

The 32-bit data burst structure of FIGS. 12 and 13 described above does not require additional signal lines such as the EDC signal line required for MTA support on the DBI signal line in the 7:8 bit encoding of FIG. 10 . In addition, the EDC signal line may be configured to be used for error detection of the data DQ of the DQ[i] serial data line. The PAM-4 encoder 112 generates a checksum or a cyclic redundancy check (CRC) for the data DQ and transmits predetermined CRC bits to the EDC signal line, thereby improving the performance of the PAM-4 encoder 112 . can provide Accordingly, the PAM-4 encoder 112 performs the encoding method of FIG. 11 to send 3-bits of a 32-bit data burst in each of the DQ[i] serial data lines on the DBI signal line, and 3 on the DBI signal line. : Performs 4-bit encoding 1400 to support MTA on DBI signal line, while meeting performance improvement and minimum overhead of PAM-4 encoder 112 .

15 is a block diagram of a first example of a memory system including an encoding and decoding apparatus according to embodiments of the present invention.

Referring to FIG. 15 , a memory system 1500 may include a memory controller 1510 and a memory device 1520 . Memory system 1500 is an integrated circuit, electronic device or system, smart phone, tablet PC, computer, server, workstation, portable communication terminal, Personal Digital Assistant (PDA), Portable Multimedia Player (PMP), and other suitable computers. may refer to a computing device, such as a virtual machine or a virtual computing device thereof, and the like. Alternatively, the memory system 1500 may be a part of components included in a computing system such as a graphics card.

The memory controller 1510 may be communicatively connected to the memory device 1520 through a channel or a memory bus 1530 . For the sake of brevity, it is illustrated that the clock CLK, command/address CA, and data DQ are provided between the memory controller 1510 and the memory device 1520 through one signal line, but in reality, the clock CLK, command/address CA, and data DQ are provided. may be provided through a plurality of signal lines or a bus.

The clock CLK signal may be transmitted from the memory controller 1510 to the memory device 1520 through a clock signal line of the memory bus 1530 . The command/address (CA) signal may be transmitted from the memory controller 1510 to the memory device 1520 through the command/address bus of the memory bus 1530 . The chip select (CS) signal may be transmitted from the memory controller 1510 to the memory device 1520 through a chip select (CS) line of the memory bus 1530 . The chip select (CS) signal activated to be logic high may indicate that the command/address (CA) signal transmitted through the command/address (CA) bus is a command. Data DQ is transmitted from the memory controller 1510 to the memory device 1520 or from the memory device 1520 to the memory controller 1510 through the data DQ bus of the memory bus 1530 composed of bidirectional signal lines. ) can be transmitted.

The memory controller 1510 includes a data transmitter 1512 that transmits data DQ to the memory device 1520 , and the data transmitter 1512 transmits write data bursts to be transmitted to the memory device 1520 with a PAM-4 symbol. and a PAM-4 encoder 112 configured to convert The PAM-4 encoder 112 is configured to look up the first to fourth subblocks concatenated in the logic circuit 114 of FIG. 1 , the combination lookup table 1310 and the lookup table set 320 described in FIGS. 3 to 5C . Tables 321-324 may be included. The PAM-4 encoder 112 encodes write data bursts into PAM-4 symbols based on the encoding operation method 600 described in FIG. 6 and the data burst structure and DBI MTA codeword described in FIGS. 11-14. can be configured to The memory controller 1510 may transmit the encoded PAM-4 symbols as data DQ to the memory device 1520 through a data (DQ) bus.

The memory device 1520 may write data DQ or read data under the control of the memory controller 1510 . The memory device 1520 may include a memory cell array 1522 and a data input buffer 1524 .

The memory cell array 1522 may include a plurality of word lines and a plurality of bit lines, and a plurality of memory cells formed at intersections of the word lines and the bit lines. Memory cells of the memory cell array 1522 include volatile memory cells (eg, dynamic random access memory (DRAM) cells, static RAM (SRAM) cells, etc.), non-volatile memory cells (eg, flash memory cells, resistive RAM (ReRAM) cells, etc.). cell, a phase change RAM (PRAM) cell, a magnetic RAM (MRAM) cell), or some other type of memory cell.

The memory device 1520 may be configured to receive and decode PAM-4 symbols transmitted through the data (DQ) bus through the data input buffer 1524 . The data input buffer 1524 may include a PAM-4 decoder 122 configured to recover the PAM-4 symbols into write data bursts. The PAM-4 decoder 122 may include the logic circuit 124 of FIG. 1 , the combinational lookup table 310 described in FIGS. 7 and 8 , the lookup table set 320 and the codeword decoding lookup table 710 . can The PAM-4 decoder 122 may be configured to decode the PAM-4 symbols into write data bursts based on the decoding operation method 1400 described in FIG. 9 . The data input buffer 1524 may provide decoded write data bursts for writing to the memory cell array 1522 .

16 is a block diagram illustrating a part of a memory device according to an embodiment of the present invention.

Referring to FIG. 16 , the memory device 1520 includes a memory cell array 1522 , a row decoder 1601 , a word line driver 1602 , a column decoder 1603 , an input/output gating circuit 1604 , an MRS 1605 , It may include a control logic circuit 1606 , an address buffer 1607 , a data input buffer 1524 , and a data output buffer 1526 .

The memory cell array 1522 includes a plurality of memory cells provided in the form of a matrix arranged in rows and columns. The memory cell array 1522 includes a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL may be connected to rows of memory cells, and the plurality of bit lines BL may be connected to columns of memory cells.

The row decoder 1601 may select any one of the plurality of word lines WL connected to the memory cell array 1522 . The row decoder 1601 decodes the row address ROW_ADDR received from the address buffer 1607 to select any one word line WL corresponding to the row address ROW_ADDR, and activates the selected word line WL. can be connected to the wordline driver 1602. The column decoder 1603 may select predetermined bit lines BL from among a plurality of bit lines BL of the memory cell array 1522 . The column decoder 1603 decodes the column address COL_ADDR received from the address buffer 1607 to generate a column select signal, and connects the bit lines BL selected by the column select signal to the input/output gating circuit 1604 . can The input/output gating circuit 1604 may include read data latches for storing read data of the bit lines BL selected by the column selection signal, and a write driver for writing write data to the memory cell array 1522 . have. The read data stored in the read data latches of the input/output gating circuit 1604 may be provided to the data (DQ) bus through the data output buffer 1526 . Write data may be applied to the memory cell array 1522 through a data input buffer 1524 coupled to the data (DQ) bus and through a write driver of the input/output gating circuit 1604 .

The control logic circuit 1606 may receive the clock signal CLK and the command CMD and generate control signals CTRLS for controlling an operation timing and/or a memory operation of the memory device 1520 . The control logic circuit 1606 may read data from the memory cell array 1522 and write data to the memory cell array 1522 using the control signals CTRLS.

The MRS 1605 may store information used by the control logic circuit 1606 to configure the operation of the memory device 1520 to set operating conditions for the memory device 1520 . The MRS 1605 may include a register that stores parameter codes for various operation and control parameters used to set operating conditions of the memory device 1520 . The parameter code may be received by the memory device 1520 through a command/address (CA) bus. The control logic circuit 1606 may provide control signals CTRLS to circuits of the memory device 1520 to operate as set in the operation and control parameters stored by the MRS 1605 . The control signals CTRLS may include the first mode selection signal MRS[1:0] and the second mode selection signal MTA_Mode described with reference to FIGS. 9 and 13 .

17 is a block diagram of a second example of a memory system including an encoding and decoding apparatus according to embodiments of the present invention.

Referring to FIG. 17 , the memory system 1700 further includes a data receiver 1714 including a PAM-4 decoder 122 in the memory controller 1710 as compared with the memory system 1500 of FIG. 15 , The difference is that the memory device 1720 shows the data output buffer 1526 including the PAM-4 encoder 112 .

When transmitting the read data bursts output from the memory cell array 1522 to the memory controller 1710 , the memory device 1720 may be configured to encode and transmit PAM-4 symbols through the data output buffer 1526 . The data output buffer 1526 may include a PAM-4 encoder 112 configured to convert the read data into PAM-4 symbols.

The memory controller 1710 may be configured to receive and decode PAM-4 symbols transmitted on the data (DQ) bus through the data receiver 1714 . The data receiver 1714 may include a PAM-4 decoder 122 configured to recover the PAM-4 symbols into read data bursts.

Although the present invention has been described with reference to a limited number of embodiments shown in the drawings, this is merely exemplary, and various changes and modifications, and other equivalent implementations, can be made thereto by those skilled in the art. It will be appreciated that examples are possible. Accordingly, the appended claims are intended to cover all such modifications and variations as fall within the true spirit and scope of the present invention.

Claims (10)

As a device,
a transmitter for a data bus, the transmitter comprising an encoder for converting data bursts to be transmitted over the data bus into codewords composed of symbols;
the encoder comprises logic circuitry for correlating the data bursts with the symbols;
the logic circuit comprises a plurality of sub-block lookup tables sorted according to the number of codeword mappings, the codeword mappings representing the correlation of some bit values in the data bursts with the symbols; and
a combination lookup table that selectively concatenates encoding results according to the plurality of subblock lookup tables based on the remaining bit values of each of the data bursts;
and the encoder is configured to provide the codeword corresponding to the data bursts to the data bus using the combinational lookup table and the plurality of subblock lookup tables. According to claim 1,
The encoder sends a 1-bit value in each of the 8 bits of the data bursts to a data bus inversion (DBI) signal line to encode the pair of 1-bit values into a symbol of the DBI signal line, and perform 7:8 bit encoding on each of the remaining 7 bits, and generate the codewords consisting of 4 symbols having at least 4 levels according to the 7:8 bit encoding. 3. The method of claim 2,
The plurality of sub-block lookup tables are configured as one lookup table set by concatenating registers storing the codeword mappings. 3. The method of claim 2, wherein the plurality of subblock lookup tables comprises the codeword mappings representing symbols corresponding to the values of some of the remaining 7 bits of each of the data bursts;
The plurality of sub-block lookup tables are
first subblock lookup tables providing 8 codeword mappings corresponding to 3-bit values of the partial bit values;
second sub-block lookup tables providing four codeword mappings corresponding to 2-bit values of the partial bit values;
third subblock lookup tables providing two codeword mappings corresponding to a 1-bit value of the partial bit values; and
An apparatus comprising a fourth subblock lookup table providing one codeword mapping with one symbol level. 5. The method of claim 4,
The plurality of sub-block lookup tables are arranged between the symbols in the codeword mappings from a level having a highest voltage level to a level having a lowest voltage level or a level having the lowest voltage level among the at least four levels. a maximum transition prevention (MTA) coding in which no maximum transition (MT) event to the level with the highest voltage level occurs. 5. The method of claim 4,
the combination lookup table is configured to combine the first subblock lookup tables and the second subblock lookup tables based on a 2-bit value of the remaining bit values of each of the data bursts to provide the codeword device to be. 5. The method of claim 4,
The combination lookup table combines the second subblock lookup tables or the first subblock lookup tables and the third subblock lookup tables based on a 3-bit value of the remaining bit values of each of the data bursts. an apparatus configured to provide the codeword in combination. 5. The method of claim 4,
The combination lookup table is configured to combine the first subblock lookup tables and the fourth subblock lookup table based on a 4-bit value among the remaining bit values of each of the data bursts or use second subblock lookup tables and combining the third subblock lookup tables to provide the codeword. 5. The method of claim 4,
and the combination lookup table is configured to combine the third subblock lookup tables based on a 5-bit value of the remaining bit values of each of the data bursts to provide the codeword. As a device,
a receiver for a data bus, the receiver comprising a decoder for converting codewords composed of symbols received on the data bus into data bursts;
wherein the decoder comprises logic circuitry representing a correlation between the symbols and the data bursts;
The logic circuit is
a codeword decoding lookup table configured to provide a lookup table mapping specifying subblock lookup tables corresponding to the symbols of each of the codewords;
the sub-block lookup tables classified according to the number of codeword mappings, the codeword mappings indicate the correlation between the symbols and some bit values in the data bursts; and
a combination lookup table concatenating the subblock lookup tables based on a combination of the subblock lookup tables specified by the lookup table mapping;
and the decoder reconstructs the data bursts corresponding to the codeword by using the codeword decoding lookup table, the subblock lookup tables, and the combination lookup table.

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