KR20230056552A - Semiconductor memory device and method of operating the same - Google Patents

Abstract

A semiconductor memory device includes a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins receive write data to be stored in the memory cell array or output read data stored in the memory cell array. A semiconductor memory device performs a burst operation in which one data set including a plurality of data bits is input or output through a plurality of data input/output pins based on one command received from the outside. The number of data input/output pins corresponds to an integer other than a power of 2 (non-power-of-two), and the burst length (BL), which is the basic unit of burst operation, is an integer excluding a power of 2 respond to

Description

Semiconductor memory device and its driving method {SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME}

The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory device and a method for driving the semiconductor memory device.

Semiconductor memory devices may be classified into non-volatile memory devices such as flash memory and volatile memory devices such as dynamic random access memory (DRAM). For example, since volatile memory devices are relatively inexpensive, they are used to store large amounts of data such as system memories.

The degree of integration and capacity of semiconductor memory devices are increasing, and data transfer rates are also increasing. This can increase the total number of bits transferred for each memory access, and typically requires additional input/output (I/O) pins or lanes and corresponding module/board signal traces. can However, when input/output pins are added, the manufacturing cost of the semiconductor memory device may increase, and therefore, technologies for transmitting more bits without excessively increasing the number of input/output pins are being studied.

One object of the present invention is to provide a semiconductor memory device capable of improving bandwidth without excessive cost increase while improving signal integrity characteristics.

Another object of the present invention is to provide a method of driving the semiconductor memory device.

In order to achieve the above object, a semiconductor memory device according to example embodiments includes a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins receive write data to be stored in the memory cell array or output read data stored in the memory cell array. The semiconductor memory device performs a burst operation in which one data set including a plurality of data bits is input or output through the plurality of data input/output pins based on one command received from the outside. The number of the plurality of data input/output pins corresponds to a non-power-of-two integer, and the burst length (BL), which is a basic unit of the burst operation, is a power of 2 Corresponds to integers excepted.

In order to achieve the above object, in a method of driving a semiconductor memory device according to example embodiments, a write command or a read command is received. A data write operation of storing write data in the memory cell array or a data read operation of reading read data stored in the memory cell array is performed based on the write command or the read command. During the data write operation, the write data is received through a plurality of data input/output pins, and during the data read operation, the read data is output through the plurality of data input/output pins. The operation of receiving the write data and the operation of outputting the read data is a burst in which one data set including a plurality of data bits is input or output through the plurality of data input/output pins based on one command. ) is performed based on the operation. The number of the plurality of data input/output pins corresponds to a non-power-of-two integer, and the burst length (BL), which is a basic unit of the burst operation, is a power of 2 Corresponds to integers excepted.

In order to achieve the above object, a semiconductor memory device according to example embodiments includes a memory cell array, a plurality of data input/output pins, a data processing path, and a clock divider. The plurality of data input/output pins receive write data to be stored in the memory cell array or output read data stored in the memory cell array. The data processing path is disposed between the memory cell array and the plurality of data input/output pins. The clock divider generates a second command clock signal based on the first command clock signal. The semiconductor memory device performs a data write operation of storing the write data in the memory cell array based on a write command or a data read operation of reading the read data stored in the memory cell array based on a read command. carry out The operation of receiving the write data and the operation of outputting the read data is a burst in which one data set including a plurality of data bits is input or output through the plurality of data input/output pins based on one command. ) is performed based on the operation. The number of the plurality of data input/output pins corresponds to a non-power-of-two integer, and the burst length (BL), which is a basic unit of the burst operation, is a power of 2 Corresponds to integers excluded and integers that are multiples of three. The plurality of data bits included in the one data set include first data bits corresponding to the write data or the read data, and the number of the first data bits corresponds to an integer that is a power of 2. The memory cell array, the data processing path, and the plurality of data input/output pins operate based on a data clock signal and the second command clock signal. The division ratio of the clock divider corresponds to an integer excluding powers of 2 and an integer that is a multiple of 3. A value obtained by dividing the period of the second command clock signal by the period of the data clock signal corresponds to an integer excluding powers of 2 and an integer that is a multiple of 3.

In the semiconductor memory device and method of driving the semiconductor memory device according to the embodiments of the present invention as described above, both the burst length and the number of data input/output pins may correspond to integers other than powers of 2. At this time, the actual data to be written or read may be implemented to include the number of pieces of information (ie, data bits) corresponding to an integer that is a power of 2. In addition, additional data necessary for writing or reading may be further included or discarded dummy data may be further included. Accordingly, it is possible to improve the bandwidth of the semiconductor memory device without excessively increasing cost while improving signal integrity characteristics.

1 is a block diagram illustrating a semiconductor memory device according to example embodiments.
2 is a diagram for explaining a burst operation performed in a semiconductor memory device according to example embodiments.
3 is a block diagram illustrating a memory system including a semiconductor memory device according to example embodiments.
FIG. 4 is a block diagram illustrating a specific example of the semiconductor memory device of FIG. 1 .
5, 6, 7, 8, 9a, 9b, 9c, 10, and 11 are diagrams for explaining operations of semiconductor memory devices according to example embodiments.
12 is a block diagram illustrating a semiconductor memory device according to example embodiments.
FIG. 13 is a block diagram illustrating a specific example of the semiconductor memory device of FIG. 12 .
14, 15a, 15b, 16a, and 16b are diagrams for explaining operations of semiconductor memory devices according to example embodiments.
17 and 18 are flowcharts illustrating a method of driving a semiconductor memory device according to example embodiments.
19 is a block diagram illustrating an example of a memory module applicable to a memory system according to example embodiments.
20 is a block diagram illustrating an example of a memory system according to example embodiments.
21 is a block diagram illustrating an example of applying a memory module according to an embodiment of the present invention to an electronic system.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in more detail. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components are omitted.

1 is a block diagram illustrating a semiconductor memory device according to example embodiments.

Referring to FIG. 1 , the semiconductor memory device 100 includes a memory cell array 110 , a data processing path 120 and a plurality of data input/output pins 130 .

The memory cell array 110 stores data. For example, the memory cell array 110 may include a plurality of memory cells that store data.

In one embodiment, the semiconductor memory device 100 may be a volatile memory device. For example, the semiconductor memory device 100 may be a dynamic random access memory (DRAM), and the memory cell array 110 may include a plurality of dynamic memory cells.

The plurality of data input/output pins 130 receive write data WDAT to be stored in the memory cell array 110 or output read data RDAT stored in the memory cell array 110 . For example, a pin may mean a contact pad or a contact pin, but may not be limited thereto.

The data processing path 120 is disposed between the memory cell array 110 and the plurality of data input/output pins 130 and processes data or reads data for storing the received write data WDAT in the memory cell array 110 . It is possible to perform data processing to output (RDAT).

The memory cell array 110, the data processing path 120, and the plurality of data input/output pins 130 may operate based on the data clock signal WCK.

The semiconductor memory device 100 may perform a data writing operation or a data reading operation. For example, when a write command is received, the semiconductor memory device 100 performs a data write operation of storing write data WDAT in the memory cell array 110 based on the write command, and writes the data. During operation, write data WDAT may be received through the plurality of data input/output pins 130 . For example, when a read command is received, the semiconductor memory device 100 performs a data read operation of reading read data RDAT stored in the memory cell array 110 based on the read command. During a data read operation, read data RDAT may be output through the plurality of data input/output pins 130 .

The semiconductor memory device 100 may perform a burst operation. The burst operation represents an operation in which one data set DS including a plurality of data bits is input or output through a plurality of data input/output pins 130 based on one command received from the outside.

The operations of receiving the write data WDAT during the data write operation and outputting the read data RDAT during the data read operation may be performed based on the burst operation. For example, one data set DS may include write data WDAT or read data RDAT. For example, one data set DS including the write data WDAT may be input through the plurality of data input/output pins 130 based on one write command. For example, one data set DS including the read data RDAT may be output through the plurality of data input/output pins 130 based on one read command.

According to embodiments of the present invention, the number of the plurality of data input/output pins 130 corresponds to an integer other than a power of 2 (ie, not a power of 2) (non-power-of-two), A burst length (BL), which is a basic unit of the burst operation, corresponds to an integer excluding powers of 2, which will be described later with reference to FIG. 2 .

2 is a diagram for explaining a burst operation performed in a semiconductor memory device according to example embodiments.

Referring to FIG. 2 , one data set DS that is input or output through a plurality of data input/output pins DQ based on one command during the burst operation is illustrated.

In the burst operation, a semiconductor memory device (eg, 100 in FIG. 1 ) writes a large amount of data by sequentially decreasing or increasing an address from an initial address received from a memory controller (eg, 20 in FIG. 3 ). Indicates a reading operation. The basic unit of the burst operation is referred to as a burst length (BL).

2 shows a case where the plurality of data input/output pins DQ includes first to (m+1)th data input/output pins DQ0, DQ1, ..., DQm, that is, (m+1) data input/output pins. (m is a natural number of 2 or more). 2 shows a case where the burst length BL is (n+1) (n is a natural number of 4 or greater).

One data set DS may include a plurality of data bits BL0, BL1, BL2, BL3, ..., BLn. The total number of data bits (BL0, BL1, BL2, BL3, ..., BLn) is the product of the number of data input/output pins (DQ0, DQ1, ..., DQm) and the burst length (BL), that is, Corresponds to (m+1)*(n+1), and may indicate an information transfer unit that is input or output at one time based on one command.

During the burst operation, data bits BL0, BL1, BL2, BL3, ..., BLn are transmitted through data input/output pins DQ0, DQ1, ..., DQm based on the data clock signal WCK. It can be input or output sequentially. For example, (m+1) data bits BL0 are simultaneously input or output through (m+1) data input/output pins DQ0, DQ1, ..., DQm, and then (m+1) 1) (m + 1) data bits BL1 are simultaneously input or output through the data input/output pins DQ0, DQ1, ..., DQm, and then (m + 1) data input/output pins ( (m + 1) data bits (BL2) are simultaneously input or output through DQ0, DQ1, ..., DQm, and then (m + 1) data input/output pins (DQ0, DQ1, ... , DQm), (m + 1) data bits (BL3) are simultaneously input or output, and then (m + 1) data input/output pins (DQ0, DQ1, ..., DQm) through (m + 1) +1) data bits BLn may be simultaneously input or output. Accordingly, (n+1) data bits (BL0, BL1, BL2, BL3, ..., BLn) corresponding to the burst length (BL) are transmitted through one data input/output pin (eg, DQ0). It can be input or output sequentially.

According to embodiments of the present invention, the number of data input/output pins DQ0, DQ1, ..., DQm, that is, (m+1) may correspond to an integer excluding powers of 2. Also, the burst length BL, that is, (n+1) may correspond to an integer excluding powers of 2. For example, at least one of the number of data input/output pins DQ0, DQ1, ..., DQm and the burst length BL may correspond to an integer that is a multiple of three.

As described above with reference to FIG. 1 , one data set DS may include write data WDAT or read data RDAT. At this time, the plurality of data bits BL0, BL1, BL2, BL3, ..., BLn included in one data set DS are the first data bits corresponding to the write data WDAT or the read data RDAT. It may contain data bits. For example, the first data bits may represent actual data to be written or read. For example, the number of first data bits may correspond to an integer that is a power of 2.

In an embodiment, one data set DS may further include additional data related to the write data WDAT or the read data RDAT. At this time, the plurality of data bits (BL0, BL1, BL2, BL3, ..., BLn) included in one data set (DS) further include second data bits excluding the first data bits, The second data bits may correspond to the additional data. For example, the additional data may include at least one of data bus inversion (DBI) information, error correction code (ECC) information (eg, parity bits), and meta data required to write or read the actual data. Including, but the present invention may not be limited thereto. For example, the number of second data bits may correspond to an integer that is a power of 2.

In another embodiment, one data set DS may further include dummy data unrelated to the write data WDAT or the read data RDAT. At this time, the plurality of data bits (BL0, BL1, BL2, BL3, ..., BLn) included in one data set (DS) further include second data bits excluding the first data bits, The second data bits may correspond to the dummy data. For example, the dummy data may represent discarded data that is not used to write or read the real data. For example, the number of second data bits may correspond to an integer that is a power of 2.

In one embodiment, even if the number of the first data bits and the number of the second data bits each correspond to an integer that is a power of 2, a plurality of data including the first data bits and the second data bits The number of bits BL0, BL1, BL2, BL3, ..., BLn, that is, (m+1)*(n+1) may correspond to an integer excluding powers of 2.

Conventionally, both or at least one of the burst length and the number of data input/output pins are required to transmit the number of information (i.e., data bits) corresponding to an integer that is a power of 2 during burst operation. implemented to respond. For example, by implementing the burst length and the number of data input/output pins as 2 ^y and 2 ^z , respectively, 2 ^x data bits were transmitted at once based on one command (x, y, z are natural numbers, respectively , x=y+z).

In order to improve the bandwidth of a semiconductor memory device, it is necessary to increase a burst length or the number of data input/output pins. At this time, in the case of using the above-described conventional method, there is a difficulty in implementation because all or at least one of the burst length and the number of data input/output pins must be implemented in the form of a power of 2. For example, when the burst length is doubled, there is a problem in that signal integrity characteristics are severely deteriorated due to lack of a data window, and when the number of data input/output pins is doubled, manufacturing There was a problem of excessive increase in cost.

In the semiconductor memory device according to embodiments of the present invention, both the burst length and the number of data input/output pins may correspond to integers other than powers of 2. At this time, the actual data to be written or read may be implemented to include the number of pieces of information (ie, data bits) corresponding to an integer that is a power of 2. In addition, additional data necessary for writing or reading may be further included or discarded dummy data may be further included. Accordingly, it is possible to improve the bandwidth of the semiconductor memory device without excessively increasing cost while improving signal integrity characteristics.

In other words, in order to transfer 2 ^x pieces of information (i.e., data bits), the burst length and the number of data input/output pins do not have values of 2 ^y and 2 ^z , respectively, but the product can be implemented to correspond to 2 ^x . , and if necessary, 2 ^x pieces of information can be implemented by discarding some bits. In the case of transmitting a total of 2 ^x +a pieces of information by transmitting additional data such as DBI information, ECC information, and meta data, the burst length and the number of data input/output pins do not have values of 2 ^y and 2 ^z , respectively. It can be implemented so that the product corresponds to 2 ^x +a (a is a natural number).

3 is a block diagram illustrating a memory system including a semiconductor memory device according to example embodiments.

Referring to FIG. 3 , the memory system 10 includes a memory controller 20 and a semiconductor memory device 40 . The memory system 10 may further include a plurality of signal lines 30 connecting the memory controller 20 and the semiconductor memory device 40 .

The semiconductor memory device 40 is controlled by the memory controller 20 . For example, the memory controller 20 may write data to or read data from the semiconductor memory device 40 based on a request from an external host device (not shown).

The plurality of signal lines 30 may include a control line, a command line, an address line, data lines, and a power line. The memory controller 20 transmits a command CMD, an address ADDR, and a control signal CTRL to the semiconductor memory device 40 through the command line, the address line, and the control line, and transmits the control signal CTRL through the data lines. Data DAT may be exchanged with the semiconductor memory device 40 and the power supply voltage PWR may be provided to the semiconductor memory device 40 through the power line. Although not shown, the plurality of signal lines 30 may further include a DQS line for transmitting a data strobe signal (ie, a DQS signal).

The semiconductor memory device 40 may be a semiconductor memory device according to example embodiments. For example, as described above with reference to FIGS. 1 and 2 , the semiconductor memory device 40 includes the number of data input/output pins corresponding to an integer excluding powers of 2, and the data input/output pins correspond to the data lines. It is connected to and can receive or output data (DAT). The data DAT includes a data set for performing the burst operation, and the burst length of the data set may correspond to an integer excluding powers of 2.

In one embodiment, some or all of the plurality of signal lines 30 may be referred to as channels. In this specification, the data lines through which data DAT is transmitted are referred to as channels. However, the present invention is not limited thereto, and the channel may further include the command line through which the command CMD is transmitted and/or the address line through which the address ADDR is transmitted.

FIG. 4 is a block diagram illustrating a specific example of the semiconductor memory device of FIG. 1 .

Referring to FIG. 4 , the semiconductor memory device 200 includes a control logic circuit 210, an address register 220, a bank control logic 230, a row address multiplexer 240, a refresh counter 245, and a column address latch ( 250), row decoder 260, column decoder 270, memory cell array 300, sense amplifier unit 285, input/output gating circuit 290, data input/output buffer 295, and data input/output pins 299. can include For example, the semiconductor memory device 200 may be a DRAM.

The memory cell array 300 may include first to eighth bank arrays 310 to 380 . In addition, the row decoder 260 includes first to eighth bank row decoders 260a to 260h respectively connected to the first to eighth bank arrays 310 to 380, and the column decoder 270 includes the first to eighth bank arrays 310 to 380. It includes first to eighth bank column decoders 270a to 270h connected to the first to eighth bank arrays 310 to 380, respectively, and the sense amplifier unit 285 includes the first to eighth bank arrays 310 to 270h. 380) may include first to eighth bank sense amplifiers 285a to 285h respectively connected to each other.

First to eighth bank arrays 310 to 380, first to eighth bank sense amplifiers 285a to 285h, first to eighth bank column decoders 270a to 270h, and first to eighth banks The row decoders 260a to 260h may configure the first to eighth banks, respectively. Each of the first to eighth bank arrays 310 to 380 includes a plurality of word lines WL, a plurality of bit lines BTL, and a plurality of word lines WL and bit lines BTL crossing each other. It may include a plurality of memory cells MC formed at points.

Although an example of the semiconductor memory device 200 including 8 banks is shown in FIG. 4 , the semiconductor memory device 200 may include any number of banks according to embodiments.

The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 20 . The address register 220 provides the received bank address BANK_ADDR to the bank control logic 230, provides the received row address ROW_ADDR to the row address multiplexer 240, and provides the received column address COL_ADDR. Column address latch 250 may be provided.

The bank control logic 230 may generate bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, a bank row decoder corresponding to the bank address BANK_ADDR among the first to eighth bank row decoders 260a to 260h is activated, and the first to eighth bank column decoders 270a ~270h), a bank column decoder corresponding to the bank address BANK_ADDR may be activated.

The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 and receive the refresh row address REF_ADDR from the refresh counter 245 . The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to eighth bank row decoders 260a to 260h, respectively.

Among the first to eighth bank row decoders 260a to 260h, the bank row decoder activated by the bank control logic 230 decodes the row address RA output from the row address multiplexer 240 to obtain the row address You can activate the corresponding word line. For example, the activated bank row decoder may apply a word line driving voltage to a word line corresponding to a row address RA.

The column address latch 250 may receive the column address COL_ADDR from the address register 220 and temporarily store the received column address COL_ADDR. Also, the column address latch 250 may gradually increase the received column address COL_ADDR in a burst mode in which a burst operation is performed. The column address latch 250 may apply the temporarily stored or gradually increased column address COL_ADDR to the first to eighth bank column decoders 270a to 270h, respectively.

A bank column decoder activated by the bank control logic 230 among the first to eighth bank column decoders 270a to 270h corresponds to the bank address BANK_ADDR and the column address COL_ADDR through the input/output gating circuit 290 can activate the sense amplifier that

The input/output gating circuit 290 includes circuits for gating input/output data, input data mask logic, read data latches for storing data output from the first to eighth bank arrays 310 to 380, and the first to eighth bank arrays 310 to 380. Write drivers for writing data to the first to eighth bank arrays 310 to 380 may be included.

Data DAT read from one of the first to eighth bank arrays 310 to 380 may be sensed by a sense amplifier corresponding to the one bank array and stored in the read data latches. there is. The data DAT stored in the read data latches may be output through a data input/output buffer 295 and data input/output pins 299 and provided to the memory controller 20 .

Data DAT to be written in one of the first to eighth bank arrays 310 to 380 is received from the memory controller 20 through the data input/output pins 299 and the data input/output buffer 295, The received data DAT is provided to the input/output gating circuit 290, and the input/output gating circuit 290 may write the received data DAT into the subpage of the one bank array through the write drivers.

The data input/output buffer 295 receives data DAT in a write operation and provides the received data DAT to the input/output gating circuit 290, and in a read operation, the data DAT provided from the input/output gating circuit 290 may be provided to the memory controller 20.

The control logic circuit 210 may control the operation of the semiconductor memory device 200 . For example, the control logic circuit 210 may generate control signals to allow the semiconductor memory device 200 to perform a write operation or a read operation. The control logic circuit 210 may include a command decoder 211 for decoding the command CMD received from the memory controller 20 and a mode register 212 for setting an operation mode of the semiconductor memory device 200. can For example, the command decoder 211 may generate the control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, and a chip select signal.

The memory cell array 300 may correspond to the memory cell array 110 of FIG. 1 . The sense amplifier unit 285 , the input/output gating circuit 290 , the data input/output buffer 295 , and the like may correspond to the data processing path 120 of FIG. 1 . The data input/output pins 299 may correspond to the plurality of data input/output pins 130 of FIG. 1 . The memory cell array 300, the data input/output buffer 295, and the data input/output pins 299 may operate based on the data clock signal WCK. Although not shown in detail, the sense amplifier unit 285, the input/output gating circuit 290, and the like may operate based on the data clock signal WCK. For example, the data clock signal WCK may be received from the memory controller 20 or generated internally in the semiconductor memory device 200 .

5, 6, 7, 8, 9a, 9b, 9c, 10, and 11 are diagrams for explaining operations of semiconductor memory devices according to example embodiments.

Referring to FIG. 5 , when a plurality of commands CMD1, CMD2, and CMD3 are continuously received in a burst operation, and a plurality of data sets DS1, corresponding to the plurality of commands CMD1, CMD2, and CMD3, A case in which DS2 and DS3) are continuously received is exemplified. tCCD may indicate a minimum time interval required between successive commands.

For example, when the plurality of commands CMD1, CMD2, and CMD3 are write commands, a plurality of data sets DS1, DS2, and DS3 including write data are continuously input through a plurality of data input/output pins. and a data write operation may be performed based on the write commands and the write data. For example, when the plurality of commands CMD1 , CMD2 , and CMD3 are read commands, a data read operation is performed based on the read commands to obtain read data, and a plurality of data including the read data The sets DS1 , DS2 , and DS3 may be continuously output through a plurality of data input/output pins.

Referring to FIG. 6, a case in which both the burst length and the number of data input/output pins are implemented to correspond to integers that are powers of 2 according to the conventional method is illustrated. For example, FIG. 6 shows one data set (eg, DS1 in FIG. 5 ) that is input or output based on one command (eg, CMD1 in FIG. 5 ).

In the example of FIG. 6, the burst length is 2 ⁴ =16, and the number of data input/output pins (DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7) is 2 ³ =8, so one data set may include 16*8=128 data bits (BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11, BL12, BL13, BL14, BL15). In addition, one data mask inversion (DMI) input/output pin for additional information is additionally formed, and one data set includes 16 DBI bits (DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15) may be further included. For example, as described above with reference to FIG. 2 , one data set may further include the additional data related to the write data WDAT or the read data RDAT, and the DBI bits DBI0 , DBI1 , DBI2 , DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15) may correspond to the DBI information included in the additional data.

Therefore, in the example of FIG. 6, one data set transmitted based on one command includes a total of 144 (= 128 + 16) bits transmitted through a total of 9 (= 8 + 1) I/O pins. can include

In addition, in the example of FIG. 6 , data bits BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11, BL12, BL13, and BL14 are generated based on the data clock signal WCKc. , BL15) and DBI bits (DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15) are input or output, and the data clock signal ( It can operate in a quad data rate (QDR) method in which four bits are transferred during one cycle (tCKc) of WCKc). Accordingly, as 4 cycles of the data clock signal WCKc are repeated within tCCD (ie, tCCD=4*tCKc), a burst length of 16 can be realized.

In the existing low power double data rate 5 (LPDDR5) standard, a burst operation is implemented by forming two data sets shown in FIG. 6 . In this case, since the burst length is 16 and the number of data input/output pins is 16, 256 data bits are transferred, and 32 DBI bits are transferred through 2 DMI input/output pins, so a total of 18 input/outputs in one burst operation. A total of 288 bits can be passed through the pins. For example, when tCCD is about 1.88 ns, the period (tCKc) of the data clock signal (WCKc) is about 470 ps, and the time required to transmit one bit (ie, 1 unit interval (UI)) is about 118 ps. can be

Referring to FIG. 7, a case in which both the burst length and the number of data input/output pins are implemented to correspond to an integer that is a power of 2 according to the conventional method, and a case in which the bandwidth is doubled compared to FIG. 6 are exemplified. are doing Similar to FIG. 6, FIG. 7 shows one set of data being input or output based on one command.

In the example of FIG. 7, the burst length is 2 ⁵ =32, and the number of data input/output pins (DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7) is 2 ³ =8, so one data set is 32*8=256 data bits (BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11, BL12, BL13, BL14, BL15, BL16, BL17, BL18, BL19 , BL20, BL21, BL22, BL23, BL24, BL25, BL26, BL27, BL28, BL29, BL30, BL31). In addition, one DMI input/output pin for additional information is additionally formed, and one data set includes 32 DBI bits (DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7) received through the DMI input/output pin. , DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15, DBI16, DBI17, DBI18, DBI19, DBI20, DBI21, DBI22, DBI23, DBI24, DBI25, DBI26, DBI27, DBI28, DBI29, DBI30, DBI31) can include more. For example, the DBI bits (DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15, DBI16, DBI17, DBI18, DBI19, DBI20, DBI21, DBI22, DBI23, DBI24, DBI25, DBI26, DBI27, DBI28, DBI29, DBI30, DBI31) may correspond to the DBI information described above with reference to FIG. 2 .

Therefore, in the example of FIG. 7, one data set transmitted based on one command includes a total of 288 (= 256 + 32) bits transmitted through a total of 9 (= 8 + 1) input/output pins. can include

In addition, in the example of FIG. 7 , data bits BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11, BL12, BL13, and BL14 are generated based on the data clock signal WCKr. , BL15, BL16, BL17, BL18, BL19, BL20, BL21, BL22, BL23, BL24, BL25, BL26, BL27, BL28, BL29, BL30, BL31) and DBI bits (DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15, DBI16, DBI17, DBI18, DBI19, DBI20, DBI21, DBI22, DBI23, DBI24, DBI25, DBI26, DBI27, DBI28, DBI29, DBI30 and DBI31) are input or output, and can operate in a QDR method in which four bits are transmitted during one cycle (tCKr) of the data clock signal (WCKr). Accordingly, as 8 cycles of the data clock signal WCKr are repeated within tCCD (ie, tCCD=8*tCKr), a burst length of 32 can be realized.

In the LPDDR6 standard, which is being discussed recently, a method of implementing a burst operation by forming two data sets shown in FIG. 7 was reviewed in order to double the bandwidth compared to LPDDR5. In this case, since the burst length is 32 and the number of data input/output pins is 16, 512 data bits are transferred, and 64 DBI bits are transferred through 2 DMI input/output pins, so a total of 18 input/output bits are transmitted in one burst operation. A total of 576 bits can be passed through the pins. In other words, compared to the example of FIG. 6, in the example of FIG. 7, the burst length doubles (16 -> 32) and the number of bits included in one data set doubles (144 -> 288). , and thus the bandwidth can be doubled. However, compared to the example of FIG. 6 , in the example of FIG. 7 , the cycle tCKr of the data clock signal WCKr may be reduced by half. For example, when tCCD is equal to about 1.88 ns, the period tCKr of the data clock signal WCKr decreases to about 235 ps, and the time required to transmit one bit can decrease to about 59 ps (that is, , 1 UI=59 ps). Accordingly, compared to the example of FIG. 6 , in the example of FIG. 7 , signal integrity characteristics may be severely deteriorated.

Meanwhile, although not shown, the bandwidth may be doubled by doubling the number of input/output pins. However, in this case, a problem of excessively increasing manufacturing cost may occur.

Referring to FIG. 8, when the burst length and the number of data input/output pins are implemented to correspond to integers other than powers of 2 according to embodiments of the present invention, and the bandwidth is doubled compared to FIG. 6 An implementation case is exemplified. For example, both the burst length and the number of data input/output pins may be implemented to correspond to integers that are multiples of 3. Similar to Figs. 6 and 7, Fig. 8 shows one data set to be input or output based on one command.

In the example of FIG. 8, the burst length is 24 (= 3*2 ³ ), and the number of data input/output pins (DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, DQ8, DQ9, DQ10, DQ11) is 12 (=3*2 ² ). In this case, one data set transmitted based on one command will include a total of 288 (= 24 * 12) bits (BL0 to BL31, DBI0 to DBI31) transmitted through a total of 12 input/output pins. can That is, the same number of bits as in the example of FIG. 7 can be transmitted.

In addition, in the example of FIG. 8 , data bits BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11, BL12, BL13, and BL14 are generated based on the data clock signal WCK. , BL15, BL16, BL17, BL18, BL19, BL20, BL21, BL22, BL23, BL24, BL25, BL26, BL27, BL28, BL29, BL30, BL31) and DBI bits (DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15, DBI16, DBI17, DBI18, DBI19, DBI20, DBI21, DBI22, DBI23, DBI24, DBI25, DBI26, DBI27, DBI28, DBI29, DBI30 and DBI31) are input or output, and can operate in a QDR method in which four bits are transmitted during one cycle (tCK) of the data clock signal (WCK). Accordingly, as 6 cycles of the data clock signal WCK are repeated within tCCD (ie, tCCD=6*tCK), a burst length of 24 can be realized.

Compared to the example of FIG. 6, in the example of FIG. 8, the burst length increases by 1.5 times (16->24), the number of input/output pins increases by 1.33 times (9->12), and the number of bits included in one data set The number doubles (144 -> 288), so the bandwidth can be doubled. Also, compared to the example of FIG. 6 , in the example of FIG. 8 , the period tCK of the data clock signal WCK may be reduced by about 2/3. For example, when tCCD is equal to about 1.88 ns, the cycle (tCK) of the data clock signal (WCK) is about 313 ps, and the time required to transmit one bit can be reduced to about 78 ps (ie, 1 UI=78 ps). In this case, compared to the example of FIG. 6, the signal integrity characteristic of the example of FIG. 8 is lowered, but compared to the example of FIG. 7, the example of FIG. 8 does not excessively degrade the signal integrity characteristic (ie, while securing the signal integrity characteristic). ) can effectively improve the bandwidth of a semiconductor memory device. In addition, compared to the example of FIG. 6, the example of FIG. 8 does not excessively increase the number of input/output pins (increased by 1.33 times), effectively increasing the bandwidth of the semiconductor memory device without excessive cost increase (that is, with minimal cost increase). can improve

Compared to the example of FIG. 7, in the example of FIG. 8, data bits (BL24, BL25, BL26, BL27, BL28, BL29, BL30, BL31) and DBI bits (DBI24, DBI25, DBI26, DBI27, DBI28, DBI29, DBI30 and DBI31 may be arranged, assigned, and/or mapped to correspond to the data input/output pins DQ9, DQ10, and DQ11. 7 and 8, data bits (BL24, BL25, BL26, BL27, BL28, BL29, BL30, BL31) and DBI bits (DBI24, DBI25, DBI26, DBI27, DBI28) whose arrangement, allocation and/or mapping are changed , DBI29, DBI30, DBI31) are indicated by hatching. Also, compared to the example of FIG. 7 , in the example of FIG. 8 , the period tCK of the data clock signal WCK may increase by about 1.33 times and the number of input/output pins may increase by 1.33 times. Therefore, as shown in the example of FIG. 8, according to the embodiments of the present invention, a method of implementing the burst length and the number of data input/output pins to correspond to an integer excluding powers of 2 (ie, an integer that is a multiple of 3) is LPDDR6. Standards may be more suitable.

In one embodiment, data bits BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11, BL12, BL13, BL14, BL15, BL16, BL17, BL18, BL19, BL20 , BL21, BL22, BL23, BL24, BL25, BL26, BL27, BL28, BL29, BL30, BL31) is the first data bit corresponding to the write data WDAT or read data RDAT described above with reference to FIG. DBI bits (DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15, DBI16, DBI17, DBI18, DBI19, DBI20, DBI21, DBI22, DBI23, DBI24, DBI25, DBI26, DBI27, DBI28, DBI29, DBI30, DBI31) may be the second data bits corresponding to the additional data described above with reference to FIG. 2 . As described above, the burst length is implemented to correspond to an integer excluding powers of 2 (eg, 24), and the number of data input/output pins is also implemented to correspond to an integer excluding powers of 2 (eg, 12). However, the number of first data bits may correspond to an integer that is a power of 2 (eg, 256) and the number of second data bits may correspond to an integer that is a power of 2 (eg, 32). However, the sum of the numbers of the first and second data bits may correspond to an integer (eg, 288) excluding powers of 2.

Referring to FIGS. 9A, 9B, and 9C, cases in which the burst length and the number of data input/output pins are all implemented to correspond to integers other than powers of 2 according to embodiments of the present invention are illustrated.

DBI bits (DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15, DBI16, DBI17, DBI18, DBI19, DBI20, DBI21, DBI22, Except for DBI23, DBI24, DBI25, DBI26, DBI27, DBI28, DBI29, DBI30, and DBI31) being different, examples of FIGS. A description overlapping with that of FIG. 8 will be omitted.

In the example of FIG. 9A , DBI bits (DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15, DBI16, DBI17, DBI18, DBI19, The ECC bits (ECC0, ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8, ECC9, ECC10) . In other words, as described above with reference to FIG. 2, one data set includes the additional data related to the write data WDAT or read data RDAT, the additional data includes the ECC information, and the ECC bit fields (ECC0, ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8, ECC9, ECC10, ECC11, ECC12, ECC13, ECC14, ECC15, ECC16, ECC17, ECC18, ECC19, ECC20, ECC21, ECC22, ECC23, ECC24, ECC25, ECC26, ECC27, ECC28, ECC29, ECC30, ECC31) may correspond to the ECC information (eg, parity bit).

In the example of FIG. 9B, the DBI bits (DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15, DBI16, DBI17, DBI18, DBI19, The meta bits (MET0, MET1, MET2, MET3, MET4, MET5, MET6, MET7, MET8, MET9, MET10) . In other words, as described above with reference to FIG. 2, one data set includes the additional data related to the write data WDAT or read data RDAT, the additional data includes the meta data, and the meta bit fields (MET0, MET1, MET2, MET3, MET4, MET5, MET6, MET7, MET8, MET9, MET10, MET11, MET12, MET13, MET14, MET15, MET16, MET17, MET18, MET19, MET20, MET21, MET22, MET23, MET24, MET25, MET26, MET27, MET28, MET29, MET30, MET31) may correspond to the meta data.

In the example of FIG. 9C, the DBI bits (DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15, DBI16, DBI17, DBI18, DBI19, The dummy bits (DUM0, DUM1, DUM2, DUM3, DUM4, DUM5, DUM6, DUM7, DUM8, DUM9, DUM10) , DUM11, DUM12, DUM13, DUM14, DUM15, DUM16, DUM17, DUM18, DUM19, DUM20, DUM21, DUM22, DUM23, DUM24, DUM25, DUM26, DUM27, DUM28, DUM29, DUM30, DUM31). In other words, as described above with reference to FIG. 2, one data set includes the dummy data irrelevant to the write data WDAT or the read data RDAT and discarded without being used during data write/read operations, dummy bits (DUM0, DUM1, DUM2, DUM3, DUM4, DUM5, DUM6, DUM7, DUM8, DUM9, DUM10, DUM11, DUM12, DUM13, DUM14, DUM15, DUM16, DUM17, DUM18, DUM19, DUM20, DUM21, DUM22, DUM23, DUM24, DUM25, DUM26, DUM27, DUM28, DUM29, DUM30, DUM31) may correspond to the dummy data.

10 illustrates a case in which both the burst length and the number of data input/output pins are implemented to correspond to integers that are powers of 2 according to the conventional method. 11 illustrates a case in which both the burst length and the number of data input/output pins are implemented to correspond to integers excluding powers of 2 according to embodiments of the present invention.

The example of FIG. 10 is substantially the same as the example of FIG. 7 , and the example of FIG. 11 may be substantially the same as the example of FIG. 8 except for the arrangement of some bits. Descriptions overlapping those of FIGS. 7 and 8 will be omitted.

Compared to the example of FIG. 10, in the example of FIG. 11, data bits (BL3, BL7, BL11, BL15, BL19, BL23, BL27, BL31) and DBI bits (DBI3, DBI7, DBI11, DBI15, DBI19, DBI23, DBI27 and DBI31) may be arranged, allocated, and/or mapped to correspond to the data input/output pins DQ9 to DQ11. 10 and 11, data bits (BL3, BL7, BL11, BL15, BL19, BL23, BL27, BL31) and DBI bits (DBI3, DBI7, DBI11, DBI15, DBI19) whose arrangement, allocation and/or mapping are changed , DBI23, DBI27, DBI31) are indicated by hatching.

However, the present invention is not limited thereto, and bits to be changed in arrangement, allocation, and/or mapping may be determined in various ways according to embodiments. Also, DBI bits may be different as described above with reference to FIGS. 9a, 9b and 9c.

12 is a block diagram illustrating a semiconductor memory device according to example embodiments.

Referring to FIG. 12 , the semiconductor memory device 102 includes a memory cell array 110, a data processing path 120, and a plurality of data input/output pins 130, and may further include a clock divider 140. there is.

Except for further including a clock divider 140 , the semiconductor memory device 102 may be substantially the same as the semiconductor memory device 100 of FIG. 1 . Descriptions overlapping those of FIG. 1 will be omitted.

The clock divider 140 may generate the second command clock signal TCLK based on the first command clock signal CLK. For example, the second command clock signal TCLK may be generated by dividing the first command clock signal CLK.

The memory cell array 110, the data processing path 120, and the plurality of data input/output pins 130 may operate based on the data clock signal WCK and the second command clock signal TCLK.

In one embodiment, the division ratio of the clock divider 140, that is, a value obtained by dividing the period of the second command clock signal TCLK by the period of the first command clock signal CLK may correspond to an integer excluding powers of 2. there is. For example, the division ratio of the clock divider 140 may correspond to an integer that is a multiple of 3. However, the present invention is not limited thereto, and the division ratio of the clock divider 140 may correspond to an arbitrary integer.

FIG. 13 is a block diagram illustrating a specific example of the semiconductor memory device of FIG. 12 .

Referring to FIG. 13 , the semiconductor memory device 202 includes a control logic circuit 210, an address register 220, a bank control logic 230, a row address multiplexer 240, a refresh counter 245, and a column address latch ( 250), row decoder 260, column decoder 270, memory cell array 300, sense amplifier unit 285, input/output gating circuit 290, data input/output buffer 295, and data input/output pins 299. and may further include a clock divider 205.

Except for further including a clock divider 205 , the semiconductor memory device 202 may be substantially the same as the semiconductor memory device 200 of FIG. 4 . A description overlapping with that of FIG. 4 will be omitted.

The clock divider 205 may correspond to the clock divider 140 of FIG. 12 . The clock divider 205 may generate the second command clock signal TCLK based on the first command clock signal CLK. The control logic circuit 210 and the address register 220 may operate based on the second command clock signal TCLK. For example, the first command clock signal CLK may be received from the memory controller 20 or generated internally in the semiconductor memory device 202 .

14, 15a, 15b, 16a, and 16b are diagrams for explaining operations of semiconductor memory devices according to example embodiments.

Referring to FIG. 14 , when the burst length, the number of data input/output pins, and one data set are implemented according to the conventional method as in the example of FIG. 6, the data clock signal WCKc, the command clock signal CLKc and Internal signals SIG1, SIG2, and SIG3 generated based on the above are exemplified.

Referring to FIG. 15A , when a burst length, the number of data input/output pins, and one data set are implemented according to embodiments of the present invention as in the example of FIG. 8 , a data clock signal WCK, a first command clock The signal CLK, the second command clock signal TCLK, and internal signals SIG1, SIG2, and SIG3 generated based thereon are illustrated. For example, a value obtained by dividing the period of the second command clock signal TCLK by the period of the first command clock signal CLK, that is, the division ratio of the clock divider 140 may be 3. In other words, the clock divider 140 may be a 3:1 clock divider.

Referring to FIG. 15B , when a burst length, the number of data input/output pins, and one data set are implemented according to embodiments of the present invention as in the example of FIG. 8 , a data clock signal WCK, a first command clock Signal CLK, second command clock signals TCLK1 and TCLK2, and internal signals SIG1, SIG2 and SIG3 generated based thereon are illustrated. For example, a value obtained by dividing the period of the second command clock signals TCLK1 and TCLK2 by the period of the first command clock signal CLK, that is, the division ratio of the clock divider 140 may be 6.

Internal signals SIG1 , SIG2 , and SIG3 of FIGS. 15A and 15B may be substantially the same as internal signals SIG1 , SIG2 , and SIG3 of FIG. 14 . In other words, the conventional method of FIG. 14 and the embodiments of the present invention of FIGS. 15A and 15B are data clock signals WCKc and WCK with different cycles and command clock signals CLKc, TCLK, TCLK1 and TCLK2 with different cycles. ), but can generate the same internal signals (SIG1, SIG2, SIG3). Accordingly, the conventional method of FIG. 14 and the embodiments of the present invention of FIGS. 15A and 15B can be implemented using the same internal circuits (eg, circuits included in the data processing path), and if necessary, a combo ( combo) can be easily implemented even when the operation is performed.

In one embodiment, a value obtained by dividing the period of the second command clock signals TCLK, TCLK1, and TCLK2 by the period of the data clock signal WCK may correspond to an integer excluding powers of 2. For example, a value obtained by dividing the period of the second command clock signal TCLK by the period of the data clock signal WCK may correspond to an integer that is a multiple of 3 (eg, 6). For example, a value obtained by dividing the period of the second command clock signals TCLK1 and TCLK2 by the period of the data clock signal WCK may correspond to an integer that is a multiple of 3 (eg, 12).

In one embodiment, a value obtained by dividing the period of the first command clock signal CLK by the period of the data clock signal WCK may correspond to an integer that is a power of 2 (eg, 2).

Referring to FIG. 16A, a case in which a data read operation is performed in the example of FIG. 15A is illustrated. During a data read operation, internal signals CSL, FRP, PDL, LTC, and EXT as shown may be generated.

Referring to FIG. 16B, a case in which a data writing operation is performed in the example of FIG. 15A is illustrated. During a data write operation, internal signals PWY, PCLKWC, and PWT/PDT as shown may be generated.

17 and 18 are flowcharts illustrating a method of driving a semiconductor memory device according to example embodiments.

1 and 17 , a method of driving a semiconductor memory device according to example embodiments of the present invention is performed by a semiconductor memory device 100 including a memory cell array 110 and a plurality of data input/output pins 130. is carried out

In the method of driving a semiconductor memory device according to example embodiments, a write command or a read command is received (step S100). Based on the write command or the read command, a data write operation of storing the write data WDAT in the memory cell array 110 or a data read operation of reading the read data RDAT stored in the memory cell array 110 is performed (step S200).

During the data write operation, write data WDAT is received through a plurality of data input/output pins 130, and during the data read operation, read data RDAT is output through a plurality of data input/output pins 130. there is. The operation of receiving the write data WDAT and the operation of outputting the read data RDAT is performed when one data set DS including a plurality of data bits is connected to the plurality of data input/output pins 130 based on one command. It may be performed based on a burst operation input or output through

The number of data input/output pins 130 may correspond to an integer excluding powers of 2, and the burst length, which is a basic unit of the burst operation, may correspond to integers excluding powers of 2. For example, as described above with reference to FIG. 2 , at least one of the number of data input/output pins DQ0 , DQ1 , ..., DQm and the burst length BL may correspond to an integer that is a multiple of 3.

12 and 18 , a method of driving a semiconductor memory device according to example embodiments includes a memory cell array 110, a plurality of data input/output pins 130, and a clock divider 140. performed by the memory device 102 .

In the method of driving a semiconductor memory device according to example embodiments, step S100 may be substantially the same as step S100 of FIG. 17 . The second command clock signal TCLK may be generated by dividing the first command clock signal CLK (step S300). For example, a value obtained by dividing the period of the second command clock signal TCLK by the period of the first command clock signal CLK may correspond to an integer excluding powers of 2. For example, a value obtained by dividing the period of the second command clock signal TCLK by the period of the first command clock signal CLK may correspond to an integer that is a multiple of 3.

Based on the write command or the read command, a data write operation of storing the write data WDAT in the memory cell array 110 or a data read operation of reading the read data RDAT stored in the memory cell array 110 is performed (step S200a). Step S200a is similar to step S200 of FIG. 17, except that the operation of receiving the write data WDAT during the data write operation and the operation of outputting the read data RDAT during the data read operation are performed using the second command clock signal. (TCLK).

Meanwhile, embodiments of the present invention may be implemented in the form of a product including a computer readable program code stored in a computer readable medium. The computer readable program code may be provided to processors of various computers or other data processing devices. The computer-readable medium may be a computer-readable signal medium or a computer-readable recording medium. The computer-readable recording medium may be any tangible medium capable of storing or including a program in or connected to an instruction execution system, equipment, or device. For example, the computer-readable medium may be provided in the form of a non-transitory storage medium. Here, non-temporary means that the storage medium does not contain a signal and is tangible, but does not distinguish whether data is stored semi-permanently or temporarily in the storage medium.

19 is a block diagram illustrating an example of a memory module applicable to a memory system according to example embodiments.

Referring to FIG. 19 , the memory module 500 includes a buffer chip 590 (eg, registering clock driver; RCD) disposed (mounted) on a circuit board 501, a plurality of semiconductor memory devices 601a, 601b, 601c, 601d, 601e, 602a, 602a, 602c, 602d, 602e, 603a, 603b, 603c, 603d, 604a, 604b, 604c, 604d), module resistors 560, 570, SPD (ser ial presence detection) A chip 580 and a power management integrated circuit (PMIC) 585 may be included.

The buffer chip 590 may control semiconductor memory devices (or memory chips) and the PMIC 585 under the control of the memory controller 20 . For example, the buffer chip 590 may receive an address ADDR, a command CMD, and data DAT from the memory controller 20 .

The SPD chip 580 may include electrically erasable programmable read-only memory (EEPROM). The SPD chip 580 may include initial information or device information (DI) of the memory module 500 . For example, the SPD chip 580 may include initial information or device information DI, such as the module type, module configuration, storage capacity, module type, and execution environment of the memory module 500 .

When a memory system including the memory module 500 is booted, the memory controller 20 reads device information DI from the SPD chip 580, and based on the read device information DI, the memory module 500 ) can be recognized. The memory controller 20 may control the memory module 500 based on device information DI from the SPD chip 580 . For example, the memory controller 20 may identify types of semiconductor memory devices included in the memory module 500 according to device information DI from the SPD chip 580 .

Here, the circuit board 501 is a printed circuit board, and is formed between the first edge portion 503 and the second edge portion 505 in the first direction D1 in a second direction perpendicular to the first direction D1 ( D2) can be extended. The buffer chip 590 is disposed in the center of the circuit board 501, and the semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d include the buffer chip 590 and the first edge portion ( 503 and between the buffer chip 590 and the second edge portion 505 in a plurality of rows.

Here, the semiconductor memory devices 601a to 601e and 602a to 602e are arranged in a plurality of rows between the buffer chip 590 and the first edge portion 503, and the semiconductor memory devices 603a to 603d and 604a to 604d ) are arranged in a plurality of rows between the buffer chip 590 and the second edge portion 505 . For example, the semiconductor memory devices 601a to 601d, 602a to 602d, 603a to 603d, and 604a to 604d are data chips that store actual data, and the semiconductor memory devices 601e and 602e store ECC information (eg, For example, it may be parity chips that store parity bits).

The buffer chip 590 provides command/address signals to the semiconductor memory devices 601a to 601e through the command/address transmission line 561, and provides command/address signals to the semiconductor memory devices 602a to 602e through the command/address transmission line 563. ) to provide a command/address signal. In addition, the buffer chip 590 provides command/address signals to the semiconductor memory devices 603a to 603d through the command/address transmission line 571, and provides command/address signals to the semiconductor memory devices 604a through the command/address transmission line 573. ~ 604d) may be provided with a command/address signal.

The command/address transmission lines 561 and 563 are commonly connected to the module resistor 560 disposed adjacent to the first edge portion 503, and the command/address transmission lines 571 and 573 are connected to the second edge portion. It may be commonly connected to the module resistance unit 570 disposed adjacent to 505 . Each of the module resistors 560 and 570 may include a termination resistor Rtt/2 connected to the termination voltage Vtt.

For example, each of the semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604e may be a DRAM device.

The SPD chip 580 may be disposed adjacent to the buffer chip 590 , and the PMIC 585 may be disposed between the semiconductor memory device 603d and the second edge portion 505 . The PMIC 585 generates a power voltage VDD based on the input voltage VIN, and supplies the power voltage VDD to semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d. can provide

20 is a block diagram illustrating an example of a memory system according to example embodiments.

Referring to FIG. 20 , a memory system 800 may include a memory controller 810 and at least one memory module 820 or 830 . For example, the memory system 800 may have quad rank memory modules.

The memory controller 810 may control memory modules to execute commands received from a processor or a host. The memory controller 810 may be implemented inside a processor or host, or may be implemented as an application processor or SoC. In the bus 840 of the memory controller 810, a source termination may be implemented through a resistor RTT for signal integrity. The resistor RTT may be connected to the input/output buffers 811 and 813.

The first memory module 820 and the second memory module 830 may be connected to the memory controller 810 through a bus 840 . Each of the first memory module 820 and the second memory module 830 may be the memory module described above with reference to FIG. 19 . The first memory module 820 may include at least one memory rank RK1 and RK2 , and the second memory module 830 may include at least one memory rank RK3 and RK4 .

21 is a block diagram illustrating an example of applying a memory module according to an embodiment of the present invention to an electronic system.

Referring to FIG. 21 , an electronic system 900 includes an application processor 910, a connectivity module 920, a user interface 930, a non-volatile memory device 940, a memory module 950, and a power supply ( 960). For example, electronic system 900 may be a mobile system.

The application processor 910 may include a memory controller 911 . The application processor 910 may execute applications providing Internet browsers, games, videos, and the like. The communication module 920 may perform wireless communication or wired communication with an external device.

The memory module 950 may store data processed by the application processor 910 or may operate as a working memory. The memory module 950 may include a plurality of semiconductor memory devices 951 to 95q and a buffer chip 961 . The memory module 950 may be the memory module described above with reference to FIG. 19 .

The nonvolatile memory device 940 may store a boot image for booting the electronic system 900 . The user interface 920 may include one or more input devices, such as a keypad or touch screen, and/or one or more output devices, such as speakers or display devices. The power supply 960 may supply an operating voltage of the mobile system 900 .

The electronic system 900 or components of the electronic system 900 may be mounted using various types of packages.

Embodiments of the present invention may be usefully used in any electronic device and system including a semiconductor memory device. For example, embodiments of the present invention are PC (Personal Computer), server computer (server computer), cloud computer (cloud computer), data center (data center), workstation (workstation), laptop (laptop), mobile phone ( cellular), smart phone, MP3 player, PDA (Personal Digital Assistant), PMP (Portable Multimedia Player), digital TV, digital camera, portable game console, navigation device, wearable ( wearable) devices, IoT (Internet of Things) devices, IoE (Internet of Everything) devices, e-books, VR (Virtual Reality) devices, AR (Augmented Reality) devices, drones, automotive ( It can be more usefully applied to electronic systems such as automotive).

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention described in the claims below. you will understand that you can

Claims (20)

memory cell array; and
a plurality of data input/output pins for receiving write data to be stored in the memory cell array or outputting read data stored in the memory cell array;
Performs a burst operation in which one data set including a plurality of data bits is input or output through the plurality of data input/output pins based on one command received from the outside;
The number of the plurality of data input/output pins corresponds to a non-power-of-two integer, and the burst length (BL), which is a basic unit of the burst operation, is a power of 2 A semiconductor memory device corresponding to the excluded integer. According to claim 1,
the one data set includes the write data or the read data;
The plurality of data bits included in the one data set include first data bits corresponding to the write data or the read data,
The semiconductor memory device according to claim 1 , wherein the number of first data bits corresponds to an integer that is a power of 2. According to claim 2,
The one data set further includes additional data related to the write data or the read data,
Second data bits excluding the first data bits among the plurality of data bits included in the one data set correspond to the additional data. According to claim 3,
The semiconductor memory device according to claim 1 , wherein the number of second data bits corresponds to an integer that is a power of 2. According to claim 3,
The semiconductor memory device of claim 1 , wherein the number of the plurality of data bits including the first data bits and the second data bits corresponds to an integer excluding powers of 2. According to claim 3,
The additional data includes at least one of data bus inversion (DBI) information, error correction code (ECC) information, and meta data. According to claim 2,
The one data set further includes dummy data unrelated to the write data or the read data;
The semiconductor memory device of claim 1 , wherein second data bits excluding the first data bits among the plurality of data bits included in the one data set correspond to the dummy data. According to claim 1,
The semiconductor memory device according to claim 1, wherein the burst length corresponds to an integer that is a multiple of three. According to claim 1,
a clock divider configured to generate a second command clock signal based on the first command clock signal;
The semiconductor memory device of claim 1 , wherein the memory cell array and the plurality of data input/output pins operate based on the second command clock signal. According to claim 9,
The semiconductor memory device according to claim 1 , wherein the division ratio of the clock divider corresponds to an integer excluding powers of 2. According to claim 10,
The semiconductor memory device according to claim 1 , wherein a division ratio of the clock divider corresponds to an integer that is a multiple of 3. According to claim 9,
The semiconductor memory device according to claim 1 , wherein the memory cell array and the plurality of data input/output pins additionally operate based on a data clock signal. According to claim 12,
The semiconductor memory device of claim 1 , wherein a value obtained by dividing the period of the second command clock signal by the period of the data clock signal corresponds to an integer excluding powers of 2. According to claim 13,
wherein a value obtained by dividing the period of the second command clock signal by the period of the data clock signal corresponds to an integer that is a multiple of 3. According to claim 12,
The semiconductor memory device of claim 1 , wherein a value obtained by dividing the period of the first command clock signal by the period of the data clock signal corresponds to an integer that is a power of 2. According to claim 12,
A data processing path disposed between the memory cell array and the plurality of data input/output pins;
The semiconductor memory device of claim 1 , wherein the data processing path operates based on the second command clock signal and the data clock signal. According to claim 1,
The semiconductor memory device is a dynamic random access memory (DRAM). receiving a write command or a read command; and
performing a data write operation to store write data in a memory cell array or a data read operation to read read data stored in the memory cell array, based on the write command or the read command;
During the data write operation, the write data is received through a plurality of data input/output pins, and during the data read operation, the read data is output through the plurality of data input/output pins;
The operation of receiving the write data and the operation of outputting the read data is a burst in which one data set including a plurality of data bits is input or output through the plurality of data input/output pins based on one command. ) is performed based on the operation,
The number of the plurality of data input/output pins corresponds to a non-power-of-two integer, and the burst length (BL), which is a basic unit of the burst operation, is a power of 2 A method of driving a semiconductor memory device corresponding to an excluded integer. According to claim 18,
Generating a second command clock signal by dividing the first command clock signal;
The operation of receiving the write data and the operation of outputting the read data are performed based on the second command clock signal. memory cell array;
a plurality of data input/output pins for receiving write data to be stored in the memory cell array or outputting read data stored in the memory cell array;
a data processing path disposed between the memory cell array and the plurality of data input/output pins; and
a clock divider for generating a second command clock signal based on the first command clock signal;
Performs a data write operation to store the write data in the memory cell array based on a write command or performs a data read operation to read the read data stored in the memory cell array based on a read command;
The operation of receiving the write data and the operation of outputting the read data is a burst in which one data set including a plurality of data bits is input or output through the plurality of data input/output pins based on one command. ) is performed based on the operation,
The number of the plurality of data input/output pins corresponds to a non-power-of-two integer, and the burst length (BL), which is a basic unit of the burst operation, is a power of 2 Corresponds to integers excluded and integers that are multiples of three,
The plurality of data bits included in the one data set include first data bits corresponding to the write data or the read data, and the number of the first data bits corresponds to an integer that is a power of 2;
The memory cell array, the data processing path, and the plurality of data input/output pins operate based on a data clock signal and the second command clock signal;
The division ratio of the clock divider corresponds to an integer excluding powers of 2 and an integer that is a multiple of 3,
A value obtained by dividing the period of the second command clock signal by the period of the data clock signal corresponds to an integer excluding powers of 2 and an integer that is a multiple of 3.

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