KR20240021934A - Field effect transistor with reduced gate fringe area and method of manufacturing the same - Google Patents

Abstract

The semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip may be formed over the plurality of semiconductor active regions. Deep source/drain regions are formed by implanting dopants within the semiconductor active region rather than implanting dopant into the inter-electrode region of the shallow trench isolation structure. The gate strip is divided into gate stacks either before or after the formation of deep source/drain regions.

Description

Field effect transistor with reduced gate fringe area and method of manufacturing the same

Related applications

This application is related to U.S. Provisional Patent Application No. 17/496,099, filed on October 7, 2021; U.S. Provisional Patent Application No. 17/496,122, filed October 7, 2021; and U.S. regular continuation-in-part patent application Ser. No. 17/529,802, filed November 18, 2021, the entire contents of which are incorporated herein by reference for all purposes. .

Technology field

This disclosure relates generally to the field of semiconductor devices, and specifically to field effect transistors with reduced gate fringe areas and methods of manufacturing the same.

Prior art high voltage field effect transistors often suffer from surface breakdown voltage. These transistors often have complex expanded low-doping drain (LDD) structures to improve surface breakdown characteristics at the expense of increased process complexity and cost.

According to an aspect of the present disclosure, a semiconductor structure is provided, the structure comprising: first and second field effect transistors, each of the first and second field effect transistors comprising: a source region arranged along a first horizontal direction; a semiconductor active region including a channel region and a drain region; a gate dielectric in contact with the top surface of the channel region; a gate electrode overlying the gate dielectric and including a semiconductor gate electrode portion and a gate silicide region; and first and second field effect transistors including a dielectric gate spacer laterally surrounding the gate electrode; and a shallow trench isolation structure laterally surrounding each of the semiconductor active regions of the first and second two field effect transistors, wherein the shallow trench isolation structure is laterally isolated along the first horizontal direction. Contains two via cavities; The dielectric gate spacers of the first and second field effect transistors include downwardly protruding portions that fill the two via cavities in the shallow trench isolation structure.

According to another aspect of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising: first and second field effect transistors, each of the first and second field effect transistors comprising: a source arranged along a first horizontal direction; a semiconductor active region including a region, a channel region, and a drain region; a gate dielectric in contact with the upper surface of the channel region; a gate electrode overlying the gate dielectric and including a semiconductor gate electrode portion and a gate silicide region; and a pair of dielectric gate spacers located on opposite sides of the gate electrode; and a shallow trench isolation structure laterally surrounding each of the semiconductor active regions of the first and second two field effect transistors, wherein each of the pair of dielectric gate spacers has: an active-region overlying the semiconductor active region; -Upper gate spacer portion; and an active-region inter-gate spacer portion overlying a portion of the shallow trench isolation structure and including stepped sidewalls.

According to another aspect of the present disclosure, a method of forming a semiconductor device is provided, the method comprising: forming a shallow trench isolation structure in an upper region of a semiconductor substrate having a first conductivity type of doping, the shallow trench isolation structure comprising: laterally surrounding a plurality of semiconductor active regions that are patterned portions of the semiconductor substrate; Form a gate strip including a vertical stack of a gate electrode strip and a plurality of gate dielectrics over the plurality of semiconductor active regions, wherein the gate strip extends continuously as a single continuous structure across each of the plurality of semiconductor active regions and the shallow covering the inter-electrode region of the trench isolation structure; forming a source/drain extension region by implanting a dopant of a second conductivity type into surface portions of the plurality of semiconductor active regions that are not masked by the gate strip after formation of the gate strip; forming a deep source/drain region by implanting additional dopant of the second conductivity type within a portion of the plurality of semiconductor active regions without implanting additional dopant of the second conductivity type into the inter-electrode region of the shallow trench isolation structure. steps; and forming the gate strip by removing a portion of the gate strip overlying the inter-electrode region of the shallow trench isolation structure after forming the source/drain extension region and before or after forming the deep source/drain region. It includes dividing into gate stacks.

According to one aspect of the present disclosure, a semiconductor structure includes first and second field effect transistors and a shallow trench isolation structure. Each of the first and second field effect transistors includes a semiconductor active region including a source region, a channel region, and a drain region arranged along a first horizontal direction, a gate dielectric in contact with a top surface of the channel region, and a gate dielectric on the gate dielectric. It includes an overlying gate electrode, and a dielectric gate spacer laterally surrounding the gate electrode. The shallow trench isolation structure laterally surrounds each of the semiconductor active regions of the first and second two field effect transistors. The shallow trench isolation structure has a planar top surface between two via cavities extending in a first horizontal direction and located in an inter-gate region between gate electrodes of the first and second field effect transistors, and a dielectric gate spacer of the second field effect transistor including a downwardly protruding portion filling the two via cavities in the shallow trench isolation structure.

According to another aspect of the present disclosure, a field effect transistor includes a semiconductor active region including a source region, a channel region, and a drain region arranged along a first horizontal direction, a gate dielectric in contact with a top surface of the channel region, and the gate dielectric a gate electrode having overlying four sides, a dielectric gate spacer laterally surrounding the gate electrode on the four sides, and a second portion of the gate electrode extending in a second horizontal direction perpendicular to the first horizontal direction. It includes dielectric offset spacers located only on the sides of the dog. The gate dielectric spacer is in physical contact with the dielectric offset spacer across two sides of the gate electrode extending in the second horizontal direction, and the gate dielectric spacer is in physical contact with the dielectric offset spacer over two sides of the gate electrode extending in the first horizontal direction. It is in physical contact with the two sides.

According to another aspect of the present disclosure, a method of forming a semiconductor device includes forming a shallow trench isolation structure in an upper region of a semiconductor substrate having doping of a first conductivity type, the shallow trench isolation structure comprising patterning the semiconductor substrate. laterally surrounding a plurality of semiconductor active regions, the portion having longitudinal edges parallel to a first horizontal direction and laterally spaced apart along a second horizontal direction perpendicular to the first horizontal direction; Form a gate strip including a vertical stack of a gate electrode strip and a plurality of gate dielectrics over the plurality of semiconductor active regions, wherein the gate strip is located across each of the plurality of semiconductor active regions and between the plurality of semiconductor active regions. extending continuously as a single continuous structure over a portion of the shallow trench isolation structure, dopants of a second conductivity type within surface portions of the plurality of semiconductor active regions that are not masked by the gate strip after formation of the gate strip. forming a source/drain extension region by implanting, and dividing the gate strip into the gate stack by removing a portion of the gate strip located within a region of the shallow trench isolation structure after forming the source/drain extension region. Includes steps.

According to another aspect of the present disclosure, a semiconductor structure includes first and second field effect transistors and a shallow trench isolation structure. Each of the first and second field effect transistors includes a semiconductor active region including a source region, a channel region, and a drain region arranged along a first horizontal direction, a gate dielectric in contact with a top surface of the channel region, and a gate dielectric on the gate dielectric. It includes an overlying gate electrode, and a pair of dielectric gate spacers located on opposite sides of the gate electrode. The shallow trench isolation structure laterally surrounds each of the semiconductor active regions of the first and second two field effect transistors. Each of the pair of dielectric gate spacers includes an over-active region gate spacer portion overlying the semiconductor active region and including a straight inner sidewall perpendicular to the first horizontal direction; and an active-region inter-gate spacer portion overlying a portion of the shallow trench isolation structure and including stepped sidewalls, the stepped sidewalls comprising: a lower straight sidewall segment adjacent each pair of straight inner sidewalls; An upper straight sidewall segment laterally offset from the straight sidewall segment, and a connecting surface adjacent the upper edge of the lower straight sidewall segment and the lower edge of the upper straight sidewall segment.

According to another aspect of the present disclosure, a method of forming a semiconductor device is provided, the method comprising: forming a shallow trench isolation structure in an upper region of a semiconductor substrate having a first conductivity type of doping, the shallow trench isolation structure comprising: is a patterned portion of the semiconductor substrate, a plurality of semiconductor active regions having longitudinal edges parallel to a first horizontal direction and laterally spaced along a second horizontal direction perpendicular to the first horizontal direction. Surrounding laterally; forming a gate strip over the plurality of semiconductor active regions, the gate strip including a plurality of gate dielectrics and one gate electrode strip; forming a dielectric gate spacer around the gate strip; forming deep source/drain regions by implanting a dopant of a second conductivity type opposite to the first conductivity type into portions of the plurality of semiconductor active regions that are not masked by the gate strip and the dielectric gate spacer; and dividing the gate electrode strip into a plurality of gate electrodes laterally spaced along the second horizontal direction and overlying each of the plurality of semiconductor active regions after forming the deep source/drain regions.

1A is a vertical cross-sectional view of a first example structure after formation of a gate dielectric layer, a semiconductor gate electrode material layer, a silicon oxide capping layer, and a silicon nitride capping layer, according to one embodiment of the present disclosure.
FIG. 1B is a top view of the first exemplary structure of FIG. 1A. Vertical plane A - A' is the plane of the vertical section in Figure 1A.
2A is a vertical cross-sectional view of a first example structure after formation of a shallow trench, according to one embodiment of the present disclosure.
FIG. 2B is a top view of the first example structure of FIG. 2A. Vertical plane A - A' is the plane of the vertical section in Figure 2a.
3A is a vertical cross-sectional view of a first example structure after deposition of a layer of dielectric fill material, according to one embodiment of the present disclosure.
FIG. 3B is a top view of the first exemplary structure of FIG. 3A. Vertical plane A - A' is the plane of the vertical section in Figure 3a.
4A is a vertical cross-sectional view of a first example structure after deposition of a shallow trench isolation structure, according to an embodiment of the present disclosure.
FIG. 4B is a top view of the first example structure of FIG. 4A. Vertical plane A - A' is the plane of the vertical section in Figure 4A.
5A is a vertical cross-sectional view of a first example structure after removing the silicon nitride capping layer and the silicon oxide capping layer, according to an embodiment of the present disclosure.
FIG. 5B is a top view of the first example structure of FIG. 5A. Vertical plane A - A' is the plane of the vertical section in Figure 5A.
6A is a vertical cross-sectional view of a first example structure after formation of a metal gate electrode material layer and a gate cap dielectric layer, according to an embodiment of the present disclosure.
FIG. 6B is a top view of the first example structure of FIG. 6A. Vertical plane A - A' is the plane of the vertical section in Figure 6A.
7A is a vertical cross-sectional view of a first example structure after formation of a gate strip, according to one embodiment of the present disclosure.
FIG. 7B is a top view of the first example structure of FIG. 7A. Vertical plane A - A' is the plane of the vertical section in Figure 7A.
FIG. 7C is a vertical cross-sectional view of the first exemplary structure along vertical plane C-C' of FIG. 7B.
FIG. 7D is a vertical cross-sectional view of the first exemplary structure along vertical plane D—D' of FIG. 7C.
8A is a vertical cross-sectional view of a first example structure after formation of offset spacers and source/drain extension regions, according to one embodiment of the present disclosure.
FIG. 8B is a top view of the first example structure of FIG. 8A. Vertical plane A - A' is the plane of the vertical section in Figure 8A.
FIG. 8C is a vertical cross-sectional view of the first exemplary structure along vertical plane C-C' of FIG. 8B.
FIG. 8D is a vertical cross-sectional view of the first exemplary structure along vertical plane D—D' of FIG. 8C.
9A is a vertical cross-sectional view of a first example structure after application and patterning of a photoresist layer, according to one embodiment of the present disclosure.
FIG. 9B is a top view of the first example structure of FIG. 9A. Vertical plane A - A' is the plane of the vertical section in Figure 9a.
FIG. 9C is a vertical cross-sectional view of the first exemplary structure along vertical plane C-C' of FIG. 9B.
FIG. 9D is a vertical cross-sectional view of the first exemplary structure along vertical plane D—D' of FIG. 9C.
10A is a vertical cross-sectional view of a first example structure after patterning gate strips into a gate stack, according to one embodiment of the present disclosure.
FIG. 10B is a top view of the first example structure of FIG. 10A. Vertical plane A - A' is the plane of the vertical section in Figure 10A.
FIG. 10C is a vertical cross-sectional view of the first exemplary structure along vertical plane C-C' of FIG. 10B.
FIG. 10D is a vertical cross-sectional view of the first exemplary structure along vertical plane D—D' of FIG. 10B.
11A is a vertical cross-sectional view of a first example structure after formation of dielectric gate spacers, according to one embodiment of the present disclosure.
FIG. 11B is a top view of the first example structure of FIG. 11A. Vertical plane A - A' is the plane of the vertical section in FIG. 11A.
FIG. 11C is a vertical cross-sectional view of the first exemplary structure along vertical plane C-C' of FIG. 11B.
FIG. 11D is a vertical cross-sectional view of the first exemplary structure along vertical plane D—D' of FIG. 11B.
FIG. 12A is a vertical cross-sectional view of a first example structure after formation of deep source/drain regions, according to one embodiment of the present disclosure.
FIG. 12B is a top view of the first example structure of FIG. 12A. Vertical plane A - A' is the plane of the vertical section in Figure 12a.
FIG. 12C is a vertical cross-sectional view of the first exemplary structure along vertical plane C-C' of FIG. 12B.
FIG. 12D is a vertical cross-sectional view of the first exemplary structure along vertical plane D—D' of FIG. 12B.
FIG. 13A is a vertical cross-sectional view of a first example structure after formation of a dielectric liner and a contact level dielectric layer, according to an embodiment of the present disclosure.
FIG. 13B is a top view of the first example structure of FIG. 13A. Vertical plane A - A' is the plane of the vertical section in FIG. 13A.
FIG. 13C is a vertical cross-sectional view of the first exemplary structure along vertical plane C-C' of FIG. 13B.
FIG. 13D is a vertical cross-sectional view of the first exemplary structure along vertical plane D—D' of FIG. 13B.
14A is a vertical cross-sectional view of a first example structure after formation of a contact via structure, according to one embodiment of the present disclosure.
FIG. 14B is a top view of the first example structure of FIG. 14A. Vertical plane A - A' is the plane of the vertical section in FIG. 14A.
FIG. 14C is a vertical cross-sectional view of the first exemplary structure along vertical plane C-C' of FIG. 14B.
FIG. 14D is a vertical cross-sectional view of the first exemplary structure along vertical plane D—D' of FIG. 14B.
FIG. 15A is a vertical cross-sectional view of a second example structure after formation of dielectric gate spacers, according to an embodiment of the present disclosure.
FIG. 15B is a top view of the second exemplary structure of FIG. 15A. Vertical plane A - A' is the plane of the vertical section in FIG. 15A.
FIG. 15C is a vertical cross-sectional view of a second exemplary structure along vertical plane C-C' of FIG. 15B.
FIG. 15D is a vertical cross-sectional view of a second exemplary structure along vertical plane D—D' of FIG. 15B.
FIG. 16A is a vertical cross-sectional view of a second example structure after formation of deep source/drain regions, according to an embodiment of the present disclosure.
FIG. 16B is a top view of the second exemplary structure of FIG. 16A. Vertical plane A - A' is the plane of the vertical section in FIG. 16A.
FIG. 16C is a vertical cross-sectional view of a second exemplary structure along vertical plane C-C' of FIG. 16B.
FIG. 16D is a vertical cross-sectional view of the second exemplary structure along vertical plane D—D' of FIG. 16B.
FIG. 17A is a vertical cross-sectional view of a second example structure after application and patterning of a photoresist layer, according to one embodiment of the present disclosure.
FIG. 17B is a top view of the second exemplary structure of FIG. 17A. Vertical plane A - A' is the plane of the vertical section in FIG. 17A.
FIG. 17C is a vertical cross-sectional view of a second exemplary structure along vertical plane C-C' of FIG. 17B.
FIG. 17D is a vertical cross-sectional view of a second exemplary structure along vertical plane D—D' of FIG. 17B.
FIG. 18A is a vertical cross-sectional view of a second example structure after patterning gate strips into a gate stack, according to an embodiment of the present disclosure.
FIG. 18B is a top view of the second exemplary structure of FIG. 18A. Vertical plane A - A' is the plane of the vertical section in FIG. 18A.
FIG. 18C is a vertical cross-sectional view of a second exemplary structure along vertical plane C-C' of FIG. 18B.
FIG. 18D is a vertical cross-sectional view of the second exemplary structure along vertical plane D—D' of FIG. 18B.
FIG. 19A is a vertical cross-sectional view of a second example structure after removal of the photoresist layer, according to one embodiment of the present disclosure.
FIG. 19B is a top view of the second exemplary structure of FIG. 19A. Vertical plane A - A' is the plane of the vertical section in FIG. 19A.
FIG. 19C is a vertical cross-sectional view of a second exemplary structure along vertical plane C-C' of FIG. 19B.
FIG. 19D is a vertical cross-sectional view of the second exemplary structure along vertical plane D—D' of FIG. 19B.
FIG. 19E is a vertical cross-sectional view of a second exemplary structure along vertical plane E-E' of FIG. 19B.
FIG. 20A is a vertical cross-sectional view of a second example structure after formation of a dielectric liner and a contact level dielectric layer and contact via structure, according to an embodiment of the present disclosure.
FIG. 20B is a top view of the second exemplary structure of FIG. 20A. Vertical plane A - A' is the plane of the vertical section in Figure 20A.
FIG. 20C is a vertical cross-sectional view of a second exemplary structure along vertical plane C-C' of FIG. 20B.
FIG. 20D is a vertical cross-sectional view of the second exemplary structure along vertical plane D—D' of FIG. 20B.
FIG. 21A is a vertical cross-sectional view of a third example structure after formation of a gate dielectric layer, a first semiconductor gate electrode material layer, and a shallow trench isolation structure, according to an embodiment of the present disclosure.
FIG. 21B is a top view of the third example structure of FIG. 21A. Vertical plane A - A' is the plane of the vertical section in Figure 21A.
22A is a vertical cross-sectional view of a third example structure after formation of a second semiconductor gate electrode material layer, according to an embodiment of the present disclosure.
FIG. 22B is a top view of the third example structure of FIG. 22A. Vertical plane A - A' is the plane of the vertical section in FIG. 22A.
23A is a vertical cross-sectional view of a third example structure after formation of a gate strip, according to an embodiment of the present disclosure.
FIG. 23B is a top view of the third example structure of FIG. 23A. Vertical plane A - A' is the plane of the vertical section in Figure 7A.
FIG. 23C is a vertical cross-sectional view of a third exemplary structure along vertical plane C-C' of FIG. 23B.
FIG. 23D is a vertical cross-sectional view of a third exemplary structure along vertical plane D—D' of FIG. 23B.
FIG. 24A is a vertical cross-sectional view of a third example structure after formation of offset spacers and source/drain extension regions, according to an embodiment of the present disclosure.
FIG. 24B is a top view of the third exemplary structure of FIG. 24A. Vertical plane A - A' is the plane of the vertical section in FIG. 24A.
FIG. 24C is a vertical cross-sectional view of a third example structure along vertical plane C-C' of FIG. 24B.
FIG. 24D is a vertical cross-sectional view of a third exemplary structure along vertical plane D—D' of FIG. 24B.
FIG. 25A is a vertical cross-sectional view of a third example structure after patterning gate strips into a gate stack, according to an embodiment of the present disclosure.
FIG. 25B is a top view of the third exemplary structure of FIG. 25A. Vertical plane A - A' is the plane of the vertical section in FIG. 25A.
FIG. 25C is a vertical cross-sectional view of a third exemplary structure along vertical plane C-C' of FIG. 25B.
FIG. 25D is a vertical cross-sectional view of a third exemplary structure along vertical plane D—D' of FIG. 25B.
FIG. 26A is a vertical cross-sectional view of a third example structure after formation of dielectric gate spacers, according to an embodiment of the present disclosure.
FIG. 26B is a top view of the third exemplary structure of FIG. 26A. Vertical plane A - A' is the plane of the vertical section in FIG. 26A.
FIG. 26C is a vertical cross-sectional view of a third exemplary structure along vertical plane C-C' of FIG. 26B.
FIG. 26D is a vertical cross-sectional view of a third exemplary structure along vertical plane D—D' of FIG. 26B.
FIG. 27A is a vertical cross-sectional view of a third example structure after formation of deep source/drain regions and silicide regions, according to an embodiment of the present disclosure.
FIG. 27B is a top view of the third exemplary structure of FIG. 27A. Vertical plane A - A' is the plane of the vertical section in FIG. 27A.
FIG. 27C is a vertical cross-sectional view of a third exemplary structure along vertical plane C-C' of FIG. 27B.
FIG. 27D is a vertical cross-sectional view of a third exemplary structure along vertical plane D—D' of FIG. 27B.
FIG. 28A is a vertical cross-sectional view of a third example structure after formation of a dielectric liner and a contact level dielectric layer, according to an embodiment of the present disclosure.
FIG. 28B is a top view of the third exemplary structure of FIG. 28A. Vertical plane A - A' is the plane of the vertical section in FIG. 28A.
FIG. 28C is a vertical cross-sectional view of a third exemplary structure along vertical plane C-C' of FIG. 28B.
FIG. 28D is a vertical cross-sectional view of a third exemplary structure along vertical plane D—D' of FIG. 28B.
29A is a vertical cross-sectional view of a third example structure after formation of a contact via structure, according to an embodiment of the present disclosure.
FIG. 29B is a top view of the third exemplary structure of FIG. 29A. Vertical plane A - A' is the plane of the vertical section in FIG. 29A.
FIG. 29C is a vertical cross-sectional view of a third exemplary structure along vertical plane C-C' of FIG. 29B.
FIG. 29D is a vertical cross-sectional view of a third exemplary structure along vertical plane D—D' of FIG. 29B.
FIG. 29E is a vertical cross-sectional view of a third alternative example structure after formation of a contact via structure, according to an embodiment of the present disclosure.
FIG. 30A is a vertical cross-sectional view of a fourth example structure after formation of dielectric gate spacers, according to an embodiment of the present disclosure.
FIG. 30B is a top view of the fourth exemplary structure of FIG. 30A. Vertical plane A - A' is the plane of the vertical section in Figure 30A.
FIG. 30C is a vertical cross-sectional view of a fourth exemplary structure along vertical plane C-C' of FIG. 30B.
FIG. 30D is a vertical cross-sectional view of a fourth exemplary structure along vertical plane D—D' of FIG. 30B.
FIG. 31A is a vertical cross-sectional view of a fourth example structure after formation of deep source/drain regions, according to an embodiment of the present disclosure.
FIG. 31B is a top view of the fourth exemplary structure of FIG. 31A. Vertical plane A - A' is the plane of the vertical section in Figure 31A.
FIG. 31C is a vertical cross-sectional view of a fourth exemplary structure along vertical plane C-C' of FIG. 31B.
FIG. 31D is a vertical cross-sectional view of a fourth exemplary structure along vertical plane D—D' of FIG. 31B.
FIG. 32A is a vertical cross-sectional view of a fourth example structure after patterning gate strips into a gate stack, according to an embodiment of the present disclosure.
Figure 32B is a top view of the fourth exemplary structure of Figure 32A. Vertical plane A - A' is the plane of the vertical section in FIG. 32A.
FIG. 32C is a vertical cross-sectional view of a fourth exemplary structure along vertical plane C-C' of FIG. 32B.
FIG. 32D is a vertical cross-sectional view of a fourth exemplary structure along vertical plane D - D' of FIG. 32B.
Figure 33A is a vertical cross-sectional view of a fourth example structure after removal of the photoresist layer, according to one embodiment of the present disclosure.
FIG. 33B is a top view of the fourth exemplary structure of FIG. 33A. Vertical plane A - A' is the plane of the vertical section in FIG. 33A.
FIG. 33C is a vertical cross-sectional view of a fourth exemplary structure along vertical plane C-C' of FIG. 33B.
FIG. 33D is a vertical cross-sectional view of a fourth exemplary structure along vertical plane D—D' of FIG. 33B.
FIG. 33E is a vertical cross-sectional view of a fourth exemplary structure along vertical plane E-E' of FIG. 33B.
34A is a vertical cross-sectional view of a fourth example structure after formation of a silicide region, according to an embodiment of the present disclosure.
Figure 34B is a top view of the fourth exemplary structure of Figure 34A. Vertical plane A - A' is the plane of the vertical section in Figure 34A.
FIG. 34C is a vertical cross-sectional view of a fourth exemplary structure along vertical plane C-C' of FIG. 34B.
FIG. 34D is a vertical cross-sectional view of a fourth exemplary structure along vertical plane D—D' of FIG. 34B.
FIG. 35A is a vertical cross-sectional view of a fourth example structure after formation of a dielectric liner and a contact level dielectric layer and contact via structure, according to an embodiment of the present disclosure.
Figure 35B is a top view of the fourth exemplary structure of Figure 35A. Vertical plane A - A' is the plane of the vertical section in Figure 5A.
FIG. 35C is a vertical cross-sectional view of a fourth exemplary structure along vertical plane C-C' of FIG. 35B.
FIG. 35D is a vertical cross-sectional view of a fourth exemplary structure along vertical plane D—D' of FIG. 35B.
FIG. 35E is a vertical cross-sectional view of an alternative fourth exemplary structure after formation of a contact via structure, according to one embodiment of the present disclosure.

Embodiments of the present disclosure relate to field effect transistors with reduced gate fringe areas and methods of making the same, various aspects of which are now described in detail.

The drawings are not drawn to a certain scale. Where a single instance of an element is illustrated, multiple instances of an element may be duplicated, unless the absence of duplication of an element is explicitly stated or clearly indicated otherwise. Ordinal numbers such as “first,” “second,” and “third” are employed solely to identify similar elements, and different ordinal numbers may be employed throughout the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

Like reference numerals refer to the same or similar elements. Unless otherwise indicated, elements with the same reference numerals are assumed to have the same composition and same function. Unless otherwise indicated, “contact” between elements refers to direct contact between the elements that provides an edge or surface shared by the elements. When two or more elements are not in direct contact with or between each other, the two elements are “uncoupled” from or between each other. As used herein, a first element located “on” a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, a first element is “directly on” a second element when there is physical contact between the surface of the first element and the surface of the second element. As used herein, a first element is “electrically connected” to a second element if there is a conductive path of at least one conductive material between the first element and the second element. As used herein, a “prototype” structure or “in-process” structure refers to a temporary structure in which the shape or composition of at least one component therein is subsequently modified.

As used herein, “layer” refers to a portion of material that includes an area having a thickness. A layer may extend across the entirety of the underlying or overlying structure, or may have an extent that is less than that of the underlying or overlying structure. Additionally, a layer may be a region of a continuous structure, either homogeneous or non-homogeneous, having a thickness less than that of the continuous structure. For example, a layer may be located between any pair of horizontal planes on or between the top and bottom surfaces of a continuous structure. The layer may extend horizontally, vertically, and/or along a tapered surface. The substrate may be one layer, may include one or more layers therein, or may have one or more layers on, over, and/or under.

As used herein, “layer stack” refers to a stack of layers. As used herein, “line” or “line structure” refers to a layer having a predominant direction of extension, i.e., the direction in which the layer extends the most.

As used herein, “semiconductor material” refers to a material having an electrical conductivity ranging from 1.0×10 ⁻⁶ S/cm to 1.0×10 ⁵ S/cm. As used herein, “semiconductor material” refers to a material that has an electrical conductivity in the range of 1.0 × 10 ⁻⁶ S/cm to 1.0 × 10 ⁵ S/cm when no electrical dopant is present therein. When appropriately doped using , a doped material having an electrical conductivity ranging from 1.0 S/cm to 1.0 × 10 ⁵ S/cm can be produced. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band in a band structure, or an n-type dopant that adds electrons to the conduction band in a band structure. As used herein, “conductive material” refers to a material that has an electrical conductivity greater than 1.0×10 ⁵ S/cm. As used herein, “insulator material,” “insulating material,” or “dielectric material” refers to a material that has an electrical conductivity of less than 1.0×10 ⁻⁶ S/cm. As used herein, “heavily doped semiconductor material” refers to a semiconductor material that has been doped with an electrical dopant at a sufficiently high atomic concentration to render it conductive, i.e., to have an electrical conductivity greater than 1.0×10 ⁵ S/cm. refers to A “doped semiconductor material ^” may be a semiconductor material that is highly ^doped , or may be an electrical dopant (i.e., p It may be a semiconductor material containing a type dopant and/or an n-type dopant. “Intrinsic semiconductor material” refers to a semiconductor material that is not doped with an electrical dopant. Accordingly, the semiconductor material may be semiconducting or conductive and may be an intrinsic semiconductor material or a doped semiconductor material. Doped semiconductor materials can be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, “metallic material” refers to a conductive material containing at least one metallic element therein. All measurements of electrical conductivity are made under standard conditions.

As used herein, “field effect transistor” refers to any semiconductor device having a semiconductor channel through which current flows at a current density controlled by an external electric field. As used herein, “channel region” refers to the semiconductor region where the mobility of charge carriers is affected by an applied electric field. “Gate electrode” refers to a portion of conductive material that controls electron mobility in the channel region by application of an electric field. “Source region” refers to the doped semiconductor region that supplies charge carriers flowing through the channel region. “Drain region” refers to the doped semiconductor region that receives charge carriers supplied by the source region and passing through the channel region. “Source/drain region” refers to the source region of a field effect transistor or the drain region of a field effect transistor. “Source extension region” refers to a doped semiconductor region having the same type of doping as the source region and having a smaller dopant concentration, including the portion disposed between the source region and the channel region. “Drain extension region” refers to a doped semiconductor region having the same type of doping as the drain region and having a smaller dopant concentration, including the portion disposed between the drain region and the channel region. “Source/drain extension area” refers to either the source extension area or the drain extension area.

1A and 1B, a first example structure according to a first embodiment of the present disclosure is shown. The first example structure includes a stack of a gate dielectric layer 50L, a semiconductor gate electrode material layer 52L, a silicon oxide capping layer 42, and a silicon nitride capping layer 44 formed over a semiconductor substrate 8. .

The semiconductor substrate 8 includes a layer 10 of semiconductor material. The semiconductor substrate 8 may optionally comprise at least one further material layer in its lower part. In one embodiment, semiconductor substrate 8 may be a bulk semiconductor substrate comprised of a layer of semiconductor material 10 (e.g., a single crystal silicon wafer), or an underlying semiconductor material layer 10 (such as a silicon oxide layer). It may be a semiconductor-on-insulator (SOI) substrate including a buried insulator layer, and a handle substrate underlying the buried insulator layer. Alternatively, the semiconductor material layer 10 may include a layer of an epitaxial semiconductor (e.g., single crystal silicon) deposited on a semiconductor substrate (e.g., a silicon wafer) 8 or The upper portion of (8) may include a doped well (e.g., a doped silicon well).

The semiconductor material layer 10 may include a lightly doped semiconductor material portion (eg, a silicon portion) on which at least one field effect transistor may be formed. In one embodiment, the entire semiconductor material in semiconductor material layer 10 may include lightly doped semiconductor material. In other embodiments, the lightly doped semiconductor material can be a semiconductor well buried within another semiconductor material with a different dopant concentration and, optionally, an opposite conductivity type of doping. The dopant concentration of the lightly doped semiconductor material portion can be optimized for the body region of the at least one field effect transistor to be subsequently formed. ^For example, ^a lightly doped portion ^of semiconductor material may ^be electrically active ^{with an atomic} concentration in ^the range of 1.0 Dopants may be included, but smaller or larger atomic concentrations may also be used. The conductivity type of the portion of the semiconductor material layer 10 that is subsequently used as the body region of the field effect transistor is herein defined as a first conductivity type, which may be p-type for an n-type field effect transistor or n-type for a p-type field effect transistor. Referred to as conductive type.

The semiconductor material of the semiconductor material layer 10 may be an elemental semiconductor material (such as silicon) or an alloy of at least two elemental semiconductor materials (such as a silicon-germanium alloy), or (III-V compound semiconductor material or II-VI It may be a compound semiconductor material (such as a group compound semiconductor material), or it may be an organic semiconductor material. The thickness of semiconductor material layer 10 may range from 0.5 mm to 2 mm when semiconductor material layer 10 is a bulk semiconductor substrate. If the semiconductor material layer 10 is an insulator-on-insulator substrate, the thickness of the top semiconductor material layer within the semiconductor material layer 10 may range from 100 nm to 1,000 nm, although smaller and larger thicknesses may also be employed. You can.

Gate dielectric layer 50L, semiconductor gate electrode material layer 52L, silicon oxide capping layer 42, and silicon nitride capping layer 44 may be sequentially deposited on semiconductor substrate 8.

Gate dielectric layer 50L includes a dielectric material having a thickness suitable for operation of a high voltage field effect transistor. Gate dielectric layer 50L may be conformally formed on all physically exposed surfaces of semiconductor material layer 10, for example, by thermal oxidation of the physically exposed surface portions of semiconductor material layer 10. You can. If the semiconductor material layer 10 includes single crystal silicon, the gate dielectric layer may consist essentially of thermal silicon oxide. In one embodiment, gate dielectric layer 50L may consist essentially of a semiconductor oxide of the material of semiconductor substrate 8 and may have the same thickness throughout. The thickness of gate dielectric layer 50L may range from 6 nm to 100 nm, such as 10 nm to 60 nm, although smaller and larger thicknesses may also be employed.

Semiconductor gate electrode material layer 52L includes a doped semiconductor material, such as doped polysilicon. A semiconductor gate electrode material layer 52L may be deposited over the gate dielectric layer 50L. For example, semiconductor gate electrode material layer 52L may be deposited by chemical vapor deposition (CVD). The thickness of the semiconductor gate electrode material layer 52L may range from 30 nm to 300 nm, although smaller and larger thicknesses may also be employed.

Silicon oxide capping layer 42 includes a silicon oxide material, such as undoped silicate glass. Silicon oxide capping layer 42 may be deposited, for example, by chemical vapor deposition. The thickness of the silicon oxide capping layer 42 may range from 10 nm to 100 nm, although smaller or larger thicknesses may also be employed.

Silicon nitride capping layer 44 includes silicon nitride. Silicon nitride capping layer 44 may be deposited, for example, by chemical vapor deposition. The thickness of the silicon nitride caving layer 44 may range from 30 nm to 300 nm, although smaller and larger thicknesses may also be used.

2A and 2B, photoresist layer 17 may be applied over the first example structure and may be lithographically patterned into separate portions of photoresist material overlying each transistor active region 10A. there is. Each transistor active region 10A includes an area of each combination of the source region, channel region, and drain region of each field effect transistor to be subsequently formed. The transistor active area 10A is also referred to as the semiconductor active area.

An anisotropic etch process is performed through the silicon nitride capping layer 44, the silicon oxide capping layer 42, the semiconductor gate electrode material layer 52L, and the gate dielectric layer 50L, and over the semiconductor material layer 10. A shallow trench 19 extending vertically into the portion may be etched. Photoresist layer 17 may be used as an etch mask layer during an anisotropic etching process. The depth of the shallow trench 19, measured from a horizontal plane comprising the top surface of the semiconductor material layer 10, may range from 100 nm to 2,000 nm, such as 200 nm to 1,000 nm, although smaller and larger thicknesses are also employed. It can be.

Shallow trenches 19 may be interconnected with each other. A shallow trench 19 laterally surrounds each of the transistor active regions 10A. Transistor active area 10A is a portion of semiconductor material layer 10 located above a horizontal plane comprising the bottom surface of shallow trench 19 and laterally surrounded by a set of continuous sidewalls of shallow trench 19. In other words, each unetched portion of the semiconductor material layer 10 laterally surrounded by shallow trench 19 constitutes a transistor active region 10A. Photoresist layer 17 may subsequently be removed, for example by ashing.

3A and 3B, at least one dielectric fill material may be deposited within shallow trench 19 to form dielectric fill material layer 20L. The at least one dielectric fill material may include undoped silicate glass. The at least one dielectric fill material may be deposited by a conformal deposition process, such as a chemical vapor deposition process.

4A and 4B, a chemical mechanical planarization process may be performed to remove a portion of the dielectric fill material layer 20L on a horizontal plane including the top surface of the silicon nitride capping layer 44. The remaining portion of dielectric fill material layer 20L constitutes shallow trench isolation structure 20. Shallow trench isolation structure 20 may subsequently be vertically recessed such that the top surface of shallow trench isolation structure 20 is formed around a horizontal plane comprising the bottom surface of silicon nitride capping layer 44.

5A and 5B, the silicon nitride capping layer 44 may be removed selectively with respect to the shallow trench isolation structure 20 and the silicon oxide capping layer 42. For example, the silicon nitride capping layer 44 may be removed by performing a wet etch process using high temperature phosphoric acid. Subsequently, an etching process to etch the silicon oxide material of the silicon oxide capping layer 42 may be performed to selectively remove the silicon oxide capping layer 42 with respect to the material of the semiconductor gate electrode material layer 52L. In one embodiment, the etching process may include a wet etching process using dilute hydrofluoric acid. The top surface of the shallow trench isolation structure 20 may be vertically recessed during the etching process. In one embodiment, the top surface of shallow trench isolation structure 20 may be positioned about the height of the top surface of semiconductor gate electrode material layer 52L. Shallow trench isolation structure 20 may be formed into an upper portion of semiconductor substrate 8 through semiconductor gate electrode material layer 52L and gate dielectric layer 50L.

Generally, shallow trench isolation structure 20 may be formed in an upper region of semiconductor substrate 8 having a first conductivity type of doping. The shallow trench isolation structure 20 laterally surrounds the plurality of transistor active regions 10A, which are patterned portions of the semiconductor substrate 8, has a longitudinal edge parallel to the first horizontal direction hd1, and has a longitudinal edge parallel to the first horizontal direction hd1. 1 are laterally spaced apart along a second horizontal direction (hd2) perpendicular to the horizontal direction (hd1). In one embodiment, the shallow trench isolation structure 20 laterally surrounds each of the semiconductor active regions 10A of at least two field effect transistors arranged along the second horizontal direction hd2. In one embodiment, shallow trench isolation structure 20 may have a planar top surface located in a horizontal plane.

Referring to FIGS. 6A and 6B , the metal gate electrode material layer 54L may be deposited directly on the top surface of the semiconductor gate electrode material layer 52L. The metal gate electrode material layer 54L includes a metallic material, such as a transition metal, a conductive metallic nitride material (eg, TiN, TaN, or WN), or a metal silicide material. Metal gate electrode material layer 54L may be deposited by physical vapor deposition and/or chemical vapor deposition. The metal gate electrode material layer 54L may have a thickness ranging from 50 nm to 150 nm, although smaller and larger thicknesses may also be employed.

A gate cap dielectric layer 58L may subsequently be deposited over the metal gate electrode material layer 54L. Gate cap dielectric layer 58L may include a passivating dielectric material, such as silicon nitride. Gate cap dielectric layer 58L may be deposited, for example, by chemical vapor deposition. The thickness of gate cap dielectric layer 58L may range from 10 nm to 100 nm, such as 20 nm to 60 nm, although smaller and larger thicknesses may also be employed.

7A-7D, a photoresist layer (not shown) may be applied over gate cap dielectric layer 58L and patterned into discrete photoresist material portions by lithographic exposure and development. Each patterned portion of photoresist material can have the shape of a respective gate strip to be subsequently formed. In one embodiment, the transistor active area 10A may be arranged in at least one row of transistor active areas 10A arranged along the second horizontal direction hd2. In one embodiment, the transistor active area 10A may be arranged in multiple rows of transistor active areas 10A arranged along the second horizontal direction hd2. In this case, the illustrated portion of the first exemplary structure as shown in FIGS. 7A to 7D corresponds to two neighboring transistor active regions 10A arranged along the second horizontal direction hd2. In one embodiment, transistor active area 10A may be arranged as a two-dimensional periodic array, such as a two-dimensional periodic rectangular array.

Each portion of patterned photoresist material may have a respective rectangular horizontal cross-sectional shape with each pair of longitudinal sidewalls along the second horizontal direction hd2. In one embodiment, each patterned photoresist material portion is positioned in a second horizontal direction over a plurality of transistor active areas 10A, such as rows of transistor active areas 10A arranged along the second horizontal direction hd2. It may extend laterally along direction hd2.

An anisotropic etching process is performed to form a pattern of the patterned photoresist material portion into a gate cap dielectric layer 58L, a metal gate electrode material layer 54L, a semiconductor gate electrode material layer 52L, and a gate dielectric layer 50L. It can be delivered through. Unmasked areas of shallow trench isolation structure 20 may be incidentally recessed during the anisotropic etch process.

Gate strips 50, 52, 54S, and 58S may be formed on each row of the transistor active region 10A arranged along the second horizontal direction hd2. Each of the gate strips 50, 52, 54S, and 58S is patterned with a gate cap dielectric layer 58L, a metal gate electrode material layer 54L, a semiconductor gate electrode material layer 52L, and a gate dielectric layer 50L. Includes the parts that are For example, each of the gate strips 50, 52, 54S, and 58S includes a plurality of gate dielectrics 50, which are patterned portions of the gate dielectric layer 50L, and a patterned portion of the semiconductor gate electrode material layer 52L. A plurality of semiconductor gate electrode portions 52 that are a portion, a metal gate electrode strip 54S that is a patterned portion of the metal gate electrode material layer 54L, and a gate cap that is a patterned portion of the gate cap dielectric layer 58L. Includes dielectric strip 58S. An adjacent combination of a plurality of semiconductor gate electrode portions 52 and metal gate electrode strips 54A constitute gate electrode strips 52 and 54S. Gate electrode strips 52, 54S extend continuously as a single continuous structure over each transistor active region 10A within a row of transistor active regions 10A. Each gate electrode strip 52, 54S includes a pair of longitudinal side walls extending laterally along the second horizontal direction hd2 and laterally spaced along the first horizontal direction by the gate length GL. can do. In one embodiment, each gate electrode strip 52, 54S includes a semiconductor gate electrode that extends laterally along the first horizontal direction hd1 and contacts a respective sidewall surface segment of shallow trench isolation structure 20. Portion 52 may include a plurality of surface segments, such as sidewalls.

8A to 8D, offset spacers 55 may be selectively formed on sidewalls of gate strips 50, 52, 54S, and 58S. Offset spacers 55 may be formed by conformal deposition of a thin dielectric liner and an anisotropic etch process to remove horizontally extending portions of the thin dielectric liner and/or a surface of the physically exposed surface of semiconductor gate electrode portion 52. Can be formed by oxidation. The lateral thickness of offset spacer 55, if present, may range from 0.3 nm to 20 nm, such as 1 nm to 6 nm, although smaller and larger thicknesses may also be employed. The offset spacer 55 may include silicon oxide, silicon nitride, or a silicon oxide/silicon nitride double layer.

Electrical dopant of the second conductivity type is within the unmasked portion of the semiconductor material layer 10 that is not masked by the gate strips 50, 52, 54S, 58S to form source/drain extension regions 31, 39. can be injected The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The source/drain extension regions 31 and 39 may include, for example, a source extension region 31 and a drain extension region 39 . Typically, each of the source/drain extensions 31, 39 is doped with an opposite conductivity type than the conductivity type of the remainder of the transistor active region 10A from which each of the source/drain extensions 31, 39 is formed. You can have it. For example, if transistor active area 10A has a doping of a first conductivity type, source/drain extension regions 31, 39 formed within the surface area of transistor active area 10A have a doping opposite to the first conductivity type. It has a second conductivity type of doping. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant atomic concentration of the source/drain region 31 may range from 1.0 x 10 ¹⁸ /cm ³ to 1.0 x 10 ²⁰ /cm ³ , although lower or higher dopant concentrations may also be used. Accordingly, extension regions (i.e., lDD regions) 31 and 39 are implanted before separating the gate strips 50, 52, 54S, and 58S into gate electrodes. The gate strip blocks the LDD implant process from doping the edge region of the transistor active region 10A below the gate strip in the gate fringe region. Avoiding doping the gate fringe region at the edge of each transistor active region 10A doping prevents or reduces leakage current paths through the gate fringe region and reduces transistor leakage current.

9A-9D, a photoresist layer 47 can be applied over the first example structure and lithographically patterned to form gate strips 50, 52 overlying the top surface of the shallow trench isolation structure 20. , 54S, 58S), an opening 47A can be formed. Typically, patterned photoresist layer 47 can cover the entire area of each transistor active region 10A, with gate strips 50, 52, 54S, and 58S subsequently cut (i.e., transistor A rectangular opening 47A may be included in the gate fringe area between the active areas 10A. In other words, the area of the openings 47A of the patterned photoresist layer 47 corresponds to the gate fringe area from which portions of the gate strips 50, 52, 54S, and 58S are subsequently removed. In one embodiment, the patterned photoresist layer is arranged along the second horizontal direction hd2 and overlies the shallow trench isolation structure 20 and forms a layer of the underlying gate strips 50, 52, 54S, and 58S. It includes rows of openings 47A with area overlap with each portion. In one embodiment, rows of rectangular openings 47A may be formed in patterned photoresist layer 47 over each gate strip 50, 52, 54S, 58S.

In one embodiment, each rectangular opening 47A of patterned photoresist layer 47 may have a first pair of straight sidewalls and a second pair of straight sidewalls. The first pair of straight sidewalls may extend laterally along a first horizontal direction hd1 and extend along the gate length GL of the underlying gate strips 50, 52, 54S, 58S (i.e., along the first horizontal direction hd1). It has a length greater than the lateral dimension along direction hd1). As shown in FIG. 9D , the second pair of sidewalls may extend laterally along a second horizontal direction hd2 and may overlie and contact respective portions of shallow trench isolation structure 20 . Accordingly, the second sidewall has no area overlap with the underlying gate strips 50, 52, 54S, 58S. The second pair of sidewalls of each opening 47A in patterned photoresist layer 47 also does not have any area overlap with any of the transistor active regions 10A.

As shown in Figure 9D, a top portion of shallow trench isolation structure 20 is exposed within opening 47A. Specifically, a pair of rectangular top segments of shallow trench isolation structure 20 may be physically exposed within the area of each opening 47A in patterned photoresist layer 47. Additionally, a rectangular surface segment of the top of gate cap dielectric strip 58S may be physically exposed within the area of each opening 47A in patterned photoresist layer 47. The width of each rectangular opening 47A of the patterned photoresist layer 47 along the second horizontal direction hd2 is the width between neighboring pairs of transistor active regions 10A along the second horizontal direction hd2. It may be smaller than the lateral spacing. The length of each rectangular opening 47A in the patterned photoresist layer 47 along the first horizontal direction hd1 is greater than the gate length GL of the underlying gate strips 50, 52, 54S, 58S. It may be large, which is the width of the underlying gate strips 50, 52, 54S, and 58S along the first horizontal direction hd1.

Referring to FIGS. 10A to 10D , the unmasked portion of each gate strip 50, 52, 54S, and 58S may be etched by performing an anisotropic etching process. The etching process is performed after implantation of the extended regions (i.e., lDD regions) 31 and 39 into the transistor active region 10A. The row pattern of openings 47A in patterned photoresist layer 47 may be transferred through gate strips 50, 52, 54S, 58S and into unmasked areas of shallow trench isolation structure 20. The unmasked portion of the offset spacer 55 may be incidentally removed during the anisotropic etching process. The unmasked portion of shallow trench isolation structure 20 may be vertically recessed to form via cavity 11 . A pair of via cavities 11 extending vertically into shallow trench isolation structure 20 may be formed within each opening within a row of openings in patterned photoresist layer 47 .

Each of the gate strips 50, 52, 54S, 58S is separated from the gate stack 50 by removing a portion of each gate strip 50, 52, 54S, 58S located within the gate fringe region overlying the shallow trench isolation structure 20. , 52, 54, 58). Each gate stack 50, 52, 54, 58 includes a vertical stack of a gate dielectric 50, a semiconductor gate electrode portion 52, a metal gate electrode portion 54, and a gate cap dielectric 58. Each metal gate electrode portion 54 is a patterned portion of a respective metal gate electrode strip 54S. Each gate cap dielectric 58 is a patterned portion of a gate cap dielectric strip 58S. Each gate dielectric 50 is one of a plurality of gate dielectrics 50 within each of the gate strips 50, 52, 54S, and 58S. Each adjacent combination of semiconductor gate electrode portion 52 and metal gate electrode portion 54 constitutes gate electrodes 52 and 54. Accordingly, each of the gate electrodes 52 and 54 is a patterned portion of a respective gate electrode strip 52 and 54S.

Each of the gate stacks 50, 52, 54, and 58 is formed on each of the transistor active areas 10A. Each gate stack includes a gate dielectric 50 and gate electrodes 52 and 54. In one embodiment, each of gate stacks 50, 52, 54, and 58 includes a pair of peripheral regions (PR) located within a gate fringe region, and in plan view along a vertical direction perpendicular to the top surface of semiconductor substrate 8. has area overlap with the shallow trench isolation structure 20.

A pair of via cavities 11 may be formed under each opening 47A in the patterned photoresist layer 47. The pair of via cavities 11 includes a pair of proximal side walls 11P laterally spaced along the first horizontal direction hd1 by a first spacing S1, which is the gate spacer inner side wall spacing, i.e. Also referred to as the gap between a pair of inner sidewalls of a subsequently formed gate spacer. In one embodiment, the pair of via cavities 11 have a pair of distal sidewalls laterally spaced along the first horizontal direction hd1 by a second spacing S2, also referred to as the trench distal sidewall spacing. Includes (11D).

Each region of shallow trench isolation structure 20 located within a region located between adjacent pairs of gate dielectrics 50 is referred to herein as an inter-gate region. Each inter-gate region of the shallow trench isolation structure 20 is in contact with a respective lower surface segment of an adjacent pair of gate electrodes 52, 54, such as a lower surface segment of the metal gate electrode portion 54 of the adjacent pair. It includes a pair of uppermost horizontal segments (THSS) of a shallow trench isolation structure 20 that Additionally, each inter-gate region of shallow trench isolation structure 20 is adjacent to the uppermost horizontal plane segment by a pair of vertical plane segments and includes an intermediate horizontal plane segment (IHSS) located between each pair of via cavities 11. . The middle horizontal plane segment is physically exposed beneath the opening 47A of the patterned photoresist layer 47.

In one embodiment, the intermediate horizontal plane segment (IHSS) is located above a horizontal plane comprising a planar top surface of the shallow trench isolation structure 20 covered by a patterned photoresist layer 47. In one embodiment, the bottom surface of via cavity 11 is located below a horizontal plane comprising the planar top surface of shallow trench isolation structure 20 covered by patterned photoresist layer 47.

In one embodiment, each via cavity 11 includes a pair of stepped proximal side walls with each horizontal step located between an upper vertical proximal side wall segment and a lower vertical proximal side wall segment. The pair of lower vertical proximal side wall segments may be laterally spaced from each other by a first spacing S1. The pair of upper vertical proximal sidewall segments may be laterally spaced from each other by a gate length (GL).

In one embodiment, each via cavity 11 has a pair of first sidewalls 111 parallel to the first horizontal direction hd1 and vertically coincident with the widthwise sidewalls of neighboring pairs of gate electrodes 52 and 54. ), and a pair of second side walls (e.g., the proximal side wall 11P and the distal side wall 11D) perpendicular to the first horizontal direction hd1 and adjacent to the vertically extending edges of the pair of first side walls 111. Includes. In one embodiment, each gate electrode 52, 54 has a pair of longitudinal electrodes perpendicular to the first horizontal direction hd1 and laterally spaced along the first horizontal direction hd1 by the gate length GL. Includes side walls. In one embodiment, the pair of second side walls 11P of each via cavity 11 includes a pair of side wall segments (stepped side walls) laterally spaced apart along the first horizontal direction by the gate length GL. 11P), which is the upper straight side wall segment).

In one embodiment, each gate electrode 52, 54 is laterally spaced along the first horizontal direction hd1 by a gate length GL and extends laterally along the second horizontal direction hd2. It includes a pair of longitudinal side walls. As shown in FIG. 10D, the lateral spacing between a pair of horizontal steps 11H of a pair of stepped proximal sidewalls 11P over each inter-gate region of shallow trench isolation structure 20 is equal to the gate length. Same as (GL).

In one embodiment, each gate electrode 52, 54 has a semiconductor gate electrode portion 52 in contact with the respective top surface of the gate dielectric 50, and a metal gate electrode portion 54 overlying the semiconductor gate electrode portion 52. ) includes. In one embodiment, semiconductor gate electrode portion 52 contacts a sidewall of a region between a pair of gates of shallow trench isolation structure 20. In one embodiment, the semiconductor gate electrode portion includes a top surface located in the same horizontal plane as a topmost segment of a region between a pair of gates of shallow trench isolation structure 20. In one embodiment, metal gate electrode portion 54 contacts a topmost segment of a region between a pair of gates of shallow trench isolation structure 20.

In one embodiment shown in FIG. 10B, the longitudinal sidewall of the metal gate electrode portion 54 perpendicular to the first horizontal direction hd1 is adjacent to the semiconductor gate electrode portion 52 in each of the gate electrodes 52 and 54. It coincides vertically with the longitudinal side wall. However, as shown in FIG. 10C, the width direction sidewall of the metal gate electrode portion 54 parallel to the first horizontal direction hd1 is adjacent to the semiconductor gate electrode portion 52 in each of the gate electrodes 52 and 54. It is laterally offset outward from the widthwise sidewall.

11A-11D, patterned photoresist layer 47 may be removed, for example, by ashing. The dielectric gate spacer material layer may be deposited conformally, and an anisotropic etch process may be performed to remove horizontally extending portions of the dielectric gate spacer material layer. The dielectric gate spacer material layer includes a dielectric material, such as silicon oxide and/or silicon nitride, and may be formed by at least one chemical vapor deposition process, such as at least one low pressure chemical vapor deposition (LPCVD) process. The remaining portion of the dielectric gate spacer material layer includes dielectric gate spacers 56 laterally surrounding each of the gate stacks 50, 52, 54, and 58. In an illustrative example, each dielectric gate spacer 56 has a thickness of 5 nm to 100 nm, such as 10 nm to 50 nm, measured along the first horizontal direction hd1 over transistor active area 10A between the inner and outer sidewalls. It can have a range of widths, but smaller and larger widths can also be employed.

According to one aspect of the present disclosure, the thickness of the dielectric gate spacer material layer is 1 of the spacing between adjacent pairs of laterally spaced gate stacks 50, 52, 54, 58 along the second horizontal direction hd2. It can be greater than /2. For example, the thickness of the dielectric gate spacer material layer may vary depending on the thickness of each opening 47A in patterned photoresist layer 47, as employed in the processing steps of FIGS. 9A-9D and 10A-10D. It can be larger than 1/2 the width. In this case, the vertical growth surface of the dielectric gate spacer material layer forms a seam between each neighboring pair 50, 52, 54, 58 of laterally spaced gate stacks along the second horizontal direction hd2. ) are merged to form. After the anisotropic etching process to form the dielectric gate spacers 56, neighboring pairs of dielectric gate spacers 56 arranged along the second horizontal direction hd2 are positioned midway between neighboring pairs of dielectric gate spacers 56. are positioned and contact each other in a vertical plane extending along the first horizontal direction (hd2). All gate-to-gate regions of shallow trench isolation structure 20 may be covered by dielectric gate spacers 56.

In general, each neighboring pair of dielectric gate spacers 56 laterally spaced along the second horizontal direction hd1 may contact each other along a respective vertical plane parallel to the first horizontal direction hd1. . In one embodiment, the outer transverse sidewalls of neighboring pairs of dielectric gate spacers 56 have vertical vertical extensions extending laterally along a first horizontal direction hd1 above each inter-gate region of shallow trench isolation structure 20. They come into contact with each other in the meeting.

Each via cavity 11 may be filled by a downwardly protruding portion of each pair of dielectric gate spacers 56 . Each neighboring pair of dielectric gate spacers 56 arranged along the second horizontal direction hd2 has a pair of via cavities 11 filled with the downwardly protruding portions of each neighboring pair of dielectric gate spacers 56. ) may be in contact with each other across the respective inter-gate regions of the shallow trench isolation structure 20, including.

In one embodiment, each dielectric gate spacer 56 is directed toward a respective gate electrode 52, 54 and extends laterally along a second horizontal direction hd2 and by a first spacing S1, That is, it includes a pair of inner longitudinal side walls that are laterally spaced apart along the first horizontal direction hd1 by the distance between the inner side walls of the gate spacer 55. In one embodiment, each dielectric gate spacer 56 faces away from each gate electrode 52, 54 and extends laterally along a second horizontal direction hd2, herein outside the gate spacer. It comprises a pair of outer longitudinal side walls, laterally spaced apart by a third spacing S3, referred to as the side wall spacing. In one embodiment, third spacing S3 (i.e., gate spacer outer sidewall spacing) may be greater than second spacing S2 (i.e., trench distal sidewall spacing).

In one embodiment, each gate-to-gate region of the shallow trench isolation structure is adjacent a respective topmost segment of the gate-to-gate region of the shallow trench isolation structure 20 and is contacted by a respective sidewall of the dielectric gate spacer 56. , comprising a pair of side wall segments extending laterally along the first horizontal direction hd1. In one embodiment, dielectric gate spacer 56 may include four downwardly protruding portions extending vertically into four via cavities 11 within shallow trench isolation structure 20 . In one embodiment, shallow trench isolation structure 20 may have a planar top surface located in a horizontal plane and in an area not covered by gate electrodes 52, 54 or by dielectric gate spacer 56.

Accordingly, the dielectric offset spacer 55 is formed only on two sides of each of the gate electrodes 52 and 54 extending in the second horizontal direction hd2 and the gate electrode 52 extending in the vertical first horizontal direction hd1. 54) Absent on each of the other two sides. In contrast, gate dielectric spacer 56 laterally surrounds each of gate electrodes 52, 54 on all four sides. Accordingly, the gate dielectric spacer 56 is in physical contact with the dielectric offset spacer 55 located on two sides of each of the gate electrodes 52 and 54 extending in the second horizontal direction hd2, and the gate dielectric spacer ( 56) is in physical contact with the other two sides of each of the gate electrodes 52 and 54 extending in the first horizontal direction hd1.

12A-12D, additional electrical dopants of the second conductivity type are present in the gate stacks 50, 52, 54, 58, and in the masking of the semiconductor material layer 10 that is not masked by the dielectric gate spacer 56. It may be injected into the unapplied portion to form deep source/drain regions 32 and 38.

According to one aspect of the present disclosure, the gap between adjacent pairs of gate electrodes 52 and 54 laterally spaced apart along the second horizontal direction hd2 is filled with a pair of dielectric gate spacers 56. Accordingly, additional electrical dopant of the second conductivity type is present in the portion of the transistor active region 10A proximate to the width edge of the gate cap dielectric 58 and metal gate electrode portion 54 parallel to the first horizontal direction hd1. not injected This property provides a second type of conductivity into the peripheral portion of the semiconductor active region 10A proximate to the widthwise edge of the metal gate electrode portion 54 and the gate cap dielectric 58 parallel to the first horizontal direction hd1. This allows reduction of the lateral spacing between neighboring pairs of semiconductor active regions 10A without concern for collateral injection of dopants.

Deep source/drain regions 32 and 38 may include, for example, a deep source region 32 and a deep drain region 38. Typically, the atomic concentration of dopants in the deep source/drain regions (32, 38) is greater than the atomic concentration of dopants in the extended source/drain regions (31, 39). In this way, the volume of the source/drain extension regions 31, 39 that overlaps the volume of the deep source/drain regions 32, 38 is incorporated into each one of the deep source/drain regions 32, 38. In one embodiment, the atomic concentration of dopant in the deep source/drain regions 32, 38 may range from 5.0 × 10 ¹⁸ /cm ³ to 2.0 × 10 ²¹ /cm ³ , although lower or higher dopant concentrations may also be used. can be hired.

The unimplanted portion of each transistor active region 10A constitutes a channel region 36. Each channel region 36 may have an atomic concentration of a dopant of the first conductivity type ranging from 1.0 x 10 ¹⁴ /cm ³ to 1.0 x 10 ¹⁸ /cm ³ , although smaller and larger dopant concentrations may also be employed. . Each of the source/drain extension regions 31, 39 and each of the deep source/drain regions 32, 38 each adjacent combination comprises a combination of the source extension regions 31 and the deep source regions 32. It constitutes a source/drain region, which may be a source region (31, 32) or a drain region (38, 39) comprising a combination of a drain extension region (39) and a deep drain region (38). In general, source regions 32, 32 and drain regions 38, 39 may be formed in portions of each transistor active region 10A laterally spaced from each other by respective channel regions 36.

13A-13D, at least one dielectric liner 62, 64 may be selectively formed over the physically exposed surface of the first example structure by at least one conformal deposition process. The at least one dielectric liner 62, 64 may include a stack of a silicon oxide liner 62 and a silicon nitride liner 64, for example. Contact level dielectric layer 80 includes gate stacks 50, 52, 54, 58, source/drain regions {(31, 32), (38, 39)}, shallow trench isolation structures 20, and optionally at least It can be deposited over one dielectric liner (62, 64). Contact level dielectric layer 80 includes a dielectric material such as silicon oxide. A planarization process, such as a chemical mechanical planarization process, may optionally be performed to planarize the top surface of the contact level dielectric layer 80. The vertical distance between the top surface of the contact level dielectric layer 80 and the top surface of the gate cap dielectric 58 may range from 50 nm to 500 nm, although smaller and larger vertical distances may also be employed.

14A-14C, a contact via cavity may be formed through the contact level dielectric layer 80 and filled with at least one conductive material, such as at least one metallic material. The excess portion of at least one conductive material may be removed from above the horizontal plane comprising the top surface of the contact level dielectric layer 80 by a planarization process, which may include a recess etch process and/or a chemical mechanical planarization process. . Each remaining portion of at least one conductive material constitutes a contact via structure 82, 85, 88. The contact via structures 82, 85, and 88 include a source contact via structure 82 contacting each of the source regions 31 and 32, a drain contact via structure 88 contacting each of the drain regions 38 and 39, and It may include a gate contact via structure 85 in contact with each of the gate electrodes 52 and 54.

1A-14D comprehensively and according to various embodiments of the present disclosure, the semiconductor structure includes a first field effect transistor 100A, a second field effect transistor 100B, and a shallow trench isolation structure 20. . Each of the first and second field effect transistors (100A, 100B) includes a source region (31, 32), a channel region (36), and a drain region (38, 39) arranged along the first horizontal direction (hd1). The semiconductor active region 10A, the gate dielectric 50 in contact with the upper surface of the channel region 36, the gate electrodes 52 and 54 placed on the gate dielectric 50, and the gate electrodes 52 and 54 are laterally It includes a dielectric gate spacer 56 surrounding the . The shallow trench isolation 20 structure laterally surrounds each of the semiconductor active regions 10A of the first and second two field effect transistors 100A and 100B. The shallow trench isolation structure 20 extends in the first horizontal direction hd1 and is located within the inter-gate region between the gate electrodes 52 and 54 of the first and second field effect transistors 100A and 100B. Having a planar top surface between the two via cavities 11, the dielectric gate spacers 56 of the first and second field effect transistors 100A, 100B are positioned between the two via cavities 11 in the shallow trench isolation structure 20. Includes a downwardly protruding portion that fills the .

In one embodiment, the dielectric offset spacer 55 is located only on two sides of each of the gate electrodes 52 and 54 extending in the second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Gate dielectric spacers 56 laterally surround each of the gate electrodes 52, 54 on all four sides. The gate dielectric spacer 56 is in physical contact with a dielectric offset spacer 55 spanning two sides of each of the gate electrodes 52 and 54 extending in the second horizontal direction h2, and the gate dielectric spacer 56 is Each of the gate electrodes 52 and 54 extending in the first horizontal direction hd1 is in physical contact with the other two sides.

In one embodiment, each dielectric gate spacer 56 faces a respective gate electrode 52, 54 and extends laterally along a second horizontal direction hd2 (first gap S1 and a pair of inner longitudinal sidewalls laterally spaced apart along a first horizontal direction (hd1) by the gate spacer inner sidewall spacing; The pair of via cavities 11 includes a pair of proximal sidewalls 11P laterally spaced apart along the first horizontal direction hd1 by the gate spacer inner sidewall spacing.

In one embodiment, each dielectric gate spacer 56 points away from each gate electrode 52, 54 and extends laterally along a second horizontal direction hd2 (third gap S3 ), comprising a pair of outer longitudinal sidewalls laterally spaced along a first horizontal direction (hd1) by a gate spacer outer sidewall spacing; The pair of via cavities 11 are positioned along the first horizontal direction hd1 by a trench distal sidewall spacing (such as second spacing S2) that is less than the gate spacer external sidewall spacing (such as third spacing S3). It includes a pair of laterally spaced distal side walls 11D.

In one embodiment, the outer widthwise sidewalls of neighboring pairs of dielectric gate spacers 56 have vertical vertical extensions extending laterally along a first horizontal direction hd1 above each inter-gate region of shallow trench isolation structure 20. They come into contact with each other in the meeting.

In one embodiment, each inter-gate region of shallow trench isolation structure 20 includes: a pair of uppermost horizontal plane segments THSS contacting each lower surface segment of a neighboring pair of gate electrodes 52, 54; and an intermediate horizontal plane segment (IHSS) located between each pair of via cavities 11 and adjacent to the uppermost horizontal plane segment (THSS) by a pair of vertical plane segments. In one embodiment, the intermediate horizontal surface segment (IHSS) is located above the planar top surface of the shallow trench isolation structure 20.

In one embodiment, the lower surface of via cavity 11 is located below the planar upper surface of shallow trench isolation structure 20. In one embodiment, each via cavity 11 includes a pair of stepped proximal side walls with each horizontal step located between an upper vertical proximal side wall segment and a lower vertical proximal side wall segment; Each gate electrode 52, 54 includes a pair of longitudinal side walls laterally spaced apart along the first horizontal direction hd1 by the gate length GL; The lateral spacing between a pair of horizontal steps of a pair of stepped proximal sidewalls over each inter-gate region of the shallow trench isolation structure 20 is equal to the gate length GL.

In one embodiment, each of the gate electrodes 52 and 54 includes a semiconductor gate electrode portion 52 that contacts the upper surface of each gate dielectric 50; and a metal gate electrode portion 54 overlying the semiconductor gate electrode portion 52. In one embodiment, the semiconductor gate electrode portion 52 contacts the sidewall of a region between a pair of gates of the shallow trench isolation structure 20; The semiconductor gate electrode portion 52 includes a top surface located in the same horizontal plane as the uppermost segment of the region between the pair of gates of the shallow trench isolation structure 20; The metal gate electrode portion 54 contacts the uppermost segment of the region between the pair of gates of the shallow trench isolation structure 20.

In one embodiment, the longitudinal sidewall of the metal gate electrode portion 54 perpendicular to the first horizontal direction hd1 vertically coincides with the longitudinal sidewall of the semiconductor gate electrode portion 52; The widthwise sidewall of the metal gate electrode portion 54 parallel to the first horizontal direction hd1 is laterally offset outward from the widthwise sidewall of the semiconductor gate electrode portion 52; Each gate-to-gate region of shallow trench isolation structure 20 is adjacent a respective topmost segment of the gate-to-gate region of shallow trench isolation structure 20 and is contacted by a respective sidewall of dielectric gate spacer 56. 1 comprising a pair of side wall segments extending laterally along the horizontal direction (hd1).

In one embodiment, each dielectric gate spacer 56 in the first and second field effect transistors 100A, 100B has four via cavities 11 extending vertically into four via cavities 11 in the shallow trench isolation structure 20. Includes a downward protruding portion.

In one embodiment, each via cavity 11 has: a pair of first sidewalls parallel to the first horizontal direction hd1 and perpendicular to the widthwise sidewalls of neighboring pairs of gate electrodes 52, 54; (111); and a pair of second side walls (such as the proximal side wall 11P and the distal side wall 11D) perpendicular to the first horizontal direction hd1 and adjacent the vertically extending edges of the pair of first side walls 111. . In one embodiment, each gate electrode 52, 54 has a pair of longitudinal electrodes perpendicular to the first horizontal direction hd1 and laterally spaced along the first horizontal direction hd1 by the gate length GL. Includes side walls; The second pair of side walls includes a pair of side wall segments (eg, upper side wall segments of the proximal side wall 11P) laterally spaced along the first horizontal direction hd1 by the gate length GL.

In another embodiment, the field effect transistor 100A is a semiconductor active device including source regions 31 and 32, channel regions 36, and drain regions 38 and 39 arranged along the first horizontal direction hd1. Region 10A, gate dielectric 50 in contact with the top surface of channel region 36, gate electrodes 52, 54 having four sides overlying gate dielectric 50, gate electrode 52 on the four sides. , 54) laterally surrounding the dielectric gate spacer 56, and only on two sides of the gate electrodes 52, 54 extending in a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. and a dielectric offset spacer 55 located thereon. The gate dielectric spacer 56 is in physical contact with the dielectric offset spacer 55 across two sides of the gate electrodes 52 and 54 extending in the second horizontal direction hd2, and the gate dielectric spacer 56 is connected to the first horizontal direction hd2. 1 It is in physical contact with the other two sides of the gate electrodes 52 and 54 extending in the horizontal direction (hd1).

In the first previously described embodiment of the present disclosure, the gate strip is divided into gate stacks before forming dielectric gate spacers 56 and deep source/drain regions 32, 38. However, in a second embodiment of the present disclosure, the gate strip is divided into gate stacks after forming dielectric gate spacers 56 and deep source/drain regions 32, 38.

15A to 15D, a second exemplary structure according to the second embodiment of the present disclosure is a structure in which each of the gate strips 50, 52, and 54S is formed after performing the LDD ion implantation step shown in FIGS. 8A to 8D. , 58S) can be derived from the first example structure of FIGS. 8A-8D by forming dielectric gate spacers 56 around 58S). A layer of dielectric gate spacer material may be conformally deposited on dielectric offset spacers 55 located on the sidewalls of the gate strip, and an anisotropic etch process may be performed to remove horizontally extending portions of the dielectric gate spacer material layer. . The dielectric gate spacer material layer includes a dielectric material, such as silicon oxide and/or silicon nitride, and may be formed by at least one chemical vapor deposition process, such as at least one low pressure chemical vapor deposition (LPCVD) process. The remaining portion of the dielectric gate spacer material layer includes dielectric gate spacers 56 laterally surrounding each gate strip 50, 52, 54S, and 58S. In an illustrative example, each dielectric gate spacer 56 has a thickness of 5 nm to 100 nm, such as 10 nm to 50 nm, measured along the first horizontal direction hd1 over the transistor active area 10A between the inner and outer sidewalls. It can have a range of widths, but smaller and larger widths can also be employed.

In general, each of the gate strips 50, 52, 54S, and 58S may extend along a second horizontal direction hd2 across a plurality of semiconductor active regions (i.e., transistor active regions 10A), and may include a plurality of It may include a gate dielectric 50 and gate electrode strips 52 and 54S. The gate electrode strips 52 and 54S may include a plurality of semiconductor gate electrode portions 52 and a metal gate electrode strip 54S. Each dielectric gate spacer 56 laterally surrounds each gate strip 50, 52, 54S, and 58S and extends laterally along a second horizontal direction hd2 over the plurality of semiconductor active regions 10A. do. Each dielectric gate spacer 56 is formed directly over a plurality of source extension regions 31 arranged along a second horizontal direction hd2 and a plurality of drain extensions arranged along the second horizontal direction hd2. It may be formed directly over area 39.

16A-16D, the additional electrical dopant of the second conductivity type is unmasked by the combination of gate strips 50, 52, 54S, 58S, and dielectric gate spacers 56 in layer 10 of semiconductor material. may be injected into the unmasked portion of to form deep source/drain regions 32, 38. Deep source/drain regions 32 and 38 may include, for example, a deep source region 32 and a deep drain region 38. Typically, the atomic concentration of dopants in the deep source/drain regions (32, 38) is greater than the atomic concentration of dopants in the extended source/drain regions (31, 39). In this way, the volume of the source/drain extension regions 31, 39 that overlaps the volume of the deep source/drain regions 32, 38 is incorporated into each one of the deep source/drain regions 32, 38. In one embodiment, the atomic concentration of dopant in the deep source/drain regions 32, 38 may range from 5.0 × 10 ¹⁸ /cm ³ to 2.0 × 10 ²¹ /cm ³ , although lower or higher dopant concentrations may also be used. can be hired.

According to one aspect of the present disclosure, gate strips 50, 52, 54S, and 58S cover the entire gate-to-gate area of shallow trench isolation structure 20 located between adjacent pairs of transistor active regions 10A. Accordingly, no additional electrical dopant of the second conductivity type is implanted into the portion of transistor active area 10A proximate the transverse edge of the gate electrode to be subsequently patterned from gate strips 50, 52, 54S, 58S. Accordingly, the lateral spacing between neighboring pairs of semiconductor active regions 10A extends along the width of the gate electrode (i.e., in the gate fringe region) to be subsequently patterned from the gate strips 50, 52, 54S, 58S. The reduction can be achieved without incidental implantation of dopants of the second conductivity type in the peripheral portion of the semiconductor active region 10A proximate to the edge.

The unimplanted portion of each transistor active region 10A constitutes a channel region 36. Each channel area 36 may range from 1.0 x 10 ¹⁴ /cm ³ to 1 x 10 ¹⁸ /cm ³ , but lower and higher dopant concentrations may also be employed. Each of the source/drain extension regions 31, 39 and each of the deep source/drain regions 32, 38 each adjacent combination comprises a combination of the source extension regions 31 and the deep source regions 32. It constitutes a source/drain region, which may be a source region (31, 32) or a drain region (38, 39) comprising a combination of a drain extension region (39) and a deep drain region (38). In general, source regions 32, 32 and drain regions 38, 39 may be formed in a portion of each transistor active region 10A laterally spaced from each other by respective channel regions 36 in plan. there is.

17A to 17D, the photoresist layer 47 includes gate strips 50, 52, 54S, and 58S, a dielectric gate spacer 56, and a plurality of semiconductor active regions (i.e., transistor active region 10A). ) can be applied above. Photoresist layer 47 may be lithographically patterned to form openings 47A spanning portions of gate strips 50, 52, 54S, and 58S overlying the top surface of shallow trench isolation structure 20. The patterned photoresist layer 47 is arranged along the second horizontal direction hd2 and has at least one row of openings 47A (which may include a plurality of rows of openings) located within the region of the shallow trench isolation structure 20. ) includes. In one embodiment, each opening 47A in patterned photoresist layer 47 is positioned so long as it overlies each underlying gate strip 50, 52, 54S, 58S and each dielectric gate spacer 56. and a pair of first edges spanning a pair of second edges.

Typically, patterned photoresist layer 47 may cover the entire area of each transistor active area 10A that is not covered by gate strips 50, 52, 54S, 58S or dielectric gate spacer 56. . Patterned photoresist layer 47 includes rectangular openings 47A in areas where gate strips 50, 52, 54S, and 58S are subsequently cut. In other words, the area of openings 47A in patterned photoresist layer 47 corresponds to the area from which portions of gate strips 50, 52, 54S, and 58S are subsequently removed. In one embodiment, the patterned photoresist layer 47 is arranged along the second horizontal direction hd1 and located within and underlying the region of the shallow trench isolation structure 20, gate strips 50, 52, 54S, It includes a row of openings 47A with area overlap with each portion of 58S). In one embodiment, rows of rectangular openings 47A may be formed in patterned photoresist layer 47 over each gate strip 50, 52, 54S, 58S.

In one embodiment, each rectangular opening 47A of patterned photoresist layer 47 may have a first pair of straight sidewalls and a second pair of straight sidewalls. The first pair of straight sidewalls may extend laterally along a first horizontal direction hd1 and extend along the gate length GL of the underlying gate strips 50, 52, 54S, 58S (i.e., along the first horizontal direction hd1). It has a length greater than the lateral dimension along direction hd1). In one embodiment, a first pair of straight sidewalls may overlie each transistor active area 10A. That is, the area may overlap with each transistor active region 10A on a plane along a vertical direction perpendicular to the top surface of the semiconductor substrate 8. A pair of second sidewalls may extend laterally along a second horizontal direction hd2 and may overlie and contact the upper surface of each dielectric gate spacer 56 and an underlying gate strip 50, 52, 54S, 58S) and has no area overlap. A pair of second sidewalls of each opening 47A in patterned photoresist layer 47 may have area overlap with a peripheral area of an adjacent pair of transistor active regions 10A.

A top segment of gate cap dielectric 58 and two segments of an outer sidewall of dielectric gate spacer 56 may be physically exposed within the area of each opening 47A in patterned photoresist layer 47. . The width of each rectangular opening in the patterned photoresist layer 47 along the second horizontal direction hd2 is the lateral spacing between neighboring pairs of transistor active regions 10A along the second horizontal direction hd2. It may be larger than, and may be smaller than the lateral spacing between adjacent pairs of gate dielectrics 50 laterally spaced apart along the second horizontal direction hd2. Openings 47A in patterned photoresist layer 47 do not have any area overlap with gate dielectric 50. The length of each rectangular opening 47A in the photoresist layer 47 patterned along the first horizontal direction hd1 may be greater than the gate length of the underlying gate strips 50, 52, 54S, and 58S. , which is the width of the underlying gate strips 50, 52, 54S, 58S along the first horizontal direction hd1.

Referring to FIGS. 18A to 18D, an anisotropic etching process may be performed to etch the unmasked portions of the gate strips 50, 52, 54S, and 58S and the dielectric gate spacer 56. The pattern of rows of openings 47A in patterned photoresist layer 47 may be transferred through gate strips 50, 52, 54S, 58S and into unmasked areas of dielectric gate spacer 56. The unmasked portion of the offset spacer 55 may be vertically recessed during the anisotropic etch process. Shallow trench isolation structure 20 is masked by patterned photoresist layer 47 and is not etched during the anisotropic etch process.

The pattern of rows of openings in the patterned photoresist layer 47 may be transferred through the gate strips 50, 52, 54S, 58S and to the unmasked portion of the dielectric gate spacer 56 by an anisotropic etch process. there is. The unmasked portions of the gate strips (50, 52, 54S, 58S) are removed by an anisotropic etching process, and the remaining portions of the gate strips (50, 52, 54S, 58S) are formed into a plurality of gate stacks (50, 52, 54). , 58).

Each gate strip 50, 52, 54S, 58S can be divided into gate stacks 50, 52, 54, 58 by removing the unmasked portion of each gate strip 50, 52, 54S, 58S. there is. Each of the gate electrode strips 52 and 54S is laterally spaced apart along the second horizontal direction hd2 and each of the plurality of gate electrodes 52 lies on each semiconductor active region of the plurality of semiconductor active regions 10A. 54) can be divided into: Each gate stack 50, 52, 54, 58 includes a vertical stack of a gate dielectric 50, a semiconductor gate electrode portion 52, a metal gate electrode portion 54, and a gate cap dielectric 58. Each metal gate electrode portion 54 is a patterned portion of a respective metal gate electrode strip 54S. Each gate cap dielectric 58 is a patterned portion of a gate cap dielectric strip 58S. Each gate dielectric 50 is one of a plurality of gate dielectrics 50 within each of the gate strips 50, 52, 54S, and 58S. Each adjacent combination of semiconductor gate electrode portion 52 and metal gate electrode portion 54 constitutes gate electrodes 52 and 54. Accordingly, each of the gate electrodes 52 and 54 is a patterned portion of a respective gate electrode strip 52 and 54S.

Each of the gate stacks 50, 52, 54, and 58 is formed on each of the transistor active areas 10A. Each gate stack includes a gate dielectric 50 and gate electrodes 52 and 54.

In one embodiment, the anisotropic etch process etches the material of gate strips 50, 52, 54S, and 58S at a higher etch rate than the material of dielectric gate spacers 56. A pair of stepped sidewalls may be formed on each dielectric gate spacer 56 beneath each opening in the patterned photoresist layer 47 .

In one embodiment, each dielectric gate spacer 56 includes an over-active area gate spacer portion 56A overlying semiconductor active area 10A, as shown in FIG. 18C. The active-region-above gate spacer portion 56A includes straight inner sidewalls perpendicular to the first horizontal direction hd1 and laterally spaced apart by a first spacing S1, which is the gate spacer inner sidewall spacing, i.e., the dielectric Also referred to as the gap between a pair of inner side walls of gate spacer 56. In one embodiment, each dielectric gate spacer 56 also includes an inter-active region gate spacer portion 56B that overlies a portion of shallow trench isolation structure 20, as shown in FIG. 18D. The inter-active-area gate spacer portion 56B has a lower straight sidewall segment 56L adjacent to and located in the same vertical plane as each pair of straight inner sidewalls of a neighboring over-area gate spacer portion 56A. ), an upper straight sidewall segment 56U laterally offset from the lower straight sidewall segment, and a stepped sidewall comprising a connecting horizontal surface 56H adjacent the upper edge of the lower straight sidewall segment and the lower edge of the upper straight sidewall segment. Includes. The pair of upper straight sidewall segments 56U of the two active-region inter-gate spacer portions 56B located within the same opening 47A in the patterned photoresist layer 47 are herein referred to as gate spacer upper inner sidewall segments. They may be laterally spaced from each other by a second gap S2', referred to as the gap. The lateral distance between the outer sidewalls of each dielectric gate spacer 56 along the first horizontal direction hd1 may be uniform, with a third spacing S3, also referred to herein as the gate spacer outer sidewall spacing. It is referred to. The second gap S2' may be smaller than the third gap S3.

In one embodiment, the shallow trench isolation structure 20 has a planar top surface located in a horizontal plane and at least in an area covered by a patterned photoresist layer 47 or by a dielectric gate spacer 56. You can. The lower straight sidewall segment 56L of the inter-active region gate spacer portion 56B may contact the planar top surface of the shallow trench isolation structure 20. In one embodiment, each of the upper straight sidewall segments 56U of the inter-active area gate spacer portion 56B is each of the concave outer sidewalls of the inter-active area gate spacer portion 56B of the dielectric gate spacer 56. has each upper edge adjacent to the upper edge of the segment.

In one embodiment, shallow trench isolation structure 20 includes an inter-gate region located between neighboring pairs of semiconductor active regions 10A and within a region surrounded by the outer periphery of each dielectric gate spacer 56. A pair of active-region inter-gate spacer portions 56B overlies each inter-gate region. In one embodiment, upper straight sidewall segments 56U of a pair of inter-active region gate spacer portions 56B have a first horizontal offset by a gate spacer upper inner sidewall segment spacing (equal to second spacing S2'). They are laterally spaced apart from each other along the direction hd1. The lower straight sidewall segment 56L of the pair of active-region inter-gate spacer portions 56B has a first gate spacer inner sidewall spacing (equal to first spacing S1) that is less than the gate spacer upper inner sidewall segment spacing. They are laterally spaced apart from each other along the horizontal direction. In embodiments where offset spacers 55 are omitted, the gate spacer inner sidewall spacing (such as first spacing S1) may be equal to the gate length. In one embodiment, a pair of straight inner sidewalls of each active-region-above gate spacer portion 56A is laterally along a first horizontal direction by a gate spacer inner sidewall spacing (e.g., first spacing S1). can be separated from

19A-19E, patterned photoresist layer 47 may be removed, for example, by ashing. In one embodiment, the straight inner sidewall of the active-region over-gate spacer portion 56A extends at least the gate electrodes 52 and 54 from the first horizontal plane HP1 including the lower surface of the gate electrodes 52 and 54. It extends to a second horizontal surface (HP2) including the upper surface. The entire connecting surface of the active-area-above gate spacer portion 56A is located above the first horizontal plane HP1 and below the second horizontal plane HP2. In one embodiment, the straight inner sidewalls of the over-active region gate spacer portion 56A contact the top surfaces of the source regions 31 and 32 and drain regions 38 and 39.

20A-20D, at least one layer of dielectric material 62, 64, 80 can be deposited over the second example structure. In one embodiment, the at least one layer of dielectric material (62, 64, 80) comprises at least one conformal dielectric liner (62, 64) and a contact level dielectric layer overlying the at least one conformal dielectric liner (62, 64). It contains a vertical stack containing (80). At least one dielectric liner (62, 64) each has a gate stack (50, 52, 54, 58), a dielectric gate spacer (56), a source region (31, 32), and a drain by at least one conformal deposition process. It may be deposited on the physically exposed surfaces of areas 38 and 39. The at least one dielectric liner 62, 64 may include, for example, a stack of a silicon oxide liner 62 and a silicon nitride liner 64. Contact level dielectric layer 80 includes gate stacks 50, 52, 54, 58, source/drain regions {(31, 32), (38, 39)}, shallow trench isolation structures 20, and optionally at least It can be deposited over one dielectric liner (62, 64). Contact level dielectric layer 80 includes a dielectric material, such as silicon oxide. A planarization process, such as a chemical mechanical planarization process, may optionally be performed to planarize the top surface of the contact level dielectric layer 80. The vertical distance between the top surface of the contact level dielectric layer 80 and the top surface of the gate cap dielectric 58 may range from 50 nm to 500 nm, although smaller and larger vertical distances may also be employed. Contact via structures 82, 85, 88 are then formed through contact level dielectric layer 80 as described above.

1A to 8D and 15A to 20D and according to a second embodiment of the present disclosure, the semiconductor structure includes a first field effect transistor 200A and a second field effect transistor 200B and shallow trench isolation. Includes structure (20). Each of the first and second field effect transistors 200A and 200B includes a source region 31 and 32, a channel region 36 and a drain region 38 and 39 arranged along the first horizontal direction hd1. a semiconductor active region 10A, a gate dielectric 50 in contact with the top surface of the channel region 36, gate electrodes 52, 54 overlying the gate dielectric 50, and opposite sides of the gate electrodes 52, 54. It includes a pair of dielectric gate spacers 56 located at . The shallow trench isolation 20 structure laterally surrounds each of the semiconductor active regions 10A of the first and second two field effect transistors 200A and 200B. Each of the pair of dielectric gate spacers (56) has an over-active-area gate spacer portion (56A) overlying the semiconductor active region (10A) and including straight inner sidewalls perpendicular to the first horizontal direction (hd1); and an active-region inter-gate space portion 56B overlying a portion of the shallow trench isolation structure 20 and including stepped sidewalls, the stepped sidewalls having a lower straight edge adjacent each pair of straight inner sidewalls. sidewall segment 56L, and an upper straight sidewall segment 56U laterally offset from lower straight sidewall segment 56L, and an upper edge of lower straight sidewall segment 56L and a lower edge of upper straight sidewall segment 56U. and a connecting surface 56H adjacent thereto.

In one embodiment, the straight inner sidewall extends from a first horizontal plane (HP1) comprising at least the lower surfaces of the gate electrodes (52, 54) and a second horizontal plane (HP2) comprising at least the upper surfaces of the gate electrodes (52, 54). It is extended. In one embodiment, the entirety of connecting surface 56H is located above first horizontal surface HP1 and below second horizontal surface HP2. In one embodiment, the straight inner sidewall contacts the top surfaces of source regions 31 and 32 and drain regions 38 and 39.

In one embodiment, shallow trench isolation structure 20 has a planar top surface located in a horizontal plane and in areas not covered by gate electrodes 52, 54; Lower straight sidewall segment 56L contacts the planar top surface of shallow trench isolation structure 20.

In one embodiment, each straight inner sidewall has a respective top edge adjacent the top edge of a respective segment of the concave outer sidewall of the dielectric gate spacer 56; Each upper straight sidewall segment 56U has a respective upper edge adjacent the upper edge of each additional segment of the concave outer sidewall of the dielectric gate spacer 56.

In one embodiment, shallow trench isolation structure 20 includes an inter-gate region located between adjacent pairs of semiconductor active regions 10A and within a region surrounded by an outer periphery of dielectric gate spacer 56; A pair of active-region inter-gate spacer portions 56B overlies each inter-gate region.

In one embodiment, upper straight sidewall segments 56U of a pair of inter-active region gate spacer portions 56B have a first horizontal offset by a gate spacer upper inner sidewall segment spacing (equal to second spacing S2'). laterally spaced apart from each other along direction hd1; The lower straight sidewall segment 56L of the pair of active-region inter-gate spacer portions 56B has a first gate spacer inner sidewall spacing (equal to first spacing S1) that is less than the gate spacer upper inner sidewall segment spacing. They are laterally spaced apart from each other along the horizontal direction (hd1). In one embodiment, a pair of straight inner sidewalls of each active-region-over-gate spacer portion 56A are laterally spaced along the first horizontal direction hd1 by a gate spacer inner sidewall spacing.

In one embodiment, the semiconductor structure includes at least one layer of dielectric material (62, 64, 80) overlying gate electrodes (52, 54) and dielectric gate spacers (56), each of gate electrodes (52, 54) and each width-wise sidewall parallel to the first horizontal direction hd1 and in direct contact with at least one layer of dielectric material 62, 64, 80 (eg, silicon oxide liner 62). In one embodiment, at least one of the gate electrodes 52, 54 has a pair of widths that contact a respective sidewall of at least one dielectric material layer 62, 64, 80 (e.g., silicon oxide liner 62). Includes directional side walls.

In one embodiment, the at least one layer of dielectric material (62, 64, 80) comprises at least one conformal dielectric liner (62, 64) and a contact level dielectric layer overlying the at least one conformal dielectric liner (62, 64). (80) comprising a vertical stack comprising; At least one conformal dielectric liner (62, 64) of the source regions (31, 32), drain regions (38, 39), shallow trench isolation structure (20), and active-region inter-gate spacer portion (56B). It contacts the upper surface of each stepped side wall. In one embodiment, the at least one conformal dielectric liner 62, 64 has an upper edge of a straight inner sidewall of the above-active-area gate spacer portion 56A and a step of the inter-active-area gate spacer portion 56B. It contacts the entire concave outer sidewall of the dielectric gate spacer 56 adjacent the upper edge of the mold sidewall.

In one embodiment, each of the gate electrodes 52 and 54 includes a semiconductor gate electrode portion 52 that contacts the top surface of the respective gate dielectric; and a metal gate electrode portion 54 overlying the semiconductor gate electrode portion 52 and having a first length along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The semiconductor gate electrode portion 52 includes an upper region having a first length and a lower region having a second length along a second horizontal direction hd2 that is greater than the first length. The first length of the metal gate electrode portion along the second horizontal direction hd2 is smaller than the length of the active area 10A in the second horizontal direction hd2, so that the metal gate extends along the first horizontal direction hd1. The electrode portion 54 has its edge positioned over the active area 10A.

In one embodiment, the semiconductor gate electrode portion 52 includes: an upper widthwise sidewall extending laterally along the first horizontal direction hd1 and vertically coincident with the widthwise sidewall of the metal gate electrode portion 54; a lower transverse sidewall extending laterally along a second horizontal direction hd2 and contacting a sidewall segment of the shallow trench isolation structure 20; and a horizontal plane segment connecting the upper edge of each of the lower transverse side walls to the lower edge of each of the upper transverse side walls.

Using various embodiments of the present disclosure, rows of field effect transistors, such as a two-dimensional array of field effect transistors, can be arranged along the longitudinal direction of the gate electrodes 52 and 54, i.e., between the source region and the source region within each field effect transistor. It can be scaled along a direction perpendicular to the direction of current flow in the channel region between the drain regions. Specifically, at least the LDD ion implantation process may be performed before dividing the gate strips 50, 52, 54S, and 58S into gate electrodes, thereby forming the width direction of the gate electrodes 52 and 54 to be subsequently patterned. Incidental injection of electrical dopants close to the edge can be prevented. This reduces or eliminates leakage current paths in the gate fringe area.

Referring to FIGS. 21A and 21B , the third exemplary structure according to the third embodiment of the present disclosure may be the same as the first exemplary structure shown in FIGS. 5A and 5B. In this third embodiment, the semiconductor gate electrode material layer 52L is hereinafter referred to as the first semiconductor gate electrode material layer 52L. Generally, shallow trench isolation structure 20 may be formed in an upper region of semiconductor substrate 8 having a first conductivity type of doping. Shallow trench isolation structure 20 laterally surrounds a plurality of semiconductor active regions that are patterned portions of semiconductor substrate 8 .

Referring to FIGS. 22A and 22B , the second semiconductor gate electrode material layer 53L may be formed on the first semiconductor gate electrode material layer 52L. The second semiconductor gate electrode material layer 53L includes a doped semiconductor material, such as doped polysilicon or doped amorphous silicon. The second semiconductor gate electrode material layer 53L has the same conductivity type of doping as the first semiconductor gate electrode material layer 52L and may include or include the same semiconductor material as the first semiconductor gate electrode material layer 52L. You may not. In one embodiment, the second semiconductor gate electrode material layer 53L may be deposited by chemical vapor deposition (CVD). The thickness of the second semiconductor gate electrode material layer 53L may range from 30 nm to 300 nm, although smaller and larger thicknesses may also be employed.

23A-23D, a photoresist layer (not shown) may be applied over the second semiconductor gate electrode material layer 53L and patterned into discrete photoresist material portions by lithographic exposure and development. . Each patterned portion of photoresist material can have the shape of a respective gate strip to be subsequently formed. In one embodiment, the transistor active area 10A may be arranged in at least one row of transistor active areas 10A arranged along the second horizontal direction hd2. In one embodiment, the transistor active area 10A may be arranged in multiple rows of transistor active areas 10A arranged along the second horizontal direction hd2. In this case, the illustrated portion of the first exemplary structure as shown in FIGS. 23A to 23D corresponds to two neighboring transistor active regions 10A arranged along the second horizontal direction hd2. In one embodiment, transistor active area 10A may be arranged as a two-dimensional periodic array, such as a two-dimensional periodic rectangular array.

Each portion of patterned photoresist material may have a respective rectangular horizontal cross-sectional shape with each pair of longitudinal sidewalls along the second horizontal direction hd2. In one embodiment, each patterned photoresist material portion is positioned in a second horizontal direction over a plurality of transistor active areas 10A, such as rows of transistor active areas 10A arranged along the second horizontal direction hd2. It may extend laterally along direction hd2.

An anisotropic etching process may be performed to transfer the pattern of the patterned photoresist material portion through the second semiconductor gate electrode material layer 53L, the first semiconductor gate electrode material layer 52L, and the gate dielectric layer 50L. . Unmasked areas of shallow trench isolation structure 20 may be incidentally recessed during the anisotropic etch process.

Gate strips 50, 52, and 53S may be formed on each row of the transistor active area 10A arranged along the second horizontal direction hd2. Each gate strip 50, 52, 53S includes a patterned portion of a second semiconductor gate electrode material layer 53L, a first semiconductor gate electrode material layer 52L, and a gate dielectric layer 50L. For example, each of the gate strips 50, 52, and 53S includes a plurality of gate dielectrics 50 that are patterned portions of the gate dielectric layer 50L and a patterned portion of the first semiconductor gate electrode material layer 52L. It includes a plurality of lower semiconductor gate electrode sub-portions 52 that are a portion, and a second semiconductor gate electrode strip 53S that is a patterned portion of the second semiconductor gate electrode material layer 53L. An adjacent combination of a plurality of lower semiconductor gate electrode sub-portions 52 and metal gate electrode strips 53A constitute gate electrode strips 52 and 53S. Gate electrode strips 52, 53S extend continuously as a single continuous structure over each transistor active region 10A within a row of transistor active regions 10A. Each gate electrode strip 52, 53S includes a pair of longitudinal side walls extending laterally along the second horizontal direction hd2 and laterally spaced apart along the first horizontal direction by the gate length GL. can do. In one embodiment, each gate electrode strip 52, 53S has a lower semiconductor gate extending laterally along the first horizontal direction hd1 and contacting a respective sidewall surface segment of shallow trench isolation structure 20. Electrode sub-portion 52 may include a plurality of surface segments, such as sidewalls.

24A to 24D, offset spacers 55 may be selectively formed on the sidewalls of the gate strips 50, 52, and 53S. Offset spacers 55 may be formed by conformal deposition of a thin dielectric liner and an anisotropic etch process that removes horizontally extending portions of the thin dielectric liner and/or physically exposed surfaces of the lower semiconductor gate electrode subportion 52. It can be formed by surface oxidation of. The lateral thickness of offset spacer 55, if present, may range from 0.3 nm to 20 nm, such as 1 nm to 6 nm, although smaller and larger thicknesses may also be employed. Offset spacer 55 may include silicon oxide, silicon nitride, or a silicon oxide/silicon nitride double layer.

An electrical dopant of a second conductivity type may be implanted into the unmasked portion of the semiconductor material layer 10 that is not masked by the gate strips 50, 52, 53S to form source/drain extension regions 31, 39. You can. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The source/drain extension regions 31 and 39 may include, for example, a source extension region 31 and a drain extension region 39 . Typically, each of the source/drain extensions 31, 39 is doped with an opposite conductivity type than the conductivity type of the remainder of the transistor active region 10A from which each of the source/drain extensions 31, 39 is formed. You can have it. For example, if transistor active area 10A has a doping of a first conductivity type, source/drain extension regions 31, 39 formed within the surface area of transistor active area 10A have a doping opposite to the first conductivity type. It has a second conductivity type of doping. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant atomic concentration of the source/drain region 31 may range from 1.0 x 10 ¹⁸ /cm ³ to 1.0 x 10 ²⁰ /cm ³ , although lower or higher dopant concentrations may also be used. Accordingly, extension regions (i.e., lDD regions) 31 and 39 are implanted before separating the gate strips 50, 52, and 53S into gate electrodes. The gate strip blocks the LDD implant process from doping the edge region of the transistor active region 10A below the gate strip in the gate fringe region. Avoiding doping the gate fringe region at the edge of each transistor active region 10A doping prevents or reduces leakage current paths through the gate fringe region and reduces transistor leakage current.

25A-25D, a photoresist layer 47 can be applied over the first example structure and lithographically patterned to form gate strips 50, 52 overlying the top surface of the shallow trench isolation structure 20. An opening 47A spanning a portion of 53S) can be formed. Typically, the patterned photoresist layer 47 can cover the entire area of each transistor active region 10A, with gate strips 50, 52, and 53S subsequently cut into the area (i.e., the transistor active region 10A). (gate fringe area between 10A) may include a rectangular opening 47A. In other words, the area of the openings 47A of the patterned photoresist layer 47 corresponds to the gate fringe area from which portions of the gate strips 50, 52, and 53S are subsequently removed. In one embodiment, the patterned photoresist layer is arranged along the second horizontal direction hd2 and overlying the shallow trench isolation structure 20 and in each of the underlying gate strips 50, 52, and 53S. It includes a row of openings 47A with area overlap with the portion. In one embodiment, a row of rectangular openings 47A may be formed in the patterned photoresist layer 47 over each gate strip 50, 52, 53S.

In one embodiment, each rectangular opening 47A of patterned photoresist layer 47 may have a first pair of straight sidewalls and a second pair of straight sidewalls. The first pair of straight side walls may extend laterally along a first horizontal direction (hd1) and extend along the gate length (GL) of the underlying gate strips (50, 52, 53S) (i.e., in the first horizontal direction ( It has a length greater than the lateral dimension along hd1). As shown in FIG. 9D , the second pair of sidewalls may extend laterally along a second horizontal direction hd2 and may overlie and contact respective portions of shallow trench isolation structure 20 . Accordingly, the second sidewall has no area overlap with the underlying gate strips 50, 52, 53S. The second pair of sidewalls of each opening 47A in patterned photoresist layer 47 also does not have any area overlap with any of the transistor active regions 10A.

A top portion of shallow trench isolation structure 20 is exposed within opening 47A. Specifically, a pair of rectangular top segments of shallow trench isolation structure 20 may be physically exposed within the area of each opening 47A in patterned photoresist layer 47. Additionally, a rectangular surface segment of the upper surface of the second semiconductor gate electrode strip 53S may be physically exposed within the area of each opening 47A in the patterned photoresist layer 47. The width of each rectangular opening 47A of the patterned photoresist layer 47 along the second horizontal direction hd2 is the width between neighboring pairs of transistor active regions 10A along the second horizontal direction hd2. It may be smaller than the lateral spacing. The length of each rectangular opening 47A in the patterned photoresist layer 47 along the first horizontal direction hd1 may be greater than the gate length GL of the underlying gate strips 50, 52, and 53S. There is, which is the width of the gate strips 50, 52, and 53S placed below along the first horizontal direction (hd1).

An anisotropic etching process may be performed to etch the unmasked portion of each gate strip 50, 52, and 53S. The etching process is performed after implantation of the extended regions (i.e., lDD regions) 31 and 39 into the transistor active region 10A. The row pattern of openings 47A in patterned photoresist layer 47 may be transferred through gate strips 50, 52, 53S and into unmasked areas of shallow trench isolation structure 20. The unmasked portion of the offset spacer 55 may be incidentally removed during the anisotropic etching process. The unmasked portion of shallow trench isolation structure 20 may be vertically recessed to form via cavity 11 . A pair of via cavities 11 extending vertically into shallow trench isolation structure 20 may be formed within each opening within a row of openings in patterned photoresist layer 47 .

Each of the gate strips 50, 52, and 53S is separated from the gate stack 50, 52, and 53 by removing a portion of each gate strip 50, 52, and 53S located within the gate fringe region overlying the shallow trench isolation structure 20. ) can be divided into Each gate stack 50, 52, 53 includes a vertical stack of a gate dielectric 50, a lower semiconductor gate electrode sub-portion 52, and an upper semiconductor gate electrode sub-portion 53. Each upper semiconductor gate electrode subportion 53 is a patterned portion of each second semiconductor gate electrode strip 53S. Each gate dielectric 50 is one of a plurality of gate dielectrics 50 within each gate strip 50, 52, and 53S. Each successive combination of the lower semiconductor gate electrode lower portion 52 and the upper semiconductor gate electrode lower portion 53 constitutes a semiconductor gate electrode portion, which is the gate electrodes 52 and 53. Accordingly, each of the gate electrodes 52 and 53 is a patterned portion of a respective gate electrode strip 52 and 53S.

Each gate stack 50, 52, and 53 is formed on each of the transistor active areas 10A. Each gate stack includes a gate dielectric 50 and gate electrodes 52 and 53. In one embodiment, each of gate stacks 50, 52, and 53 includes a pair of peripheral regions (PR) located within a gate fringe region, shallow in plan view along a vertical direction perpendicular to the top surface of semiconductor substrate 8. It has area overlap with the trench isolation structure 20.

A pair of via cavities 11 may be formed under each opening 47A in the patterned photoresist layer 47. The pair of via cavities 11 includes a pair of proximal side walls 11P laterally spaced along the first horizontal direction hd1 by a first spacing S1, which is the gate spacer inner side wall spacing; That is, it is also referred to as the gap between a pair of inner sidewalls of a gate spacer to be formed subsequently. In one embodiment, the pair of via cavities 11 have a pair of distal sidewalls laterally spaced along the first horizontal direction hd1 by a second spacing S2, also referred to as the trench distal sidewall spacing. Includes (11D).

Each region of shallow trench isolation structure 20 located within a region located between adjacent pairs of gate dielectrics 50 is referred to herein as an inter-gate region. Each inter-gate region of the shallow trench isolation structure 20 has a respective bottom surface segment of an adjacent pair of gate electrodes 52, 53, such as an adjacent pair of bottom surface segments of the top semiconductor gate electrode portion 53. It includes a pair of uppermost horizontal plane segments (THSS) of shallow trench isolation structure 20 in contact. Additionally, each inter-gate region of shallow trench isolation structure 20 is adjacent to the uppermost horizontal plane segment by a pair of vertical plane segments and includes an intermediate horizontal plane segment (IHSS) located between each pair of via cavities 11. . The middle horizontal plane segment is physically exposed beneath the opening 47A of the patterned photoresist layer 47.

In one embodiment, the intermediate horizontal plane segment (IHSS) is located above a horizontal plane comprising a planar top surface of the shallow trench isolation structure 20 covered by a patterned photoresist layer 47. In one embodiment, the bottom surface of via cavity 11 is located below a horizontal plane comprising the planar top surface of shallow trench isolation structure 20 covered by patterned photoresist layer 47.

In one embodiment, each via cavity 11 includes a pair of stepped proximal side walls with each horizontal step located between an upper vertical proximal side wall segment and a lower vertical proximal side wall segment. The pair of lower vertical proximal side wall segments may be laterally spaced from each other by a first spacing S1. The pair of upper vertical proximal sidewall segments may be laterally spaced from each other by a gate length (GL).

In one embodiment, each via cavity 11 has a pair of first sidewalls 111 parallel to the first horizontal direction hd1 and vertically coincident with the widthwise sidewalls of neighboring pairs of gate electrodes 52 and 53. ), and a pair of second side walls (e.g., the proximal side wall 11P and the distal side wall 11D) perpendicular to the first horizontal direction hd1 and adjacent to the vertically extending edges of the pair of first side walls 111. Includes. In one embodiment, each gate electrode 52, 53 has a pair of longitudinal electrodes perpendicular to the first horizontal direction hd1 and laterally spaced along the first horizontal direction hd1 by the gate length GL. Includes side walls. In one embodiment, the pair of second side walls 11P of each via cavity 11 includes a pair of side wall segments (stepped side walls) laterally spaced apart along the first horizontal direction by the gate length GL. 11P), which is the upper straight side wall segment).

In one embodiment, each gate electrode 52, 53 is laterally spaced along the first horizontal direction hd1 by a gate length GL and extends laterally along the second horizontal direction hd2. It includes a pair of longitudinal side walls. The lateral spacing between a pair of horizontal steps 11H of a pair of stepped proximal side walls 11P across each inter-gate region of the shallow trench isolation structure 20 is equal to the gate length GL.

In one embodiment, gate electrodes 52, 53 each have a lower semiconductor gate electrode lower portion 52 in contact with the upper surface of each gate dielectric 50, and an upper semiconductor gate electrode overlying lower semiconductor gate electrode lower portion 52. It includes an electrode sub-portion (53). In one embodiment, the lower semiconductor gate electrode subportion 52 contacts the sidewalls of a pair of gate-to-gate regions of shallow trench isolation structure 20. In one embodiment, the semiconductor gate electrode portion includes a top surface located in the same horizontal plane as a topmost segment of a region between a pair of gates of shallow trench isolation structure 20. In one embodiment, the upper semiconductor gate electrode lower portion 53 contacts the uppermost segment of the region between the pair of gates of the shallow trench isolation structure 20.

In one embodiment, the longitudinal sidewall of the upper semiconductor gate electrode subportion 53 perpendicular to the first horizontal direction hd1 is the length of the lower semiconductor gate electrode subportion 52 in each of the gate electrodes 52 and 53. Orientation coincides perpendicularly with the side wall. The widthwise sidewall of the upper semiconductor gate electrode lower portion 53 parallel to the first horizontal direction hd1 extends outward from the widthwise sidewall of the lower semiconductor gate electrode lower portion 52 in each of the gate electrodes 52 and 53. Laterally offset.

Typically, each gate strip 50, 52, 53S is positioned in the interelectrode region of the shallow trench isolation structure 20 after forming the source/drain extension regions 31, 39 and before forming the deep source/drain region. (20I) can be divided into gate stacks 50, 52, and 53 by removing portions of the gate strips 50, 52, and 53S overlying.

26A-26D, patterned photoresist layer 47 may be removed, for example, by ashing. The dielectric gate spacer material layer may be deposited conformally, and an anisotropic etch process may be performed to remove horizontally extending portions of the dielectric gate spacer material layer. The dielectric gate spacer material layer includes a dielectric material, such as silicon oxide and/or silicon nitride, and may be formed by at least one chemical vapor deposition process, such as at least one low pressure chemical vapor deposition (LPCVD) process. The remaining portion of the dielectric gate spacer material layer includes dielectric gate spacers 56 laterally surrounding each of gate stacks 50, 52, and 53. In an illustrative example, each dielectric gate spacer 56 has a thickness of 5 nm to 100 nm, such as 10 nm to 50 nm, measured along the first horizontal direction hd1 over transistor active area 10A between the inner and outer sidewalls. It can have a range of widths, but smaller and larger widths can also be employed.

According to one aspect of the present disclosure, the thickness of the dielectric gate spacer material layer is one-half the spacing between neighboring pairs of laterally spaced gate stacks 50, 52, 53 along the second horizontal direction hd2. It can be bigger than For example, the thickness of the dielectric gate spacer material layer may be less than one-half the width of each opening 47A in patterned photoresist layer 47, as employed in the processing steps of FIGS. 25A-25D. It can be big. In this case, the vertical growth surfaces of the dielectric gate spacer material layers merge to form a seam between each neighboring pair (50, 52, 53) of laterally spaced gate stacks along the second horizontal direction (hd2). do. After an anisotropic etching process to form the dielectric gate spacers 56, neighboring pairs of dielectric gate spacers 56 arranged along the second horizontal direction hd2 are positioned midway between neighboring pairs of dielectric gate spacers 56. are positioned and contact each other in a vertical plane extending along the first horizontal direction (hd2). All gate-to-gate regions of shallow trench isolation structure 20 may be covered by dielectric gate spacers 56.

In general, each neighboring pair of dielectric gate spacers 56 laterally spaced along the second horizontal direction hd1 may contact each other along a respective vertical plane parallel to the first horizontal direction hd1. . In one embodiment, the outer widthwise sidewalls of neighboring pairs of dielectric gate spacers 56 have vertical vertical extensions extending laterally along a first horizontal direction hd1 above each inter-gate region of shallow trench isolation structure 20. They come into contact with each other in the meeting.

Each via cavity 11 may be filled by a downwardly protruding portion of each pair of dielectric gate spacers 56 . Each neighboring pair of dielectric gate spacers 56 arranged along the second horizontal direction hd2 has a pair of via cavities 11 filled with the downwardly protruding portions of each neighboring pair of dielectric gate spacers 56. ) may be in contact with each other across the respective inter-gate regions of the shallow trench isolation structure 20, including.

In one embodiment, each dielectric gate spacer 56 is directed toward a respective gate electrode 52, 53 and extends laterally along a second horizontal direction hd2 by a first spacing S1, That is, it includes a pair of inner longitudinal side walls that are laterally spaced apart along the first horizontal direction hd1 by the distance between the inner side walls of the gate spacer 55. In one embodiment, each dielectric gate spacer 56 faces away from each gate electrode 52, 53 and extends laterally along a second horizontal direction hd2, herein outside the gate spacer. It comprises a pair of outer longitudinal side walls, laterally spaced apart by a third spacing S3, referred to as the side wall spacing. In one embodiment, third spacing S3 (i.e., gate spacer outer sidewall spacing) may be greater than second spacing S2 (i.e., trench distal sidewall spacing).

In one embodiment, each gate-to-gate region of the shallow trench isolation structure is adjacent a respective topmost segment of the gate-to-gate region of the shallow trench isolation structure 20 and is contacted by a respective sidewall of the dielectric gate spacer 56. , comprising a pair of side wall segments extending laterally along the first horizontal direction hd1. In one embodiment, dielectric gate spacer 56 may include four downwardly protruding portions extending vertically into four via cavities 11 within shallow trench isolation structure 20 . In one embodiment, shallow trench isolation structure 20 may have a planar top surface located in a horizontal plane and in an area not covered by gate electrodes 52, 53 or by dielectric gate spacer 56.

Accordingly, the dielectric offset spacer 55 is formed only on two sides of each of the gate electrodes 52 and 53 extending in the second horizontal direction hd2 and the gate electrode 52 extending in the vertical first horizontal direction hd1. 53) Absent on each of the other two sides. In contrast, gate dielectric spacer 56 laterally surrounds each of gate electrodes 52 and 53 on all four sides. Accordingly, the gate dielectric spacer 56 is in physical contact with the dielectric offset spacer 55 located on two sides of each of the gate electrodes 52 and 53 extending in the second horizontal direction hd2, and the gate dielectric spacer ( 56) is in physical contact with the other two sides of each of the gate electrodes 52 and 53 extending in the first horizontal direction hd1.

27A-27D, additional electrical dopants of the second conductivity type are present in the gate stacks 50, 52, 53, and in the unmasked portion of the semiconductor material layer 10 that is not masked by the dielectric gate spacer 56. It may be implanted within the portion to form deep source/drain regions 32, 38.

According to one aspect of the present disclosure, the gap between neighboring pairs of gate electrodes 52 and 53 laterally spaced apart along the second horizontal direction hd2 is filled with a pair of dielectric gate spacers 56. Accordingly, no additional electrical dopant of the second conductivity type is implanted into the portion of the transistor active region 10A proximate to the width edge of the upper semiconductor gate electrode lower portion 53 parallel to the first horizontal direction hd1. This characteristic concerns the concomitant implantation of dopants of the second conductivity type within the peripheral portion of the semiconductor active region 10A proximate to the width edge of the upper semiconductor gate electrode lower portion 53 parallel to the first horizontal direction hd1. This enables reduction of the lateral spacing between neighboring pairs of semiconductor active regions 10A.

Deep source/drain regions 32 and 38 may include, for example, a deep source region 32 and a deep drain region 38. Typically, the atomic concentration of dopants in the deep source/drain regions (32, 38) is greater than the atomic concentration of dopants in the extended source/drain regions (31, 39). In this way, the volume of the source/drain extension regions 31, 39 that overlaps the volume of the deep source/drain regions 32, 38 is incorporated into each one of the deep source/drain regions 32, 38. In one embodiment, the atomic concentration of dopant in the deep source/drain regions 32, 38 may range from 5.0 × 10 ¹⁸ /cm ³ to 2.0 × 10 ²¹ /cm ³ , although lower or higher dopant concentrations may also be used. can be hired.

The unimplanted portion of each transistor active region 10A constitutes a channel region 36. Each channel region 36 may have an atomic concentration of a dopant of the first conductivity type ranging from 1.0 x 10 ¹⁴ /cm ³ to 1.0 x 10 ¹⁸ /cm ³ , although smaller and larger dopant concentrations may also be employed. . Each of the source/drain extension regions 31, 39 and each of the deep source/drain regions 32, 38 each adjacent combination comprises a combination of the source extension regions 31 and the deep source regions 32. It constitutes a source/drain region, which may be a source region (31, 32) or a drain region (38, 39) comprising a combination of a drain extension region (39) and a deep drain region (38). In general, source regions 32, 32 and drain regions 38, 39 may be formed in portions of each transistor active region 10A laterally spaced from each other by respective channel regions 36.

Typically, the plurality of transistor active regions 10A may have a doping of a first conductivity type, and the source extension region 31 and drain extension region 39 may have a dopant of a second conductivity type opposite the first conductivity type. The deep source/drain regions 32, 38 may be formed in the upper portion of the plurality of transistor active regions 10A by implanting an additional dopant of the second conductivity type into the interelectrode region of the shallow trench isolation structure 20. It may be formed by implanting additional dopants of a second conductivity type into the plurality of semiconductor active regions 10A without implanting into 20I. In one embodiment, dielectric gate spacer 56 prevents implantation of additional dopants of the second conductivity type into interelectrode region 20I of shallow trench isolation structure 20.

A metal layer may be deposited over the third example structure. The metal layer includes and/or consists essentially of a metal that forms a silicide with the semiconductor (e.g., silicon) material of the transistor active region 10A and the upper semiconductor gate electrode subportion 53. For example, the semiconductor material of transistor active region 10A and upper semiconductor gate electrode subportion 53 may include amorphous silicon, polysilicon, or a silicon-germanium alloy, and the metal layer may include tungsten, titanium, tantalum, It may comprise and/or consist essentially of a metal that forms a silicide, such as at least one metal selected from cobalt, molybdenum, platinum, and/or nickel. The metal layer may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the horizontally extending portion of the metal layer may range from 6 nm to 60 nm, such as 12 nm to 30 nm, although smaller and larger thicknesses may also be employed.

A thermal or flash lamp annealing process can be performed to induce a reaction between the metal layer and the underlying semiconductor material portion to form a metal silicide region using a silicide process. The surface portion of the upper semiconductor gate electrode lower portion 53 (which is the surface portion of the semiconductor gate electrode portions 52 and 53) is converted into a gate silicide region 59 by reacting with the metal. The surface portions of the deep source/drain regions (32, 38) are converted into source/drain silicide regions (33, 37) by reacting with the metal. The unreacted portion of the metal layer may be removed selectively to the silicide material of the gate silicide region 59 and source/drain silicide regions 33, 37. The silicide materials of gate silicide region 59 and source/drain silicide regions 33, 37, respectively, may have a thickness ranging from 2 nm to 60 nm, such as 4 nm to 30 nm, although smaller and larger thicknesses may also be employed. there is.

28A-28D, at least one dielectric liner 62, 64 may be selectively formed over the physically exposed surface of the first example structure by at least one conformal deposition process. The at least one dielectric liner 62, 64 may include, for example, a stack of a silicon oxide liner 62 and a silicon nitride liner 64. Contact level dielectric layer 80 includes gate stacks 50, 52, 53, source/drain regions {(31, 32), (38, 39)}, shallow trench isolation structures 20, and optionally at least one It may be deposited over dielectric liners 62 and 64. Contact level dielectric layer 80 includes a dielectric material such as silicon oxide. A planarization process, such as a chemical mechanical planarization process, may optionally be performed to planarize the top surface of the contact level dielectric layer 80. The vertical distance between the top surface of the contact level dielectric layer 80 and the top surface of the gate electrodes 52, 53, 59 may range from 50 nm to 500 nm, although smaller and larger vertical distances may also be employed.

29A-29D, a contact via cavity may be formed through the contact level dielectric layer 80 and filled with at least one conductive material, such as at least one metallic material. The excess portion of at least one conductive material may be removed from above the horizontal plane comprising the top surface of the contact level dielectric layer 80 by a planarization process, which may include a recess etch process and/or a chemical mechanical planarization process. . Each remaining portion of at least one conductive material constitutes a contact via structure 82, 85, 88. Contact via structures 82, 85, and 88 include a source contact via structure 82 contacting each of the source silicide regions 33, a drain contact via structure 88 contacting each of the drain silicide regions 37, and It may include a gate contact via structure 85 in contact with each of the gate silicide regions 59 .

Figure 29E shows an alternative configuration of a third alternative exemplary structure of the third embodiment. In this alternative configuration, at least one dielectric liner 62, 64 shown in FIGS. 28A-28D is deposited by a silicide process prior to depositing the metal layer forming silicide regions 33, 37, 59. At least one of the dielectric liners 62 and 64 is etched using an anisotropic sidewall spacer etch process to form additional sidewall spacers 62S and 64S on the sides of the gate electrodes 52 and 53. After forming additional sidewall spacers 62S 64S, a metal layer is deposited over the third alternative exemplary structure, including over additional sidewall spacers 62S 64S. Silicide eutectic annealing is then performed to form silicide regions 33, 37, 59 of an alternative third exemplary structure, as described above with respect to FIGS. 27A-27D.

21A-29E and the related drawings and in accordance with a third embodiment of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising: first and second field effect transistors 200A, 200B, Each of the first and second field effect transistors 200A and 200B is a semiconductor device including: a source region 31 and 32, a channel region and a drain region 38 and 39 arranged along a first horizontal direction hd1. active area (10A); A gate dielectric 50 in contact with the upper surface of the channel region; a gate electrode (52, 53, 59) overlying the gate dielectric (50) and including semiconductor gate electrode portions (52, 53) and a gate silicide region (59); and first and second field effect transistors, comprising a dielectric gate spacer (56) laterally surrounding the gate electrodes (52, 53, 59); and a shallow trench isolation structure (20) laterally surrounding each of the semiconductor active regions (10A) of the first and second two field effect transistors (200A, 200B), wherein the shallow trench isolation structure (20) includes two via cavities (as shown in FIGS. 25A-25D) that are laterally separated along the first horizontal direction hd1; The dielectric gate spacers 56 of the first and second field effect transistors 200A, 200B include downwardly protruding portions that fill the two via cavities 11 in the shallow trench isolation structure 20.

In one embodiment, two via cavities 11 are connected by a planar top surface (e.g., an intermediate horizontal plane segment (IHSS)) of shallow trench isolation structure 20 and connect first and second field effect transistors 200A, 200B. ) is located in the inter-gate region 20I between the gate electrodes 52, 53, and 59.

In one embodiment, the first and second field effect transistors each include: a source silicide region (33) in contact with each of the source regions (31, 32); and a drain silicide region 37 in contact with each drain region 28, 29.

In one embodiment, each of the source silicide region 33 and drain silicide region 37 of the first and second field effect transistors 200A and 200B contacts a respective sidewall of the dielectric gate spacer 56.

In one embodiment, each of the semiconductor gate electrode portions 52 and 53 of the first and second field effect transistors 200A and 200B includes: a lower semiconductor gate electrode in contact with each upper surface of the gate dielectric 50; lower part (52); and an upper semiconductor gate electrode lower portion 53 overlying the lower semiconductor gate electrode portion 52 and in contact with each top segment of the shallow trench isolation structure 20.

In one embodiment, each inter-gate region 20I of shallow trench isolation structure 20 includes: a pair of uppermost horizontal plane segments ( THSS); and an intermediate horizontal surface segment (IHSS) located between each pair of via cavities and adjacent to the uppermost horizontal surface segment (THSS) by a pair of vertical surface segments.

In one embodiment, the intermediate horizontal surface segment (IHSS) is located on the planar top surface of the shallow trench isolation structure 20 connecting the upper edges of the two cavities 11.

30A to 30D, by forming a dielectric gate spacer 56 around each gate strip 50, 52, and 53S after performing the LDD ion implantation step shown in FIGS. 24A to 24D, the present disclosure A fourth example structure according to an embodiment of can be derived from the third example structure of FIGS. 24A-24D. A layer of dielectric gate spacer material may be conformally deposited on dielectric offset spacers 55 located on the sidewalls of the gate strip, and an anisotropic etch process may be performed to remove horizontally extending portions of the dielectric gate spacer material layer. . The dielectric gate spacer material layer includes a dielectric material, such as silicon oxide and/or silicon nitride, and may be formed by at least one chemical vapor deposition process, such as at least one low pressure chemical vapor deposition (LPCVD) process. The remaining portion of the dielectric gate spacer material layer includes dielectric gate spacers 56 laterally surrounding each gate strip 50, 52, 53S. In an illustrative example, each dielectric gate spacer 56 has a thickness of 5 nm to 100 nm, such as 10 nm to 50 nm, measured along the first horizontal direction hd1 over the transistor active area 10A between the inner and outer sidewalls. It can have a range of widths, but smaller and larger widths can also be employed.

In general, each gate strip 50, 52, 53S may extend along a second horizontal direction hd2 across a plurality of semiconductor active regions (i.e., transistor active regions 10A), and may include a plurality of gate dielectrics. (50) and gate electrode strips (52, 53S). The gate electrode strips 52 and 53S may include a plurality of first semiconductor gate electrode portions 52 and second semiconductor gate electrode strips 53S. Each dielectric gate spacer 56 laterally surrounds each gate strip 50, 52, and 53S and extends laterally along the second horizontal direction hd2 over the plurality of semiconductor active regions 10A. Each dielectric gate spacer 56 is formed directly over a plurality of source extension regions 31 arranged along a second horizontal direction hd2 and a plurality of drain extensions arranged along the second horizontal direction hd2. It may be formed directly over area 39.

31A-31D, additional electrical dopants of the second conductivity type are masked by the combination of gate strips 50, 52, 53S, and dielectric gate spacers 56 in unmasked semiconductor material layer 10. It may be injected into the unapplied portion to form deep source/drain regions 32 and 38. Deep source/drain regions 32 and 38 may include, for example, a deep source region 32 and a deep drain region 38. Typically, the atomic concentration of dopants in the deep source/drain regions (32, 38) is greater than the atomic concentration of dopants in the extended source/drain regions (31, 39). In this way, the volume of the source/drain extension regions 31, 39 that overlaps the volume of the deep source/drain regions 32, 38 is incorporated into each one of the deep source/drain regions 32, 38. In one embodiment, the atomic concentration of dopant in the deep source/drain regions 32, 38 may range from 5.0 × 10 ¹⁸ /cm ³ to 2.0 × 10 ²¹ /cm ³ , although lower or higher dopant concentrations may also be used. can be hired.

According to one aspect of the present disclosure, gate strips 50, 52, 53S cover the entire gate-to-gate area of shallow trench isolation structure 20 located between adjacent pairs of transistor active regions 10A. Accordingly, no additional electrical dopant of the second conductivity type is implanted into the portion of transistor active area 10A proximate to the width edge of the gate electrode to be subsequently patterned from gate strips 50, 52, 53S. Accordingly, the lateral spacing between neighboring pairs of semiconductor active regions 10A corresponds to the transverse edge of the gate electrode (i.e., in the gate fringe region) for subsequent patterning from gate strips 50, 52, 53S. The reduction can be achieved without additional implantation of dopants of the second conductivity type in the peripheral portion of the adjacent semiconductor active region 10A.

The unimplanted portion of each transistor active region 10A constitutes a channel region 36. Each channel area 36 may range from 1.0 x 10 ¹⁴ /cm ³ to 1 x 10 ¹⁸ /cm ³ , but lower and higher dopant concentrations may also be employed. Each of the source/drain extension regions 31, 39 and each of the deep source/drain regions 32, 38 each adjacent combination comprises a combination of the source extension regions 31 and the deep source regions 32. It constitutes a source/drain region, which may be a source region (31, 32) or a drain region (38, 39) comprising a combination of a drain extension region (39) and a deep drain region (38). In general, source regions 32, 32 and drain regions 38, 39 may be formed in a portion of each transistor active region 10A laterally spaced from each other by respective channel regions 36 in plan. there is.

32A-32D, photoresist layer 47 is formed over gate strips 50, 52, 53S, dielectric gate spacer 56, and a plurality of semiconductor active regions (i.e., transistor active region 10A). It can be applied. Photoresist layer 47 may be lithographically patterned to form openings 47A spanning portions of gate strips 50, 52, 53S overlying the top surface of shallow trench isolation structure 20. The patterned photoresist layer 47 is arranged along the second horizontal direction hd2 and has at least one row of openings 47A (which may include a plurality of rows of openings) located within the region of the shallow trench isolation structure 20. ) includes. In one embodiment, each opening 47A in patterned photoresist layer 47 has a pair of gate strips 50, 52, 53S underlying each and a pair of gate strips 50, 52, 53S overlying each dielectric gate spacer 56. It includes a pair of first edges spanning a second edge.

Typically, patterned photoresist layer 47 may cover the entire area of each transistor active area 10A that is not covered by gate strips 50, 52, 53S or dielectric gate spacer 56. Patterned photoresist layer 47 includes rectangular openings 47A in areas where gate strips 50, 52, 53S are subsequently cut. In other words, the area of openings 47A in patterned photoresist layer 47 corresponds to the area from which portions of gate strips 50, 52, and 53S are subsequently removed. In one embodiment, the patterned photoresist layer 47 is arranged along the second horizontal direction hd1 and located within and underlying the region of the shallow trench isolation structure 20 and the gate strips 50, 52, 53S. It includes a row of openings 47A with area overlap with each portion of . In one embodiment, a row of rectangular openings 47A may be formed in the patterned photoresist layer 47 over each gate strip 50, 52, 53S.

In one embodiment, each rectangular opening 47A of patterned photoresist layer 47 may have a first pair of straight sidewalls and a second pair of straight sidewalls. The first pair of straight side walls may extend laterally along a first horizontal direction hd1 and extend along the gate length GL of the underlying gate strips 50, 52, 53S (i.e., in the first horizontal direction ( It has a length greater than the lateral dimension along hd1). In one embodiment, a first pair of straight sidewalls may overlie each transistor active area 10A. That is, the area may overlap with each transistor active region 10A on a plane along a vertical direction perpendicular to the top surface of the semiconductor substrate 8. The pair of second side walls may extend laterally along the second horizontal direction hd2 and may overlie and contact the upper surface of each dielectric gate spacer 56 and the underlying gate strip 50, 52, 53S) and has no area overlap. A pair of second sidewalls of each opening 47A in patterned photoresist layer 47 may have area overlap with a peripheral area of an adjacent pair of transistor active regions 10A.

The top segment of the second semiconductor gate electrode strip 53S and two segments of the outer sidewall of the dielectric gate spacer 56 are physically exposed within the region of each opening 47A in the patterned photoresist layer 47. It can be. The width of each rectangular opening in the patterned photoresist layer 47 along the second horizontal direction hd2 is the lateral spacing between neighboring pairs of transistor active regions 10A along the second horizontal direction hd2. It may be larger than, and may be smaller than the lateral spacing between adjacent pairs of gate dielectrics 50 laterally spaced apart along the second horizontal direction hd2. Openings 47A in patterned photoresist layer 47 do not have any area overlap with gate dielectric 50. The length of each rectangular opening 47A in the patterned photoresist layer 47 along the first horizontal direction hd1 may be greater than the gate length of the underlying gate strips 50, 52, 53S, which It is the width of the gate strips 50, 52, and 53S placed below along the first horizontal direction (hd1).

An anisotropic etching process may be performed to etch the unmasked portions of the gate strips 50, 52, and 53S and the dielectric gate spacer 56. The pattern of rows of openings 47A in patterned photoresist layer 47 may be transferred through gate strips 50, 52, 53S and into unmasked areas of dielectric gate spacer 56. The unmasked portion of the offset spacer 55 may be vertically recessed during the anisotropic etch process. Shallow trench isolation structure 20 is masked by patterned photoresist layer 47 and is not etched during the anisotropic etch process.

The pattern of rows of openings in patterned photoresist layer 47 may be transferred through gate strips 50, 52, 53S and to the unmasked portion of dielectric gate spacer 56 by an anisotropic etch process. The unmasked portions of the gate strips 50, 52, and 53S are removed by an anisotropic etching process, and the remaining portions of the gate strips 50, 52, and 53S include a plurality of gate stacks 50, 52, and 53. .

Each gate strip 50, 52, 53S can be divided into gate stacks 50, 52, 53 by removing the unmasked portion of each gate strip 50, 52, 53S. Each of the gate electrode strips 52 and 53S is laterally spaced apart along the second horizontal direction hd2 and each of the plurality of gate electrodes 52 lies on each semiconductor active region of the plurality of semiconductor active regions 10A. 53) can be divided into: Each gate stack 50, 52, 53 includes a vertical stack of a gate dielectric 50, a first semiconductor gate electrode portion 52, and a second semiconductor gate electrode portion 53. Each second semiconductor gate electrode portion 53 is a patterned portion of each second semiconductor gate electrode strip 53S. Each gate dielectric 50 is one of a plurality of gate dielectrics 50 within each gate strip 50, 52, and 53S. Each adjacent combination of the first semiconductor gate electrode portion 52 and the second semiconductor gate electrode portion 53 constitutes gate electrodes 52 and 53. Accordingly, each of the gate electrodes 52 and 53 is a patterned portion of a respective gate electrode strip 52 and 53S.

Each gate stack 50, 52, and 53 is formed on each of the transistor active areas 10A. Each gate stack includes a gate dielectric 50 and gate electrodes 52 and 53.

In one embodiment, the anisotropic etch process etches the material of gate strips 50, 52, 53S at a higher etch rate than the material of dielectric gate spacers 56. A pair of stepped sidewalls may be formed on each dielectric gate spacer 56 beneath each opening in the patterned photoresist layer 47 .

In one embodiment, each dielectric gate spacer 56 includes an over-active area gate spacer portion 56A overlying semiconductor active area 10A, as shown in FIG. 18C. The active-region-above gate spacer portion 56A includes straight inner sidewalls perpendicular to the first horizontal direction hd1 and laterally spaced apart by a first spacing S1, which is the gate spacer inner sidewall spacing, i.e., the dielectric Also referred to as the gap between a pair of inner side walls of gate spacer 56. In one embodiment, each dielectric gate spacer 56 also includes an inter-active region gate spacer portion 56B that overlies a portion of shallow trench isolation structure 20. The inter-active-area gate spacer portion 56B has a lower straight sidewall segment 56L adjacent to and located in the same vertical plane as each pair of straight inner sidewalls of a neighboring over-area gate spacer portion 56A. ), an upper straight sidewall segment 56U laterally offset from the lower straight sidewall segment, and a stepped sidewall comprising a connecting horizontal surface 56H adjacent the upper edge of the lower straight sidewall segment and the lower edge of the upper straight sidewall segment. Includes. The pair of upper straight sidewall segments 56U of the two active-region inter-gate spacer portions 56B located within the same opening 47A in the patterned photoresist layer 47 are herein referred to as the gate spacer upper inner sidewall segments. They may be laterally spaced from each other by a second gap S2', referred to as the gap. The lateral distance between the outer sidewalls of each dielectric gate spacer 56 along the first horizontal direction hd1 may be uniform, with a third spacing S3, also referred to herein as the gate spacer outer sidewall spacing. It is referred to. The second gap S2' may be smaller than the third gap S3.

In one embodiment, the shallow trench isolation structure 20 has a planar top surface located in a horizontal plane and at least in an area covered by a patterned photoresist layer 47 or by a dielectric gate spacer 56. You can. The lower straight sidewall segment 56L of the inter-active region gate spacer portion 56B may contact the planar top surface of the shallow trench isolation structure 20. In one embodiment, each of the upper straight sidewall segments 56U of the inter-active region gate spacer portion 56B is each of the concave outer sidewalls of the inter-active region gate spacer portion 56B of the dielectric gate spacer 56. has each upper edge adjacent to the upper edge of the segment.

In one embodiment, shallow trench isolation structure 20 includes an inter-gate region located between neighboring pairs of semiconductor active regions 10A and within a region surrounded by the outer periphery of each dielectric gate spacer 56. A pair of active-region inter-gate spacer portions 56B overlies each inter-gate region. In one embodiment, upper straight sidewall segments 56U of a pair of inter-active region gate spacer portions 56B have a first horizontal offset by a gate spacer upper inner sidewall segment spacing (equal to second spacing S2'). They are laterally spaced apart from each other along the direction hd1. The lower straight sidewall segment 56L of the pair of active-region inter-gate spacer portions 56B has a first gate spacer inner sidewall spacing (equal to first spacing S1) that is less than the gate spacer upper inner sidewall segment spacing. They are laterally spaced apart from each other along the horizontal direction. In embodiments where offset spacers 55 are omitted, the gate spacer inner sidewall spacing (such as first spacing S1) may be equal to the gate length. In one embodiment, a pair of straight inner sidewalls of each active-region-above gate spacer portion 56A is laterally along a first horizontal direction by a gate spacer inner sidewall spacing (e.g., first spacing S1). can be separated from

Typically, each gate strip (50, 52, 53S) is formed into a shallow trench isolation structure ( It can be divided into gate stacks 50, 52, and 53 by removing portions of the gate strips 50, 52, and 53S that lie over the interelectrode region 20I of 20).

33A-33E, patterned photoresist layer 47 may be removed, for example, by ashing. In one embodiment, the straight inner sidewall of the active-region over-gate spacer portion 56A extends at least the gate electrodes 52 and 53 from the first horizontal plane HP1 including the lower surface of the gate electrodes 52 and 53. It extends to a second horizontal surface (HP2) including the upper surface. The entire connecting surface of the over-active-area gate spacer portion 56A is located above the first horizontal plane HP1 and below the second horizontal plane HP2. In one embodiment, the straight inner sidewalls of the over-active region gate spacer portion 56A contact the top surfaces of the source regions 31 and 32 and drain regions 38 and 39.

Referring to Figures 34A-34D, a metal layer may be deposited over the fourth example structure. The metal layer includes and/or consists essentially of a metal that forms a silicide with the semiconductor material of the transistor active region 10A and the upper semiconductor gate electrode subportion 53. For example, the semiconductor material of transistor active region 10A and upper semiconductor gate electrode subportion 53 may include amorphous silicon, polysilicon, or a silicon-germanium alloy, and the metal layer may include tungsten, titanium, tantalum, It may comprise and/or consist essentially of at least one metal selected from cobalt, molybdenum, platinum, and/or nickel. The metal layer may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the horizontally extending portion of the metal layer may range from 6 nm to 60 nm, such as 12 nm to 30 nm, although smaller and larger thicknesses may also be employed.

A thermal or flash lamp annealing process can be performed to induce a reaction between the metal layer and the underlying semiconductor material portion by a silicide process. The surface portion of the upper semiconductor gate electrode lower portion 53 (which is the surface portion of the semiconductor gate electrode portions 52 and 53) is converted into a gate silicide region 59 by reacting with the metal. The surface portions of the deep source/drain regions (32, 38) are converted into source/drain silicide regions (33, 37) by reacting with the metal. The unreacted portion of the metal layer may be removed selectively to the silicide material of the gate silicide region 59 and source/drain silicide regions 33, 37. The silicide materials of gate silicide region 59 and source/drain silicide regions 33, 37, respectively, may have a thickness ranging from 2 nm to 60 nm, such as 4 nm to 30 nm, although smaller and larger thicknesses may also be employed. there is.

In one embodiment, the gate silicide region 59 is a first horizontally extending portion in contact with a top surface of the underlying upper semiconductor gate electrode subportion 53, each of the underlying upper semiconductor gate electrode subportions 53. a pair of vertically extending portions in contact with each sidewall segment of the sidewall segment and the underlying lower semiconductor gate electrode subportion 52, and with a recessed horizontal surface of the underlying lower semiconductor gate electrode subportion 52; and a pair of second horizontally-extended portions.

35A-35D, at least one layer of dielectric material 62, 64, 80 can be deposited over the second example structure. In one embodiment, the at least one layer of dielectric material (62, 64, 80) comprises at least one conformal dielectric liner (62, 64) and a contact level dielectric layer overlying the at least one conformal dielectric liner (62, 64). It contains a vertical stack containing (80). At least one dielectric liner (62, 64) each has a gate stack (50, 52, 53), a dielectric gate spacer (56), a source region (31, 32), and a drain region ( 38, 39) can be deposited on physically exposed surfaces. The at least one dielectric liner 62, 64 may include, for example, a stack of a silicon oxide liner 62 and a silicon nitride liner 64. Contact level dielectric layer 80 includes gate stacks 50, 52, 53, source/drain regions {(31, 32), (38, 39)}, shallow trench isolation structures 20, and optionally at least one It may be deposited over dielectric liners 62 and 64. Contact level dielectric layer 80 includes a dielectric material, such as silicon oxide. A planarization process, such as a chemical mechanical planarization process, may optionally be performed to planarize the top surface of the contact level dielectric layer 80. The vertical distance between the top surface of the contact level dielectric layer 80 and the top surface of the gate electrodes 52, 53, 59 may range from 50 nm to 500 nm, although smaller and larger vertical distances may also be employed. Contact via structures 82, 85, 88 are then formed through contact level dielectric layer 80 as described above.

35E shows an alternative configuration of a third alternative exemplary structure of the third embodiment. In this alternative configuration, at least one dielectric liner 62, 64 shown in FIGS. 35A-35D is deposited by a silicide process prior to depositing the metal layer forming silicide regions 33, 37, 59. At least one of the dielectric liners 62 and 64 is etched using an anisotropic sidewall spacer etch process to form additional sidewall spacers 62S and 64S on the sides of the gate electrodes 52 and 53. After forming additional sidewall spacers 62S 64S, a metal layer is deposited over the third alternative exemplary structure, including over additional sidewall spacers 62S 64S. Silicide eutectic annealing is then performed to form silicide regions 33, 37, 59 of an alternative third exemplary structure, as described above with respect to FIGS. 34A-34D.

30A-35E and the related drawings and in accordance with a fourth embodiment of the present disclosure, a semiconductor structure is provided, the semiconductor structure comprising: first and second field effect transistors 200A, 200B, Each of the first and second field effect transistors 200A and 200B is a semiconductor device including: a source region 31 and 32, a channel region and a drain region 38 and 39 arranged along a first horizontal direction hd1. active area (10A); A gate dielectric 50 in contact with the upper surface of the channel region; a gate electrode (52, 53, 59) overlying the gate dielectric (50) and including semiconductor gate electrode portions (52, 53) and a gate silicide region (59); a pair of dielectric gate spacers (56) located on opposite sides of the gate electrodes (52, 53, 59); A shallow trench isolation structure (20) laterally surrounding each of the semiconductor active regions (10A) of the first and second two field effect transistors (200A, 200B), wherein the pair of dielectric gate spacers (56) ) each having: an over-active area gate spacer portion 56A overlying the semiconductor active area 10A; and an active-region inter-gate spacer portion 56B overlying a portion of the shallow trench isolation structure 20 and including stepped sidewalls.

In one embodiment, each of the stepped sidewalls includes: a lower straight sidewall segment 56L adjacent each pair of straight inner sidewalls; an upper straight sidewall segment (56U) laterally offset from the lower straight sidewall segment (56L); and a connecting surface 56H adjacent the upper edge of the lower straight sidewall segment 56L and the lower edge of the upper straight sidewall segment 56U.

In one embodiment, shallow trench isolation structure 20 has a planar top surface located in a horizontal plane and in areas not covered by gate electrodes 52, 53, and 59; Lower straight sidewall segment 56L contacts the planar top surface of shallow trench isolation structure 20.

In one embodiment, the over-active region gate spacer portion 56B includes straight inner sidewalls perpendicular to the first horizontal direction hd1. In one embodiment, the straight inner sidewall extends from a first horizontal plane comprising at least the lower surfaces of the gate electrodes 52, 53, 59 and to a second horizontal plane comprising at least the upper surfaces of the gate electrodes 52, 53, 59. .

In one embodiment, the first and second field effect transistors 200A, 200B each include: a source silicide region 33 in contact with each of the source regions 31, 32; and a drain silicide region 37 in contact with each drain region 38, 39.

In one embodiment, the source silicide region 33 and drain silicide region 37 of the first and second field effect transistors 200A, 200B each contact a respective sidewall of a pair of dielectric gate spacers 56. .

In one embodiment, shallow trench isolation structure 20 has an inter-gate region 20I located between adjacent pairs of semiconductor active regions 10A and within a region surrounded by the outer periphery of a pair of dielectric gate spacers 56. Includes; A pair of active-region inter-gate spacer portions 56B overlies each inter-gate region 20I.

Using various embodiments of the present disclosure, a semiconductor structure comprising a plurality of field effect transistors having a high transistor density is provided with reduced lateral spacing between neighboring pairs of semiconductor active regions 10A. Additionally, the silicide region reduces gate, source and drain resistance.

It will be understood that although the foregoing refers to certain preferred embodiments, the disclosure is not so limited. It will occur to those skilled in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to remain within the scope of the present disclosure. Where embodiments employing a particular structure and/or configuration are illustrated in the present disclosure, the disclosure may be practiced with any other functionally equivalent, interchangeable structure and/or configuration—although such substitutions are expressly prohibited or otherwise provided to those skilled in the art. Unless it is known to be impossible - it is understood. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims (60)

As a semiconductor structure,
First and second field effect transistors, wherein each of the first and second field effect transistors:
a semiconductor active region including a source region, a channel region, and a drain region arranged along a first horizontal direction;
a gate dielectric in contact with the top surface of the channel region;
a gate electrode placed on the gate dielectric; and
first and second field effect transistors including a dielectric gate spacer laterally surrounding the gate electrode; and
A shallow trench isolation structure laterally surrounding each of the semiconductor active regions of the first and second two field effect transistors,
the shallow trench isolation structure has a planar top surface between two via cavities extending in the first horizontal direction and located in an inter-gate region between gate electrodes of the first and second field effect transistors;
wherein the dielectric gate spacers of the first and second field effect transistors include downwardly protruding portions that fill the two via cavities in the shallow trench isolation structure. 2. The method of claim 1, further comprising a dielectric offset spacer located only on two sides of each of the gate electrodes extending in a second horizontal direction perpendicular to the first horizontal direction,
here,
the gate dielectric spacer laterally surrounds each of the gate electrodes on all four sides;
the gate dielectric spacer is in physical contact with the dielectric offset spacer over two sides of each of the gate electrodes extending in the second horizontal direction;
and wherein the gate dielectric spacer is in physical contact with two other sides of each of the gate electrodes extending in the first horizontal direction. According to paragraph 1,
Each of the dielectric gate spacers is directed toward a respective gate electrode, extends laterally along a second horizontal direction perpendicular to the first horizontal direction, and extends laterally along the first horizontal direction by a gate spacer inner sidewall spacing. comprising a pair of spaced apart inner longitudinal side walls;
The semiconductor structure of claim 1, wherein the pair of via cavities includes a pair of proximal sidewalls laterally spaced along the first horizontal direction by the gate spacer inner sidewall spacing. According to paragraph 3,
Each of the dielectric gate spacers is a pair of dielectric gate spacers, each facing away from the respective gate electrode, extending laterally along the second horizontal direction, and laterally spaced along the first horizontal direction by a gate spacer outer sidewall spacing. comprising an outer longitudinal side wall of;
and wherein the pair of via cavities includes a pair of distal sidewalls laterally spaced along the first horizontal direction by a trench distal sidewall spacing that is less than the gate spacer outer sidewall spacing. 2. The method of claim 1, wherein outer widthwise sidewalls of adjacent pairs of dielectric gate spacers are adjacent to each other in a vertical seam extending laterally along the first horizontal direction over each inter-gate region of the shallow trench isolation structure. Contacting semiconductor structures. 2. The method of claim 1, wherein each gate-to-gate region of the shallow trench isolation structure:
a pair of uppermost horizontal surface segments in contact with each lower surface segment of a neighboring pair of gate electrodes; and
A semiconductor structure, comprising an intermediate horizontal plane segment adjacent the uppermost horizontal plane segment by a pair of vertical plane segments and positioned between each pair of via cavities. 7. The semiconductor structure of claim 6, wherein the intermediate horizontal plane segment is located above a planar top surface of the shallow trench isolation structure. According to clause 6,
The bottom surface of the via cavity is located below the planar top surface of the shallow trench isolation structure;
each of the via cavities includes a pair of stepped proximal sidewalls having respective horizontal steps located between an upper vertical proximal sidewall segment and a lower vertical proximal sidewall segment;
Each of the gate electrodes includes a pair of longitudinal side walls spaced laterally along the first horizontal direction by the length of the gate;
and wherein a lateral spacing between a pair of horizontal steps of the pair of stepped proximal sidewalls over each inter-gate region of the shallow trench isolation structure is equal to the gate length. The method of claim 1, wherein each of the gate electrodes:
a semiconductor gate electrode portion in contact with each upper surface of the gate dielectric; and
A semiconductor structure comprising a metal gate electrode portion overlying the semiconductor gate electrode portion. According to clause 9,
the semiconductor gate electrode portion contacts a sidewall of a region between a pair of gates of the shallow trench isolation structure;
the semiconductor gate electrode portion includes a top surface located in the same horizontal plane as a topmost segment of a region between a pair of gates of the shallow trench isolation structure;
wherein the metal gate electrode portion contacts a topmost segment of a region between a pair of gates of the shallow trench isolation structure. According to clause 9,
A longitudinal sidewall of the metal gate electrode portion perpendicular to the first horizontal direction is vertically aligned with a longitudinal sidewall of the semiconductor gate electrode portion,
a width-direction sidewall of the metal gate electrode portion parallel to the first horizontal direction is laterally offset outward from a width-direction sidewall of the semiconductor gate electrode portion;
Each gate-to-gate region of the shallow trench isolation structure extends laterally along the first horizontal direction, adjacent a respective topmost segment of the gate-to-gate region of the shallow trench isolation structure, and each of the dielectric gate spacers. A semiconductor structure comprising a pair of sidewall segments contacted by sidewalls of 2. The semiconductor structure of claim 1, wherein each dielectric gate spacer in the first and second field effect transistors includes four downwardly protruding portions extending vertically into four via cavities in the shallow trench isolation structure. According to paragraph 1,
Each of the via cavities has a pair of first sidewalls parallel to the first horizontal direction and perpendicular to the width direction sidewalls of neighboring pairs of gate electrodes, and a pair of first sidewalls perpendicular to the first horizontal direction and perpendicular to the first horizontal direction. comprising a second pair of side walls adjacent vertically extending edges of the side walls;
Each of the gate electrodes includes a pair of longitudinal side walls perpendicular to the first horizontal direction and laterally spaced apart along the first horizontal direction by the length of the gate;
and the second pair of sidewalls comprises a pair of sidewall segments laterally spaced along the first horizontal direction by the gate length. As a field effect transistor,
a semiconductor active region including a source region, a channel region, and a drain region arranged along a first horizontal direction;
a gate dielectric in contact with the top surface of the channel region;
a gate electrode having four sides overlying the gate dielectric;
a dielectric gate spacer laterally surrounding the gate electrode on the four sides; and
a dielectric offset spacer located only on two sides of the gate electrode extending in a second horizontal direction perpendicular to the first horizontal direction,
here,
the gate dielectric spacer is in physical contact with the dielectric offset spacer on the two sides of the gate electrode extending in the second horizontal direction;
A field effect transistor, wherein the gate dielectric spacer is in physical contact with two other sides of the gate electrode extending in the first horizontal direction. A method of forming a semiconductor device, comprising:
forming a shallow trench isolation structure in an upper region of a semiconductor substrate having doping of a first conductivity type, the shallow trench isolation structure being a patterned portion of the semiconductor substrate and having longitudinal edges parallel to a first horizontal direction; laterally surrounding a plurality of semiconductor active regions, laterally spaced apart along a second horizontal direction perpendicular to the first horizontal direction;
Form a gate strip including a vertical stack of a gate electrode strip and a plurality of gate dielectrics over the plurality of semiconductor active regions, wherein the gate strip is located across each of the plurality of semiconductor active regions and between the plurality of semiconductor active regions. extending continuously as a single continuous structure over a portion of the shallow trench isolation structure;
forming a source/drain extension region by implanting a dopant of a second conductivity type into surface portions of the plurality of semiconductor active regions that are not masked by the gate strip after formation of the gate strip; and
Partitioning the gate strip into the gate stack by removing a portion of the gate strip located within a region of the shallow trench isolation structure after forming the source/drain extension region. 16. The method of claim 15, wherein each gate stack includes a gate dielectric and gate electrode of a respective field effect transistor. The method of claim 16 further comprising:
forming dielectric gate spacers around the gate stack, each neighboring pair of dielectric gate spacers contacting each other along a respective vertical plane parallel to the first horizontal direction; and
forming a deep source/drain region by implanting a dopant of the second conductivity into portions of the plurality of semiconductor active regions that are not masked by the gate electrode and the dielectric gate spacer. 18. The method of claim 17, further comprising forming a dielectric offset spacer on sidewalls of the gate strip,
here,
the gate dielectric spacer is in physical contact with the dielectric offset spacer over two sides of each of the gate electrodes extending in the second horizontal direction;
wherein the gate dielectric spacer is in physical contact with two other sides of each of the gate electrodes extending in the first horizontal direction. The method of claim 17 further comprising:
Forming a patterned photoresist layer over the gate strip and the plurality of semiconductor active regions, wherein the patterned photoresist layer is arranged along the second horizontal direction and includes a row of openings located within a region of the shallow trench isolation structure. Steps comprising; and
Transferring the pattern of the rows of openings in the patterned photoresist layer through the gate strip and into an unmasked region of the shallow trench isolation structure to divide the gate strip into the gate stack and to divide the patterned photoresist into the gate stack. forming a pair of via cavities extending vertically into the shallow trench isolation structure at each opening in the row of openings in a layer. 20. The method of claim 19, wherein each of the via cavities is filled by a downwardly protruding portion of a dielectric gate spacer of each pair of the dielectric gate spacers. As a semiconductor structure,
First and second field effect transistors, wherein each of the first and second field effect transistors:
a semiconductor active region including a source region, a channel region, and a drain region arranged along a first horizontal direction;
a gate dielectric in contact with the top surface of the channel region;
a gate electrode placed on the gate dielectric; and
first and second field effect transistors comprising a pair of dielectric gate spacers located on opposite sides of the gate electrode; and
A shallow trench isolation structure laterally surrounding each of the semiconductor active regions of the first and second two field effect transistors,
Each of the pair of dielectric gate spacers:
an over-active area gate spacer portion overlying the semiconductor active area and including straight inner sidewalls perpendicular to the first horizontal direction; and
a lower straight sidewall segment overlying a portion of the shallow trench isolation structure and adjacent each pair of straight inner sidewalls, an upper straight sidewall segment laterally offset from the lower straight sidewall segment, and an upper edge of the lower straight sidewall segment. A semiconductor structure comprising an inter-active region gate spacer portion comprising a stepped sidewall and a connecting surface adjacent a lower edge of the upper straight sidewall segment. 22. The semiconductor structure of claim 21, wherein the straight inner sidewall extends vertically from a first horizontal plane comprising at least a lower surface of the gate electrode and to a second horizontal plane comprising at least a upper surface of the gate electrode. 23. The semiconductor structure of claim 22, wherein the entirety of the connecting surface is located above the first horizontal plane and below the second horizontal plane. 23. The semiconductor structure of claim 22, wherein the straight inner sidewall contacts top surfaces of the source region and the drain region. According to clause 21,
the shallow trench isolation structure has a planar top surface located in a horizontal plane and within an area not covered by the gate electrode;
wherein the lower straight sidewall segment contacts a planar top surface of the shallow trench isolation structure. According to clause 21,
each of the straight inner sidewalls having a respective upper edge adjacent an upper edge of a respective segment of the concave outer sidewall of the dielectric gate spacer;
and wherein each of the upper straight sidewall segments has a respective upper edge adjacent an upper edge of a respective additional segment of a concave outer sidewall of the dielectric gate spacer. According to clause 21,
the shallow trench isolation structure includes an inter-gate region located between adjacent pairs of semiconductor active regions and within a region surrounded by an outer periphery of the pair of dielectric gate spacers;
A semiconductor structure wherein a pair of active-region inter-gate spacer portions overlies each of the inter-gate inter-regions. According to clause 27,
upper straight sidewall segments of the pair of inter-active region gate spacer portions are laterally spaced from each other along the first horizontal direction by a gate spacer upper inner sidewall segment spacing;
wherein the lower straight sidewall segments of the pair of inter-active region gate spacer portions are laterally spaced from each other along the first horizontal direction by a gate spacer inner sidewall spacing that is less than the gate spacer upper inner sidewall segment spacing. . 29. The semiconductor structure of claim 28, wherein a pair of straight inner sidewalls of each of the above-active-region gate spacer portions are laterally spaced along the first horizontal direction by the gate spacer inner sidewall spacing. 22. The method of claim 21, further comprising at least one layer of dielectric material overlying the gate electrode and the dielectric gate spacer, wherein each of the gate electrodes is parallel to the first horizontal direction and directly connected to the at least one layer of dielectric material. A semiconductor structure comprising each transverse sidewall in contact. 31. The semiconductor structure of claim 30, wherein at least one of the gate electrodes includes a pair of transverse sidewalls contacting a respective sidewall of the at least one layer of dielectric material. According to clause 30,
the at least one layer of dielectric material comprises a vertical stack including at least one conformal dielectric liner and a contact level dielectric layer overlying the at least one conformal dielectric liner;
wherein the at least one conformal dielectric liner contacts each of the source region, the drain region, a top surface of the shallow trench isolation structure, and a stepped sidewall of the active-region inter-gate spacer portion. 33. The method of claim 32, wherein the at least one conformal dielectric liner is disposed at a top edge of a straight inner sidewall of the above-active region gate spacer portion and at an upper edge of a stepped sidewall of the inter-active region gate spacer portion. A semiconductor structure in contact with the entirety of the concave outer sidewall of the adjacent dielectric gate spacer. 22. The method of claim 21, wherein each of the gate electrodes:
a semiconductor gate electrode portion in contact with each upper surface of the gate dielectric; and
a metal gate electrode portion overlying the semiconductor gate electrode portion and having a first length along a second horizontal direction perpendicular to the first horizontal direction,
The semiconductor gate electrode portion includes an upper region having the first length and a lower region having a second length along the second horizontal direction that is greater than the first length,
The first length of the metal gate electrode portion along the second horizontal direction is smaller than the length of the active region in the second horizontal direction, so that the edge of the metal gate electrode portion extending along the first horizontal direction is the A semiconductor structure positioned above the active region. 35. The method of claim 34, wherein the semiconductor gate electrode portion:
an upper width-direction sidewall extending laterally along the first horizontal direction and perpendicular to the width-direction sidewall of the metal gate electrode portion;
a lower transverse sidewall extending laterally along the second horizontal direction and contacting a sidewall segment of the shallow trench isolation structure; and
A semiconductor structure comprising a horizontal plane segment connecting an upper edge of each of the lower transverse side walls to a lower edge of each of the upper transverse side walls. A method of forming a semiconductor device, comprising:
forming a shallow trench isolation structure in an upper region of a semiconductor substrate having doping of a first conductivity type, the shallow trench isolation structure being a patterned portion of the semiconductor substrate and having longitudinal edges parallel to a first horizontal direction; laterally surrounding a plurality of semiconductor active regions, laterally spaced apart along a second horizontal direction perpendicular to the first horizontal direction;
forming a gate strip over the plurality of semiconductor active regions, the gate strip including a plurality of gate dielectrics and one gate electrode strip;
forming a dielectric gate spacer around the gate strip;
forming deep source/drain regions by implanting a dopant of a second conductivity type opposite to the first conductivity type into portions of the plurality of semiconductor active regions that are not masked by the gate strip and the dielectric gate spacer; and
After forming the deep source/drain regions, dividing the gate electrode strip into a plurality of gate electrodes laterally spaced along the second horizontal direction and overlying each of the plurality of semiconductor active regions. . 37. The method of claim 36, wherein after formation of the gate strip and before formation of the dielectric gate spacer, the source is formed by implanting additional dopants of the second conductivity type into surface portions of the plurality of semiconductor active regions that are not masked by the gate strip. /The method further comprising forming a drain extension region. The method of claim 37 further comprising:
Forming a patterned photoresist layer over the gate strip, the dielectric gate spacer, and the plurality of semiconductor active regions, wherein the patterned photoresist layer is arranged along the second horizontal direction and is located in the shallow trench isolation structure. comprising a row of openings located within the region; and
The pattern of the rows of openings in the patterned photoresist layer is transferred through the gate strip and into an unmasked portion of the dielectric gate spacer by performing an anisotropic etch process, wherein the anisotropic etch process is Removing the unmasked portion and remaining portion of the gate electrode strip comprising the plurality of gate electrodes. According to clause 38,
the anisotropic etch process etches the material of the gate electrode strip at a higher etch rate than the material of the dielectric gate spacer;
Wherein each opening in the patterned photoresist layer includes a pair of first edges spanning a corresponding gate strip and a second pair of edges overlying the dielectric gate spacer. 39. The method of claim 38, wherein a pair of stepped sidewalls are formed on the dielectric gate spacer beneath each opening in the patterned photoresist layer. As a semiconductor structure,
First and second field effect transistors, wherein each of the first and second field effect transistors:
a semiconductor active region including a source region, a channel region, and a drain region arranged along a first horizontal direction;
a gate dielectric in contact with the top surface of the channel region;
a gate electrode overlying the gate dielectric and including a semiconductor gate electrode portion and a gate silicide region; and
first and second field effect transistors including a dielectric gate spacer laterally surrounding the gate electrode; and
A shallow trench isolation structure laterally surrounding each of the semiconductor active regions of the first and second two field effect transistors,
the shallow trench isolation structure includes two via cavities laterally isolated along the first horizontal direction;
wherein the dielectric gate spacers of the first and second field effect transistors include downwardly protruding portions that fill the two via cavities in the shallow trench isolation structure. 42. The semiconductor structure of claim 41, wherein the two via cavities are connected by a planar top surface of the shallow trench isolation structure and are located within an inter-gate region between gate electrodes of the first and second field effect transistors. 42. The device of claim 41, wherein each of the first and second field effect transistors:
a source silicide region in contact with each source region; and
A semiconductor structure comprising a drain silicide region in contact with each drain region. 44. The semiconductor structure of claim 43, wherein each of the source silicide region and drain silicide region of the first and second field effect transistors contacts a respective sidewall of the dielectric gate spacer. 42. The method of claim 41, wherein each semiconductor gate electrode portion of the first and second field effect transistors is:
a lower portion of the lower semiconductor gate electrode in contact with each upper surface of the gate dielectric; and
A semiconductor structure comprising an upper semiconductor gate electrode lower portion overlying the lower semiconductor gate electrode portion and in contact with each top segment of the shallow trench isolation structure. 42. The method of claim 41, wherein each gate-to-gate region of the shallow trench isolation structure:
a pair of uppermost horizontal surface segments in contact with each lower surface segment of a neighboring pair of gate electrodes; and
A semiconductor structure, comprising an intermediate horizontal plane segment adjacent the uppermost horizontal plane segment by a pair of vertical plane segments and positioned between each pair of via cavities. 47. The semiconductor structure of claim 46, wherein the intermediate horizontal plane segment is located on a planar top surface of the shallow trench isolation structure connecting upper edges of the two cavities. As a semiconductor structure,
First and second field effect transistors, wherein each of the first and second field effect transistors:
a semiconductor active region including a source region, a channel region, and a drain region arranged along a first horizontal direction;
a gate dielectric in contact with the top surface of the channel region;
a gate electrode overlying the gate dielectric and including a semiconductor gate electrode portion and a gate silicide region; and
first and second field effect transistors comprising a pair of dielectric gate spacers located on opposite sides of the gate electrode; and
A shallow trench isolation structure laterally surrounding each of the semiconductor active regions of the first and second two field effect transistors,
Each of the pair of dielectric gate spacers:
an over-active area gate spacer portion overlying the semiconductor active area; and
A semiconductor structure comprising an inter-active region gate spacer portion overlying a portion of the shallow trench isolation structure and including stepped sidewalls. 49. The system of claim 48, wherein each of said stepped sidewalls:
a lower straight sidewall segment adjacent each pair of straight inner sidewalls;
an upper straight sidewall segment laterally offset from the lower straight sidewall segment; and
A semiconductor structure comprising an upper edge of the lower straight sidewall segment and a connecting surface adjacent the lower edge of the upper straight sidewall segment. According to clause 49,
the shallow trench isolation structure has a planar top surface located in a horizontal plane and within an area not covered by the gate electrode;
wherein the lower straight sidewall segment contacts a planar top surface of the shallow trench isolation structure. 49. The semiconductor structure of claim 48, wherein the over-active region gate spacer portion includes straight inner sidewalls perpendicular to the first horizontal direction. 52. The semiconductor structure of claim 51, wherein the straight inner sidewall extends vertically from a first horizontal plane comprising at least a lower surface of the gate electrode and to a second horizontal plane comprising at least a upper surface of the gate electrode. 49. The method of claim 48, wherein each of the first and second field effect transistors:
a source silicide region in contact with each source region; and
A semiconductor structure comprising a drain silicide region in contact with each drain region. 54. The semiconductor structure of claim 53, wherein each of the source silicide region and drain silicide region of the first and second field effect transistors contacts a respective sidewall of the pair of dielectric gate spacers. According to clause 48,
the shallow trench isolation structure includes an inter-gate region located between adjacent pairs of semiconductor active regions and within a region surrounded by an outer periphery of the pair of dielectric gate spacers;
A semiconductor structure, wherein a pair of active-region inter-gate spacer portions overlies each of the inter-gate inter-region regions. A method of forming a semiconductor device, comprising:
forming a shallow trench isolation structure in an upper region of a semiconductor substrate having a first conductivity type of doping, the shallow trench isolation structure laterally surrounding a plurality of semiconductor active regions that are a patterned portion of the semiconductor substrate. ;
Form a gate strip including a vertical stack of a gate electrode strip and a plurality of gate dielectrics over the plurality of semiconductor active regions, wherein the gate strip extends continuously as a single continuous structure across each of the plurality of semiconductor active regions and the shallow covering the inter-electrode region of the trench isolation structure;
forming a source/drain extension region by implanting a dopant of a second conductivity type into surface portions of the plurality of semiconductor active regions that are not masked by the gate strip after formation of the gate strip;
forming a deep source/drain region by implanting additional dopant of the second conductivity type within a portion of the plurality of semiconductor active regions without implanting additional dopant of the second conductivity type into the inter-electrode region of the shallow trench isolation structure. steps; and
The gate strip is formed by removing a portion of the gate strip overlying the inter-electrode region of the shallow trench isolation structure after forming the source/drain extension region and before or after forming the deep source/drain region. A method comprising dividing into stacks. 57. The method of claim 56, wherein the portion of the gate strip that overlies the inter-electrode region of the shallow trench isolation structure is removed prior to forming the deep source/drain region. 58. The method of claim 57, wherein a dielectric gate spacer is formed around the gate electrode and over the inter-electrode region of the shallow trench isolation structure, the dielectric gate spacer being of the second conductivity type within the inter-electrode region of the shallow trench isolation structure. A method further comprising preventing injection of additional dopant. 57. The method of claim 56, wherein the portion of the gate strip that overlies the inter-electrode region of the shallow trench isolation structure is removed after forming the deep source/drain region. According to clause 56,
Each of the gate stacks includes a respective gate dielectric and a respective semiconductor gate electrode portion;
The method further comprises converting a surface portion of each of the semiconductor gate electrode portions into a respective gate silicide region by reacting the surface portion of each of the semiconductor gate electrode portions with a metal.

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