KR20240126388A - Memory storing meta data and operation method of memory - Google Patents

Abstract

A method of operating a memory may include: receiving a metadata read command and a first address; reading metadata from memory cells of columns corresponding to the first address and storing the metadata in a metadata latch; receiving a normal read command and a second address; reading normal read data from memory cells of columns corresponding to the second address; and outputting the normal read data and a portion of the metadata stored in the metadata buffer.

Description

MEMORY STORING META DATA AND OPERATION METHOD OF MEMORY

The present invention relates to a memory that stores metadata together with normal data.

Recently, as the number of applications utilizing artificial intelligence and big data increases, the amount of data that needs to be processed is increasing explosively. Many computer systems (e.g., data centers, servers, etc.) require a large amount of memory, and applications that utilize computer systems require more memory than the system's capacity. In addition, as the amount of data increases, the importance of metadata required for data management is increasing.

Accordingly, a method for efficiently storing metadata in addition to normal data in memory is required.

Embodiments of the present invention can provide a method for efficiently storing and accessing metadata in memory.

A method of operating a memory according to one embodiment of the present invention may include: receiving a metadata read command and a first address; reading metadata from memory cells of columns corresponding to the first address and storing the metadata in a metadata latch; receiving a normal read command and a second address; reading normal read data from memory cells of columns corresponding to the second address; and outputting the normal read data and a portion of the metadata stored in the metadata buffer.

According to one embodiment of the present invention, a method of operating a memory may include: receiving a metadata read command and a first address; reading metadata from memory cells of columns corresponding to the first address and storing the metadata in a metadata buffer; receiving a normal write command, a second address, normal write data, and write metadata; writing the normal write data to memory cells of columns corresponding to the second address; replacing a portion of the metadata of the metadata buffer selected by the second address with the write metadata; receiving a metadata write command; and writing the metadata of the metadata buffer to memory cells of columns corresponding to the first address.

A method of operating a memory according to one embodiment of the present invention may include: receiving an active command and a first address; activating a row corresponding to the first address in response to the active command; reading metadata from metadata memory cells of the row in response to the active command and storing the metadata in a metadata buffer; receiving a normal read command and a second address; reading normal read data from memory cells of columns corresponding to the second address in response to the normal read command; and outputting a portion of the normal read data and the metadata stored in the metadata buffer, the portion being selected by the second address, in response to the normal read command.

According to one embodiment of the present invention, a method of operating a memory comprises: receiving an active command and a first address; activating a row corresponding to the first address in response to the active command; reading metadata from metadata memory cells of the row in response to the active command and storing the metadata in a metadata buffer; receiving a normal write command, a second address, normal write data, and write metadata; writing the normal write data in memory cells of columns corresponding to the second address in response to the normal write command; replacing a portion of the metadata of the metadata buffer selected by the second address with the write metadata in response to the normal write command; receiving a precharge command; writing the metadata of the metadata buffer into the metadata memory cells in response to the precharge command; And in response to the precharge command, it may include a step of precharging a row corresponding to the first address.

A memory according to one embodiment of the present invention may include: a memory bank; a metadata buffer for receiving and temporarily storing metadata read from the memory bank during a metadata read operation; and a data input/output circuit for outputting normal data read from the memory bank and a portion of the metadata stored in the metadata buffer during a normal read operation.

According to embodiments of the present invention, metadata can be efficiently stored and accessed in memory.

Figure 1 is a configuration diagram of a memory system (100) according to one embodiment of the present invention.
Figure 2 is a configuration diagram of one embodiment of the memory (150) of Figure 1.
FIG. 3 is a drawing illustrating a first embodiment of the configuration of columns of the cell array (241_0) of FIG. 2.
FIG. 4 is a drawing illustrating a second embodiment of the configuration of columns of the cell array (241_0) of FIG. 2.
FIG. 5 is a drawing illustrating a third embodiment of the configuration of columns of the cell array (241_0) of FIG. 2.
FIG. 6 is a drawing illustrating a fourth embodiment of the configuration of columns of the cell array (241_0) of FIG. 2.
Figure 7 is a flowchart illustrating one embodiment of the operation of the memory (150) of Figure 2.
FIG. 8 is a flowchart illustrating another embodiment of the operation of the memory (150) of FIG. 2.

Hereinafter, embodiments according to the technical idea of the present invention will be described with reference to the attached drawings.

Figure 1 is a configuration diagram of a memory system (100) according to one embodiment of the present invention.

Referring to FIG. 1, a memory system (100) may include a memory controller (110) and memory (150).

The memory controller (110) can control the operation of the memory (150) according to the request of the host (HOST). The host (HOST) may include a central processing unit (CPU), a graphic processing unit (GPU), an application processor (AP), etc. The memory controller (110) may include a host interface (111), a scheduler (113), a command generator (115), and a memory interface (117). The memory controller (110) may be included in a processor such as a CPU, a GPU, an AP, etc., and in this case, the host (HOST) may mean a configuration other than the memory controller (110) in the internal configurations of the processor. For example, if the memory controller (110) is included in the CPU, the host (HOST) in the drawing may represent the remaining configurations of the CPU excluding the memory controller (110).

The host interface (111) may be for an interface between the memory controller (110) and the host (HOST).

The scheduler (113) can determine the order of requests to be instructed to the memory (150) among the requests from the host (HOST). The scheduler (113) can make the order in which the requests are received from the host (HOST) different from the order of operations to be instructed to the memory (150) in order to improve the performance of the memory (150). For example, even if the host (HOST) requests a read operation of the memory (150) first and a write operation later, the order can be adjusted so that the write operation is performed before the read operation.

The command generator (115) can generate commands to be applied to the memory (150) according to the order of operations determined by the scheduler (113).

The memory interface (117) may be for an interface between the memory controller (110) and the memory (150). Commands and addresses (CA) may be transmitted from the memory controller (110) to the memory (150) through the memory interface (117), and data (DATA) may be transmitted/received. In addition to normal data, the data (DATA) may include corresponding meta data. The memory interface (117) is also called a PHY interface.

The memory (150) can perform operations directed by the memory controller (110). The operations directed from the memory controller (110) can include an active operation, a precharge operation, a read operation, a write operation, a refresh operation, a meta data read operation, and a meta data write operation.

Figure 2 is a configuration diagram of one embodiment of the memory (150) of Figure 1.

Referring to FIG. 2, the memory (150) may include a command/address receiving circuit (201), a data input/output circuit (203), a control circuit (210), memory banks (BK0 to BK3), and meta data buffers (220_0 to 220_3).

The command/address receiving circuit (201) can receive a command and address (CA) transmitted from the memory controller (110). The command and address (CA) can include multi-bit signals.

The data input/output circuit (203) can transmit and receive data (DATA) to and from the memory controller (110). The data (DATA) may be multi-bit, and the data (DATA) may include normal data and meta data.

The control circuit (210) can control the overall operation of the memory (150). The control circuit (210) can control the internal configurations of the memory (150) so that the memory (150) can perform operations instructed by the command and address (CA). The operations performed by the memory (150) may include an active operation, a precharge operation, a read operation, a write operation, a refresh operation, a meta data read operation, and a meta data write operation.

Each of the memory banks (BK0 to BK3) may include a cell array (241_0 to 241_3), a row circuit (243_0 to 243_3), and a column circuit (245_0 to 245_3). Although it is exemplified here that the memory (250) includes four memory banks (BK0 to BK3), it will be appreciated that the memory (250) may include a variety of memory banks, such as 16 or 32.

Each of the cell arrays (241_0 to 241_3) may include a plurality of memory cells arranged in a plurality of rows and a plurality of columns.

The row circuits (243_0 to 243_3) can perform an active operation to activate a row selected by a row address among a plurality of rows of the cell arrays (241_0 to 241_3). For example, the row circuit (243_0) can activate a row selected by a row address in the cell array (241_0) during the active operation of the memory bank (BK0), and the row circuit (243_3) can activate a row selected by a row address in the cell array (241_3) during the active operation of the memory bank (BK3). During the active operation, data of the memory cells of the selected row can be sensed and amplified. In addition, the row circuits (243_0 to 243_3) can refresh the memory cells of the selected row so that a refresh operation is performed.

The column circuits (245_0 to 245_3) can write data to memory cells of columns selected by a column address among columns of a row selected by the row circuits (243_0 to 243_3) in the cell arrays (241_0 to 241_3), or read data from memory cells of the selected columns. That is, the column circuits (245_0 to 245_3) can perform an operation of reading or writing data of memory cells corresponding to a row and columns selected in the cell arrays (241_0 to 241_3). For example, the column circuit (245_1) can write data or read data from memory cells of columns selected by a column address in a row selected by the row circuit (243_1) in the cell array (241_1).

Meta data buffers (220_0 to 220_3) may be provided for each of the memory banks (BK0 to BK3). The meta data buffers (220_0 to 220_3) may be used to temporarily store meta data to be read from the memory banks (BK0 to BK3) and transmitted to the memory controller (110), or to temporarily store meta data to be received from the memory controller (110) and written to the memory banks (BK0 to BK3).

FIG. 3 is a diagram illustrating a first embodiment of the configuration of columns of the cell array (241_0) of FIG. 2. Here, it is assumed that 128-bit normal data is read and written and 8-bit meta data is read and written during read and write operations of the memory (150). The cell arrays (241_1 to 241_3) of FIG. 2 can also be configured in the same manner as the cell array (241_0) of FIG. 3.

Referring to FIG. 3, the column select signals (YI<0:63>) may represent signals used to select columns in the cell array (241_0). During a read and write operation, one of the column select signals (YI<0:63>) is activated, and 128 columns corresponding to the activated column select signal can be accessed. For example, when the 123rd row is activated (selected), if the column select signal (YI<37>) is activated, 128 memory cells corresponding to the column select signal (YI<37>) in the 123rd row of the cell array can be accessed.

Columns corresponding to column selection signals (YI<0>, YI<16>, YI<32>, YI<48>) in the cell array (241_0) can be used to store metadata. In the case where 128-bit normal data is read and written and 8-bit metadata is read and written during read and write operations of the memory (150), i.e., where the ratio of normal data:metadata is 128:8, 1/16 of the area of the cell array (241_0) must be allocated for metadata, and therefore, columns corresponding to the column selection signals (YI<0>, YI<16>, YI<32>, YI<48>) are used to store metadata. Columns corresponding to a column selection signal (YI<0>) may store metadata corresponding to normal data stored in columns corresponding to the column selection signals <YI<1:15>, and columns corresponding to a column selection signal (YI<16>) may store metadata corresponding to normal data stored in columns corresponding to the column selection signals (YI<17:31>). Similarly, columns corresponding to a column selection signal (YI<32>) may store metadata corresponding to normal data stored in columns corresponding to the column selection signals <YI<33:47>, and columns corresponding to a column selection signal (YI<48>) may store metadata corresponding to normal data stored in columns corresponding to the column selection signals (YI<49:63>).

FIG. 4 is a diagram illustrating a second embodiment of the configuration of columns of the cell array (241_0) of FIG. 2. Here, it is assumed that 128 bits of normal data are read and written and 2 bits of meta data are read and written during read and write operations of the memory (150). The cell arrays (241_1 to 241_3) of FIG. 2 may also be configured in the same manner as the cell array (241_0) of FIG. 4.

Referring to FIG. 4, the column selection signals (YI<0:63>) may represent signals used to select columns in the cell array (241_0). During a read and write operation, one of the column selection signals (YI<0:63>) is activated, and 128 columns corresponding to the activated column selection signal can be accessed.

Columns corresponding to column selection signals (YI<0>) in the cell array (241_0) can be used to store metadata. When 128-bit normal data is read and written and 2-bit metadata is read and written during read and write operations of the memory (150), i.e., when the ratio of normal data:metadata is 128:2, an area of 1/64 of the cell array (240_1) must be allocated for metadata, and therefore, columns corresponding to the column selection signals (YI<0>) are used to store metadata. Metadata corresponding to normal data stored in columns corresponding to the column selection signals (YI<1:63>) can be stored in the columns corresponding to the column selection signals (YI<0>).

FIG. 5 is a diagram illustrating a third embodiment of the configuration of columns of the cell array (241_0) of FIG. 2. Here, it is assumed that 128-bit normal data is read and written and 8-bit meta data is read and written during read and write operations of the memory (150). The cell arrays (241_1 to 241_3) of FIG. 2 can also be configured in the same manner as the cell array (241_0) of FIG. 5.

Referring to FIG. 5, the cell array (241_0) may additionally be provided with an area accessed by meta column selection signals (M_YI<0:3>) in addition to an area for storing normal data accessed by column selection signals (YI<0:63>). When one of the column selection signals (YI<0:63>) and the meta column selection signals (M_YI<0:3>) is activated, 128 columns corresponding to the activated signal can be accessed.

In the case where 128-bit normal data is read and written and 8-bit meta data is read and written during the read and write operation of the memory (150), that is, when the ratio of normal data:meta data is 128:8, the size of the area for storing the meta data should be 1/16 of the size of the area for storing the normal data, so the number of column selection signals (YI<0:63>) may be 64 and the number of meta column selection signals (M_YI<0:3>) may be 4. Meta data corresponding to normal data stored in the columns corresponding to the column selection signals (YI<0:15>) may be stored in the columns corresponding to the meta column selection signal (M_YI<0>), and meta data corresponding to normal data stored in the columns corresponding to the column selection signals (YI<16:31>) may be stored in the columns corresponding to the meta column selection signal (M_YI<1>). Similarly, metadata corresponding to normal data stored in columns corresponding to column selection signals (YI<32:47>) may be stored in columns corresponding to meta column selection signals (M_YI<2>), and metadata corresponding to normal data stored in columns corresponding to column selection signals (YI<48:63>) may be stored in columns corresponding to meta column selection signals (M_YI<3>).

In the embodiment of Fig. 5, unlike the embodiment of Fig. 3, a separate area for storing metadata is provided, so that the ratio of the area for storing normal data and the area for storing metadata can be distributed exactly at 128:8, and accordingly, waste of the area of the cell array (241_0) can be avoided. However, in the case where only normal data is stored in the cell array (241_0) in the memory system (100) and metadata is not stored, the area for storing metadata may be wasted.

FIG. 6 is a diagram illustrating a fourth embodiment of the configuration of columns of the cell array (241_0) of FIG. 2. Here, it is assumed that 128 bits of normal data are read and written and 2 bits of meta data are read and written when the memory (150) performs read and write operations. The cell arrays (241_1 to 241_3) of FIG. 2 may also be configured in the same manner as the cell array (241_0) of FIG. 6.

Referring to FIG. 5, the cell array (241_0) may additionally be provided with an area accessed by a meta column selection signal (M_YI) in addition to an area for storing normal data accessed by column selection signals (YI<0:63>). When one of the column selection signals (YI<0:63>) and the meta column selection signal (M_YI) is activated, 128 columns corresponding to the activated signal can be accessed.

In the case where 128 bits of normal data are read and written and 2 bits of meta data are read and written during read and write operations of the memory (150), that is, when the ratio of normal data:meta data is 128:8, the size of the area for storing the meta data must be 1/64 of the size of the area for storing the normal data, so the number of column selection signals (YI<0:63>) may be 64 and the number of meta column selection signals (M_YI) may be 1. Meta data corresponding to normal data stored in the columns corresponding to the column selection signals (YI<0:63>) may be stored in the columns corresponding to the meta column selection signals (M_YI).

In the embodiment of Fig. 6, unlike the embodiment of Fig. 4, a separate area for storing metadata is provided, so that the ratio of the area for storing normal data and the area for storing metadata can be distributed exactly at 128:2, and accordingly, waste of the area of the cell array (241_0) can be avoided. However, in the case where only normal data is stored in the cell array (241_0) in the memory system (100) and metadata is not stored, the area for storing metadata may be wasted.

Referring again to FIGS. 2 to 6, we will learn about the various operations of the memory (150).

Active action

An active operation can be initiated by the memory controller (110) applying an active command, a bank address for selecting a memory bank to perform the active operation, and a row address for selecting a row to be activated within the selected memory bank to the memory (150). For example, when an active command, a bank address for designating a memory bank (BK2), and a row address for designating row 100 are applied to the memory (150), the row circuit (243_2) of the memory bank (BK2) can select and activate row 100 of the cell array (241_2). During the active operation, data of memory cells of the selected row of the selected memory bank can be sensed and amplified.

An operation for terminating an active operation is called a precharge operation, and the active operation can be terminated by the memory controller (110) applying a precharge command and a bank address to the memory (150). For example, when the 3rd row of the memory bank (BK3) is active, if a precharge command and a bank address for selecting the memory bank (BK3) are applied, the 3rd row of the memory bank (BK3) can be precharged.

Meta data read operation

The metadata read operation may be an operation of reading metadata of memory cells and storing them in a metadata buffer. In order for the metadata read operation to be performed, the memory bank must be in an active state. For example, when the memory banks (BK1, BK2) in the memory (150) are active, the metadata read operation of the memory banks (BK1, BK2) is possible, but the metadata read operation of the memory banks (BK0, BK3) may not be possible.

A metadata read operation can be initiated by a memory controller (110) applying a metadata read command to a memory (150), a bank address for selecting a memory bank in which the metadata read operation is to be performed, and a column address for selecting columns from which metadata is to be read within the selected memory bank. When the 10th row of the memory bank (BK1) is active, if a metadata read command, a bank address designating the memory bank (BK1), and a column address designating columns in which metadata is stored are applied, 128-bit metadata may be read from memory cells selected by the column address in the 10th row of the memory bank (BK1) and stored in the metadata buffer (220_1). During the metadata read operation, metadata may be read from memory cells selected by the address and stored in the metadata buffer (220_1), and the metadata may not be output to the outside of the memory (150).

Normal read operation

In order to perform a normal read operation, the memory bank must be in an active state. In addition, it may be required that a metadata read operation is performed once before the normal read operation, and metadata corresponding to normal data on which the normal read operation is to be performed may be stored in the metadata buffer. For example, in order to perform a normal read operation of the memory bank (BK2), the memory bank (BK2) must be in an active state, and metadata corresponding to normal data stored in memory cells on which the normal read operation is to be performed in the memory bank (BK2) may already be stored in the metadata buffer (220_2).

A normal read operation can be started by the memory controller (110) applying a normal read command to the memory (150), a bank address for selecting a memory bank in which a normal read operation is to be performed, and a column address for selecting columns from which normal data is to be read within the selected memory bank. When the 10th row of the memory bank (BK1) is activated and the meta data read operation has already been performed, if a normal read command, a bank address designating the memory bank (BK1), and a column address designating columns in which normal data is stored are applied, 128 bits of normal data can be read from memory cells selected by the column address in the 10th row of the memory bank (BK1) and outputted to the outside of the memory. Additionally, among the 128 bits of metadata stored in the metadata buffer (220_1), 8 bits (or 2 bits) of metadata corresponding to 128 bits of normal data can be output to the outside of the memory (150) following the normal data.

During normal read operation, normal data and metadata can be output continuously. For example, 128 (=4*32) bits of normal data can be output continuously with BL (Burst Length)=32 through four data pads of the memory (150), and 8 bits (=4*2) of metadata can be output continuously with BL=2 through four data pads. If the metadata is 2 bits, after 128 bits of normal data are output continuously, 2 bits of metadata can be output with BL=1 through two of the four data pads.

Normal light operation

In order for a normal write operation to be performed, the memory bank must be active. And, as with a normal read operation, a metadata read operation may be required to be performed once before the normal write operation.

A normal write operation can be started by the memory controller (110) sending a normal write command to the memory (150), a bank address for selecting a memory bank in which the normal write operation is to be performed, a column address for selecting columns in which normal data is to be written within the selected memory bank, and normal write data and write meta data. When the 10th row of the memory bank (BK1) is activated and a meta data read operation has already been performed, if a normal write command, a bank address designating the memory bank (BK1), a column address designating columns in which normal data is to be stored, normal write data and write meta data are applied, 128-bit normal data can be written in memory cells selected by the column address in the 10th row of the memory bank (BK1). In addition, 8 bits (or 2 bits) of the 128-bit meta data stored in the meta data buffer (220_1) can be replaced with the write meta data.

The memory (150) can continuously receive normal light data and meta light data during normal light operation. For example, the memory (150) can continuously receive 128 (=4*32) bits of normal light data with BL (Burst Length)=32 through four data pads, and can then continuously receive 8 bits (=4*2) of light meta data with BL=2 through four data pads. If the meta data is 2 bits, after continuously receiving 128 bits of normal light data, 2 bits of meta data with BL=1 can be received through two of the four data pads.

Metadata Light Behavior

A metadata write operation may be an operation of storing metadata stored in a metadata buffer into memory cells. In order for a metadata write operation to be performed, a memory bank must be in an active state, and a metadata read operation may be required to be performed once before the metadata write operation.

A metadata write operation can be started by a memory controller (110) applying a metadata write command, a bank address for selecting a memory bank in which a metadata write operation is to be performed, and a column address for selecting columns in which metadata is to be written within the selected memory bank to a memory (150). When the 10th row of the memory bank (BK1) is activated, if the metadata write command, the bank address designating the memory bank (BK1), and the column address designating the columns in which metadata is to be written are applied, 128-bit metadata stored in the metadata buffer (220_1) can be written to memory cells selected by the column address in the 10th row of the memory bank (BK1). The metadata write operation can be performed on memory cells that are identical to memory cells on which a metadata read operation was previously performed.

FIG. 7 is a flowchart illustrating an embodiment of the operation of the memory (150) of FIG. 2. In FIG. 7, the operation in the case where 128-bit normal data is read and written and 8-bit meta data is read and written during the read and write operation of the memory (150) will be described. That is, in FIG. 7, the operation in the case where the cell array (241_0 to 241_3) is configured as in FIG. 3 or FIG. 5 will be described. It will be assumed that the memory bank (BK2) is selected in all the operations performed in FIG. 7.

Referring to FIG. 7, first, an active operation of a memory (150) can be instructed (701). Specifically, the memory (150) can receive an active command, a bank address, and a row address transmitted from a memory controller (110).

In response to the instruction (701), an active operation can be performed (703) in the memory (150). For example, the 72nd row selected by the row address in the cell array (241_2) of the memory bank (BK2) selected by the bank address can be activated. During the active operation, data of the memory cells of the 72nd row of the cell array (241_2) can be detected and amplified.

A metadata read operation of the memory (150) can be instructed (705). The memory (150) can receive a metadata read command, a bank address, and a column address transmitted from the memory controller (110).

In response to the instruction (705), a metadata read operation can be performed (707) in the memory (150). For example, a memory bank (BK2) is selected by a bank address, and one column selection signal (e.g., YI<16> in the case of FIG. 3, M_YI<1> in the case of FIG. 5) selected by a column address is activated, so that 128 bits of metadata can be read from 128 memory cells corresponding to the column selection signal (YI<16> or M_YI<1>) in the 72nd row of the cell array (241_2) and stored in the metadata buffer (220_2).

A normal read operation of the memory (150) can be instructed (709). The memory (150) can receive a normal read command, a bank address, and a column address transmitted from the memory controller (110).

In response to the instruction (709), a normal read operation of the memory (150) may be performed (711). For example, a memory bank (BK2) selected by a bank address is selected, and one column selection signal (e.g., YI<18>) selected by a column address is activated, so that 128 bits of normal data may be read from 128 memory cells corresponding to the column selection signal (YI<18>) in row 72 of the cell array (241_2) and transmitted to the memory controller (110). In addition, 8 bits of metadata corresponding to the 128 bits of normal data of the column selection signal (YI<18>) among the 128 bits of metadata stored in the metadata buffer (220_2) may be selected and transmitted to the memory controller (110). Among the 128 bits of metadata stored in the metadata buffer (220_2), 8 bits to be transmitted to the memory controller (110) can be selected by a column address. The 128 bits of normal data can be transmitted to the memory controller (110) first, and then the 8 bits of metadata can be transmitted to the memory controller (110).

A normal write operation of the memory (150) can be instructed (713). The memory (150) can receive a normal write command, a bank address, a column address, 128-bit normal write data, and 8-bit write meta data transmitted from the memory controller (110). The memory (150) can first receive the 128-bit normal write data and then immediately receive the 8-bit write meta data.

In response to the instruction (713), a normal write operation of the memory (150) may be performed (715). For example, a memory bank (BK2) is selected by a bank address, and one column selection signal (e.g., YI<20>) selected by a column address is activated, so that 128-bit normal write data may be written to 128 memory cells corresponding to the column selection signal (YI<20>) in row 72 of the cell array (241_2). In addition, 8 bits of the 128-bit metadata stored in the metadata buffer (220_2) may be replaced with the write metadata received in step (713). The 8 bits of the 128-bit metadata stored in the metadata buffer (220_2) to be replaced with the write metadata may be selected by the column address.

A metadata write operation of the memory (150) may be instructed (717). The memory (150) may receive a metadata write command, a bank address, and a column address transmitted from the memory controller (110). Since the metadata write operation must be performed on the same memory cells as the memory cells on which the metadata read operation (705, 707) is performed, the addresses received in step (717) may have the same value as the addresses received in step (705).

In response to the instruction (717), a metadata write operation can be performed (719) in the memory (150). 128 bits of metadata stored in the metadata buffer (220_2) can be written to 128 memory cells selected by the addresses received in step (717).

A precharge operation of the memory (150) can be instructed (721). The memory (150) can receive a precharge command and a bank address transmitted from the memory controller (110).

In response to the instruction (723), a precharge operation can be performed (723) in the memory (150). That is, the active operation of the memory bank (BK2) selected by the bank address can be terminated.

In order for the normal read operation and the normal light operation to be performed, metadata must be stored in the metadata buffer (220_2). Therefore, the metadata read operation must be performed before the normal read operation and the normal light operation are performed.

In addition, since a part of the metadata stored in the metadata buffer (220_2) is changed when the normal write operation is performed, the metadata write operation for updating the changed metadata back into the memory cells must be performed before the precharge operation. For example, if the normal write operation (713, 715) in FIG. 7 is not performed, the metadata write operation (717, 719) does not need to be performed.

FIG. 8 is a flowchart illustrating another embodiment of the operation of the memory (150) of FIG. 2. In FIG. 8, the operation in the case where 128-bit normal data is read and written and 2-bit meta data is read and written during the read and write operation of the memory (150) will be described. That is, in FIG. 8, the operation in the case where the cell array (241_0 to 241_3) is configured as in FIG. 4 or FIG. 6 will be described. It will be assumed that the memory bank (BK2) is selected in all the operations performed in FIG. 8.

Referring to FIG. 8, first, an active operation of a memory (150) can be instructed (801). Specifically, the memory (150) can receive an active command, a bank address, and a row address transmitted from a memory controller (110).

In response to the instruction (801), an active operation can be performed (803) in the memory (150). For example, the 31st row selected by the row address in the cell array (241_2) of the memory bank (BK2) selected by the bank address can be activated. During the active operation, data of the memory cells of the 31st row of the cell array (241_2) can be detected and amplified.

In response to an instruction (801) of an active operation, a metadata read operation can be performed (805). In the case where metadata to be read and written at a time is 2 bits, all metadata of one row are stored in memory cells corresponding to the column select signal (YI<0> in the case of FIG. 4, M_YI in the case of FIG. 6). In addition, since all metadata of one row can be stored in the metadata buffer (220_2), a metadata read operation (which must be performed anyway) can be performed in response to an instruction of an active operation. 128-bit metadata can be read from 128 memory cells corresponding to the column select signal (YI<0> or M_YI) in the 31st row of the cell array (241_2) of the memory bank (BK2) and stored in the metadata buffer (220_2).

A normal read operation of the memory (150) can be instructed (807). The memory (150) can receive a normal read command, a bank address, and a column address transmitted from the memory controller (110).

In response to the instruction (807), a normal read operation of the memory (150) may be performed (809). For example, a memory bank (BK2) selected by a bank address is selected, and one column selection signal (e.g., YI<18>) selected by a column address is activated, so that 128 bits of normal data may be read from 128 memory cells corresponding to the column selection signal (YI<18>) in row 31 of the cell array (241_2) and transmitted to the memory controller (110). In addition, 2 bits of metadata corresponding to the 128 bits of normal data of the column selection signal (YI<18>) among the 128 bits of metadata stored in the metadata buffer (220_2) may be selected and transmitted to the memory controller (110). Among the 128 bits of metadata stored in the metadata buffer (220_2), 2 bits to be transmitted to the memory controller (110) can be selected by a column address. The 128 bits of normal data can be transmitted to the memory controller (110) first, and then the 2 bits of metadata can be transmitted to the memory controller (110).

A normal write operation of the memory (150) can be instructed (811). The memory (150) can receive a normal write command, a bank address, a column address, 128-bit normal write data, and 2-bit write meta data transmitted from the memory controller (110). The memory (150) can first receive the 128-bit normal write data and then immediately receive the 2-bit write meta data.

In response to the instruction (811), a normal write operation of the memory (150) may be performed (813). For example, a memory bank (BK2) is selected by a bank address, and one column selection signal (e.g., YI<20>) selected by a column address is activated, so that 128-bit normal write data may be written to 128 memory cells corresponding to the column selection signal (YI<20>) in row 31 of the cell array (241_2). In addition, 2 bits of the 128-bit metadata stored in the metadata buffer (220_2) may be replaced with the write metadata received in step (811). The 2 bits of the 128-bit metadata stored in the metadata buffer (220_2) to be replaced with the write metadata may be selected by the column address.

A precharge operation of the memory (150) can be instructed (815). The memory (150) can receive a precharge command and a bank address transmitted from the memory controller (110).

In response to the instruction (815), a metadata write operation can be performed (817). The metadata write operation is an operation that must be performed before the precharge operation, and when the metadata to be read and written at one time is 2 bits, the metadata write operation is performed for the memory cells of the column selection signal (YI<0> or M_YI) that has already been determined, so the metadata write operation is performed in response to the instruction. The 128-bit metadata stored in the metadata buffer (220_2) can be stored in 128 memory cells corresponding to the column selection signal (YI<0> or M_YI) in the 31st row of the cell array (241_2).

Subsequently, a precharge operation can be performed (819) in response to the instruction (815). That is, the active operation of the memory bank (BK2) selected by the bank address can be terminated.

In Fig. 8, an active operation and a metadata read operation are performed in response to an active operation instruction, and a metadata write operation and a precharge operation are performed in response to a precharge operation instruction. Accordingly, the number of times a command and an address are applied from a memory controller (110) to a memory (150) can be reduced.

In the above-described embodiments, it has been exemplified that the normal data read and written at one time is 128 bits and the meta data read and written at one time is 8 bits or 2 bits, but this is only an example and it is obvious that the number of bits of the normal data and the number of bits of the meta data may be different.

Although the embodiments according to the technical idea of the present invention have been described with reference to the attached drawings, this is only for explaining the embodiments according to the concept of the present invention, and the present invention is not limited to the embodiments. Various forms of substitution, modification, and change of the embodiments may be made by those skilled in the art without departing from the technical idea of the present invention described in the claims, and this will also be considered to fall within the scope of the present invention.

150: Memory
201: Command/Address Receiving Circuit
203: Data Input/Output Circuit
210: Control circuit
BK0~BK3: Memory banks
220_0~220_3: Metadata buffers

Claims (19)

A step of receiving a metadata read command and a first address;
A step of reading metadata from memory cells of columns corresponding to the first address and storing the metadata in a metadata latch;
Step of receiving a normal read command and a second address;
A step of reading normal read data from memory cells of columns corresponding to the second address; and
A step of outputting the normal read data and a portion of the metadata stored in the metadata buffer.
A method of operating a memory including:
In paragraph 1,
Some of the above metadata are selected by the second address.
How memory works.
In the second paragraph,
Step of receiving a normal light command, a third address, normal light data and light metadata;
A step of writing the normal light data to the memory cells of the columns corresponding to the third address;
A step of replacing some of the metadata of the metadata buffer selected by the third address with the light metadata;
Step of receiving a metadata light command; and
A step of writing metadata of the metadata buffer to memory cells of columns corresponding to the first address.
A method of operating a memory that further includes:
In the third paragraph,
Before the step of receiving the above metadata read command and the first address,
Step of receiving an active command and a fourth address; and
Step of activating the row corresponding to the above fourth address
A method of operating a memory that further includes:
In paragraph 4,
After the step of writing metadata of the above metadata buffer,
a step of receiving a precharge command; and
Step of precharging the row corresponding to the above 4th address
A method of operating a memory that further includes:
A step of receiving a metadata read command and a first address;
A step of reading metadata from memory cells of columns corresponding to the first address and storing the metadata in a metadata buffer;
A step of receiving a normal light command, a second address, normal light data and light metadata;
A step of writing the normal light data to the memory cells of the columns corresponding to the second address;
A step of replacing some of the metadata of the metadata buffer selected by the second address with the light metadata;
Step of receiving a metadata light command; and
A step of writing metadata of the above metadata buffer to memory cells of columns corresponding to the first address.
A method of operating a memory including:
In paragraph 6,
Prior to the step of receiving the above metadata light command,
Step of receiving a normal read command and a third address;
A step of reading normal read data from memory cells of columns corresponding to the third address;
A step of outputting a part of the normal read data and the metadata of the metadata buffer selected by the third address.
A method of operating a memory that further includes:
In Article 7,
Before the step of receiving the above metadata read command and the first address,
Step of receiving an active command and a fourth address; and
Step of activating the row corresponding to the above 4th address
A method of operating a memory that further includes:
In Article 8,
After the step of writing the metadata of the above metadata buffer to the memory cells of the columns corresponding to the first address,
a step of receiving a precharge command; and
Step of precharging the row corresponding to the above 4th address
A method of operating a memory that further includes:
Step of receiving an active command and a first address;
A step of activating a row corresponding to the first address in response to the above active command;
In response to the above active command, a step of reading metadata from the metadata memory cells of the row and storing the metadata in a metadata buffer;
Step of receiving a normal read command and a second address;
A step of reading normal read data from memory cells of columns corresponding to the second address in response to the above normal read command; and
In response to the above normal read command, a step of outputting a part of the normal read data and the metadata stored in the metadata buffer, which is selected by the second address.
A method of operating a memory including:
In Article 10,
After the above outputting step,
a step of receiving a precharge command; and
A step of precharging a row corresponding to the first address in response to the above precharge command.
A method of operating a memory that further includes:
In Article 10,
After the above outputting step,
Step of receiving a normal light command, a third address, normal light data and light metadata;
In response to the above normal write command, a step of writing the normal write data to the memory cells of the columns corresponding to the third address; and
In response to the above normal light command, a step of replacing some of the metadata of the above metadata buffer selected by the third address with the light metadata.
A method of operating a memory that further includes:
In Article 12,
After the above replacing step,
Step of receiving a precharge command;
In response to the precharge command, a step of writing metadata of the metadata buffer into the metadata memory cells; and
A step of precharging a row corresponding to the first address in response to the above precharge command.
A method of operating a memory that further includes:
Step of receiving an active command and a first address;
A step of activating a row corresponding to the first address in response to the above active command;
In response to the above active command, a step of reading metadata from the metadata memory cells of the row and storing the metadata in a metadata buffer;
A step of receiving a normal light command, a second address, normal light data and light metadata;
A step of writing the normal light data into memory cells of columns corresponding to the second address in response to the normal light command;
In response to the above normal light command, a step of replacing a portion of the metadata of the metadata buffer selected by the second address with the light metadata;
Step of receiving a precharge command;
In response to the precharge command, a step of writing metadata of the metadata buffer into the metadata memory cells; and
In response to the above precharge command, a step of precharging a row corresponding to the first address
A method of operating a memory including:
memory bank;
A metadata buffer that temporarily stores metadata read from the memory bank during a metadata read operation; and
A data input/output circuit that outputs normal data read from the memory bank and a portion of the metadata stored in the metadata buffer during normal read operation.
Memory containing .
In Article 15,
When normal light operation is in progress,
The above data input/output circuit receives normal light data and light metadata,
The above metadata buffer replaces some of the stored metadata with the light metadata,
The above memory bank stores the above normal light data.
Memory.
In Article 16,
When metadata light is in operation,
The metadata stored in the above metadata buffer is transferred to the above memory bank and stored.
Memory.
In Article 15,
The above memory
Containing a plurality of the above memory banks,
Containing the same number of metadata buffers as the memory banks;
Memory.
In Article 18,
Each of the above metadata buffers
Temporarily stores metadata of the memory bank corresponding to itself among the above memory banks.
Memory.

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