KR20240144705A - Display apparatus - Google Patents

Abstract

The present invention provides a display device having an expanded display area, comprising: a substrate including a display area and a peripheral area including a first peripheral area having a first bending area and a second peripheral area having a second bending area; pixels arranged on the display area and including display elements; a data driving circuit arranged in the first peripheral area; a gate driving circuit arranged in the second peripheral area; a data line connected to the data driving circuit and the pixels; a gate line connected to the gate driving circuit and the pixels; and gate connection wiring having one side connected to the gate driving circuit and the other side connected to the gate line; wherein the first peripheral area and the second peripheral area face each other with the display area interposed therebetween.

Description

Display apparatus {Display apparatus}

Embodiments of the present invention relate to a display device having an expanded display area for displaying an image.

A display device is a device that visually displays data. The display device includes a substrate divided into a display area and a peripheral area outside the display area. In the display area, scan lines and data lines are formed to be mutually insulated from each other, and a plurality of pixels connected to the scan lines and the data lines are arranged. In addition, the display area is provided with a transistor and a pixel electrode electrically connected to the transistor corresponding to each of the pixels. In addition, the display area is provided with a counter electrode that is commonly provided for the pixels. The peripheral area may include various wires, a scan driver, a data driver, a control driver, etc. that transmit electrical signals to the display area.

These display devices are becoming increasingly diverse in their uses. Accordingly, research is being actively conducted on ways to reduce or efficiently utilize the peripheral area of the display device.

Embodiments of the present invention seek to provide a display device having a reduced peripheral area and excellent display quality. However, these tasks are exemplary and the scope of the present invention is not limited thereby.

According to one aspect of the present invention, a display device is provided, comprising: a substrate including a peripheral region including a first peripheral region having a first bending region and a second peripheral region having a second bending region; a pixel arranged on the display region and including a display element; a data driving circuit arranged in the first peripheral region; a gate driving circuit arranged in the second peripheral region; a data line connected to the data driving circuit and the pixel; a gate line connected to the gate driving circuit and the pixel; and a gate connection wiring having one side connected to the gate driving circuit and the other side connected to the gate line; wherein the first peripheral region and the second peripheral region face each other with the display region interposed therebetween.

In one example, the gate connection wiring may overlap the display area.

According to one example, the display circuit board may be attached to the first peripheral area or the second peripheral area.

According to one example, the gate line may extend in a first direction, and the data line and the gate connection wiring may extend in a second direction intersecting the first direction.

According to one example, the first bending region may be located between the display region and the data driving circuit, and the second bending region may be located between the display region and the gate driving circuit.

According to one example, the internal gate driving circuit may further be disposed in the display area.

According to one example, the internal gate driving circuit may be provided to transmit a light emission control signal to the pixel.

According to one example, the substrate may further include a first insulating layer having a groove disposed on a first peripheral area and surrounding the data driving circuit; and a second insulating layer at least partially embedded in the groove.

According to one example, the substrate may further include a first insulating layer having a groove disposed in a second peripheral region and surrounding the gate driving circuit; and a second insulating layer at least partially embedded in the groove.

According to one example, the display area includes a first display area and a second display area at least partially surrounded by the first display area, and the gate driving circuit can be arranged to at least partially surround a portion of the second peripheral area that overlaps the second display area when viewed in a direction perpendicular to the substrate.

According to another aspect of the present invention, a display device is provided, comprising: a substrate including a first peripheral region including a first bending region, a peripheral region including a second peripheral region facing the first peripheral region, and a display region disposed between the first peripheral region and the second peripheral region; a pixel arranged on the display region and including a display element; a data driving circuit disposed in the first peripheral region; a gate driving circuit disposed in the second peripheral region; a gate line connected to the gate driving circuit, extending in a first direction and connected to the pixel; and a data line connected to the data driving circuit, extending in a second direction intersecting the first direction and connected to the pixel.

In one example, the second peripheral region may include a second bending region facing the first bending region in the second direction.

According to one example, the first bending region may be located between the display region and the data driving circuit, and the second bending region may be located between the display region and the gate driving circuit.

According to one example, the method may further include a gate connection wiring extending in the second direction, one end of which is connected to the gate driving circuit and the other end of which is connected to the gate line.

According to one example, the display circuit board may further be attached to the first peripheral area or the second peripheral area.

According to one example, the display area may further include internal gate driving circuits arranged along the second direction.

According to one example, the device may further include a first insulating layer disposed on the substrate and having a groove surrounding each of the gate driving circuits or each of the data driving circuits.

In one embodiment, the second insulating layer may further include at least a portion of the second insulating layer embedded in the groove.

According to one example, the display area may further include a first display area and a second display area at least partially surrounded by the first display area, and may further include a component arranged to correspond to the second display area at a lower portion of the substrate.

In one example, the gate driving circuit may be arranged to at least partially surround a portion of the second peripheral region corresponding to the component when viewed in a direction perpendicular to the substrate.

Other aspects, features and advantages other than those described above will become apparent from the following detailed description, claims and drawings for practicing the invention.

These general and specific aspects can be implemented using any system, method, computer program, or combination of any systems, methods, and computer programs.

According to one embodiment of the present invention, a device having an expanded display area can be implemented. Of course, the scope of the present invention is not limited by such effects.

FIG. 1 is a perspective view schematically illustrating a display device according to one embodiment of the present invention.
FIG. 2 is a plan view schematically illustrating a display device according to one embodiment of the present invention.
Figure 3a is an enlarged plan view of a portion of Figure 2.
FIG. 3b is an exemplary cross-sectional view of the data line and pixel circuit of FIG. 3a taken along line II'.
FIGS. 4A and 4B are equivalent circuit diagrams schematically illustrating a pixel circuit that can be applied to a display device according to one embodiment of the present invention.
FIG. 5 is a schematic plan view of a display device according to one embodiment of the present invention.
FIG. 6A is a perspective view schematically illustrating a display device according to one embodiment of the present invention.
FIG. 6b is a cross-sectional view schematically illustrating a display device according to one embodiment of the present invention.
FIG. 6c is a schematic plan view of a display device according to one embodiment of the present invention.
FIG. 6d is a cross-sectional view schematically illustrating a display device according to one embodiment of the present invention.
FIG. 7 is a cross-sectional view schematically illustrating a display device according to one embodiment of the present invention.

The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention and the methods for achieving them will become clear with reference to the embodiments described in detail below together with the drawings. However, the present invention is not limited to the embodiments disclosed below, and can be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same drawing reference numerals and redundant descriptions thereof are omitted.

In the examples below, the terms first, second, etc. are not used in a limiting sense but are used for the purpose of distinguishing one component from another.

In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

In the following examples, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not exclude in advance the possibility that one or more other features or components may be added.

In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only the case where it is directly on top of the other part, but also the case where another film, region, component, etc. is interposed in between.

In the drawings, the sizes of components may be exaggerated or reduced for convenience of explanation. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily shown for convenience of explanation, and therefore the present invention is not necessarily limited to what is shown.

In some embodiments, where the embodiments are otherwise feasible, a particular process sequence may be performed in a different order than the order described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the order described.

In this specification, "A and/or B" refers to either A, or B, or both A and B. In addition, "at least one of A and B" refers to either A, or B, or both A and B.

In the following examples, when it is said that a film, a region, a component, etc. are connected, it includes cases where the films, regions, and components are directly connected, and/or cases where other films, regions, and components are interposed between the films, regions, and components and are indirectly connected. For example, when it is said in this specification that a film, a region, and a component, etc. are electrically connected, it refers to cases where the films, regions, and components, etc. are directly electrically connected, and/or cases where other films, regions, and components are interposed between them and are indirectly electrically connected.

The x-axis, y-axis, and z-axis are not limited to the three axes on the orthogonal coordinate system, and can be interpreted in a broad sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they can also refer to different directions that are not orthogonal to each other.

Fig. 1 is a perspective view schematically illustrating a display device (1) according to one embodiment of the present invention, and Fig. 2 is a plan view schematically illustrating a display device according to one embodiment of the present invention. Fig. 3a is an enlarged plan view of a portion (AR1) of Fig. 2, and Fig. 3b is an exemplary cross-sectional view of the data line and pixel circuit of Fig. 3a taken along line I-I'.

Referring to FIG. 1, a display device (1) is a device that displays a moving image or still image, and can be used as a display screen for various products such as portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), and the like, as well as a television, a laptop, a monitor, a billboard, and the Internet of Things (IOT).

The display device (1) can be used in wearable devices such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). In addition, the display device (1) can be used as a CID (Center Information Display) placed on an automobile instrument panel, a center fascia or dashboard of an automobile, a room mirror display replacing a side mirror of an automobile, and a display placed on the back of a front seat as entertainment for the rear seats of an automobile.

The display device (1) may have a short side in a first direction and a long side in a second direction. Here, the first direction and the second direction may be directions that intersect each other. For example, the first direction and the second direction may form an acute angle with each other. As another example, the first direction and the second direction may form an obtuse angle or a right angle with each other. Hereinafter, a detailed description will be given focusing on a case where the first direction (e.g., x direction) and the second direction (e.g., y direction) form a right angle with each other.

As another example, the display device (1) may have a side length in a first direction (e.g., x direction) and a side length in a second direction (e.g., y direction) that are equal. As another example, the display device (1) may have a long side in a first direction (e.g., x direction) and a short side in a second direction (e.g., y direction).

The corner where the short side in the first direction (e.g., the x direction) and the long side in the second direction (e.g., the y direction) meet can be formed to be rounded so as to have a predetermined curvature.

Fig. 2 is a plan view schematically illustrating a display device (1) according to one embodiment of the present invention. Fig. 2 is a plan view illustrating a shape of a side area (e.g., a bending area) of the display device (1) before it is bent. That is, it is a plan view in a state where the first bending area (BA1) and the second bending area (BA2) of the display device (1) are each unbent.

The display device (1) may include a display element. For example, the display device (1) may include one of an organic light-emitting display panel using an organic light-emitting diode including an organic light-emitting layer, an ultra-small light-emitting diode display panel using a micro LED, a quantum dot light-emitting display panel using a quantum dot light-emitting element including a quantum dot light-emitting layer, and an inorganic light-emitting display panel using an inorganic light-emitting element including an inorganic semiconductor. Hereinafter, a detailed description will be given focusing on a case where the display device (1) is an organic light-emitting display device using an organic light-emitting diode as a display element.

Referring to FIG. 2, the display device (1) may include a display area (DA) and a peripheral area (PA). The display area (DA) is an area where a plurality of pixels (PX) display an image, and the peripheral area (PA) may surround at least a portion of the display area (DA).

The display device (1) may include a substrate (100) and a multilayer film disposed on the substrate (100). At this time, a display area (DA) and a peripheral area (PA) may be defined on the substrate (100) and/or the multilayer film. That is, it may be said that the substrate (100) and/or the multilayer film include a display area (DA) and a peripheral area (PA).

Each pixel (PX) may include subpixels, and each subpixel may emit light of a predetermined color using an organic light-emitting diode as a display element. Each organic light-emitting diode may emit light of, for example, red, green, or blue. Each organic light-emitting diode may be connected to a pixel circuit including a thin film transistor and a storage capacitor.

The peripheral area (PA) may be a non-display area that does not provide an image. The peripheral area (PA) may include a first peripheral area (PA1), a second peripheral area (PA2), a third peripheral area (PA3), and a fourth peripheral area (PA4) divided based on the display area (DA).

In one embodiment, the first peripheral area (PA1) may be an area located approximately at the lower end of the display area (DA). The second peripheral area (PA2) may be an area located approximately at the upper end of the display area (DA). The third peripheral area (PA3) may be an area located approximately at the left end of the display area. The fourth display area (PA4) may be an area located approximately at the right end of the display area. The first peripheral area (PA1) and the second peripheral area (PA2) may face each other in a second direction (e.g., the y direction), and the third peripheral area (PA3) and the fourth peripheral area (PA4) may face each other in a first direction (e.g., the x direction).

The peripheral area (PA) may include a bending area (BA). The bending area (BA) may include a first bending area (BA1) and a second bending area (BA2).

The first bending area (BA1) may be arranged in a peripheral area (PA) extending in a second direction (e.g., in the -y direction) from a lower end of the display area (DA). For example, the first bending area (BA1) may be arranged in the first peripheral area (PA). The second bending area (BA2) may be arranged in a peripheral area (PA) extending in a second direction (e.g., in the y direction) from an upper end of the display area (DA). The second bending area (BA2) may be arranged in the second peripheral area (PA2). When looking at the front of the display device (1) in a state where the bending area (BA) is bent, a part of the peripheral area (PA) may not be visible to the user.

A driving circuit (DC) for providing an electrical signal to each pixel (PX) through a signal line, a voltage wire for providing a voltage, etc. may be placed in the peripheral area (PA). The driving circuit (DC) may include a data driving circuit (DDC) and a gate driving circuit (GDC).

The data driving circuit (DDC) may be placed on one side of the peripheral area (PA). As illustrated in FIG. 2, the data driving circuit (DDC) may be placed in the peripheral area (PA) corresponding to the lower portion of the display device (1). The data driving circuit (DDC) may be placed in the first peripheral area (PA1).

A data driving circuit (DDC) can provide a data signal to each pixel (PX) through a data line (DL). The data line (DL) can extend in a second direction (e.g., in the y direction) and be connected to pixels (PX) located in the same column.

A data line (DL) can be connected to a data driving circuit (DDC) via a data connection line (DCL). One end of the data connection line (DCL) can be connected to the data driving circuit (DDC), and the other end can be connected to the data line (DL). The data connection line (DCL) can be arranged in a peripheral area (PA). For example, the data connection line (DCL) can be arranged corresponding to a first peripheral area (PA1).

A gate driving circuit (GDC) can transmit a gate signal to each pixel (PX) through a gate line (GL). The gate line (GL) can extend in a first direction (e.g., an x direction) and be connected to pixels (PX) positioned in the same row. The gate line (GL) can include a scan line (SL) and an emission control line (EL), and the gate signal can include a scan signal and an emission control signal. The gate driving circuit (GDC) can include a scan driving circuit and can transmit a scan signal to each pixel (PX) through the scan line (SL). In addition, the gate driving circuit (GDC) can also include an emission control driving circuit and can provide an emission control signal to each pixel (PX) through the emission control line (EL).

The gate driving circuit (GDC) may be arranged on one side of the peripheral area (PA). The gate driving circuit (GDC) may be arranged on the opposite side of the data driving circuit (DDC). As illustrated in FIG. 2, the gate driving circuit (GDC) may be arranged in the peripheral area (PA) corresponding to the upper portion of the display device (1). The gate driving circuit (GDC) may be arranged in the second peripheral area (PA2).

A gate line (GL) can be connected to a gate driving circuit (GDC) through a gate connection wiring (GCL). The gate connection wiring (GCL) can extend in a second direction (e.g., a y direction) intersecting a first direction (e.g., an x direction), and one side can be connected to the gate driving circuit (GDC) and the other side can be connected to the gate line (GL). The gate driving circuit (GDC) can transmit a gate signal to each pixel (PX) through the gate connection wiring (GCL) and the gate line (GL). The gate connection wiring (GCL) can overlap a display area (DA).

According to one embodiment of the present invention, the data driving circuit (DDC) and the gate driving circuit (GDC) may be respectively disposed on different sides of the peripheral area (PA). The data driving circuit (DDC) and the gate driving circuit (GDC) may face each other with the display area (DA) therebetween. As illustrated in FIG. 2, the data driving circuit (DDC) may be disposed in the first peripheral area (PA1), and the gate driving circuit (GDC) may be disposed in the second peripheral area (PA2).

As Comparative Example 1, the data driving circuit may be arranged at the lower end of the display device, and the gate driving circuit may be arranged at the left side and/or the right side of the display device. In this case, depending on the arrangement of the gate driving circuit, a dead space area at the left side and/or the right side of the display device may increase.

As a comparative example 2, the gate driving circuit may be arranged on one side of the peripheral area together with the data driving circuit. For example, both the data driving circuit and the gate driving circuit may be arranged at the bottom of the display device. In this case, since the wires for transmitting various signals from the driving circuit to the display area are concentrated and arranged at the bottom, the difficulty of the wiring design may increase or interference may occur between the wires. In particular, as the pixel circuit becomes more complex to implement a high-resolution display device, the number of required wires may increase, which may cause difficulty in the wiring design.

In contrast, according to one embodiment of the present invention, the data driving circuit (DDC) may be arranged at the lower end of the display device (1), and the gate driving circuit (GDC) may be arranged at the upper end of the display device (1). Accordingly, the dead space area of the left and right sides of the display device (1) may be reduced. As described above, since the second bending area (BA2) located at the upper end of the display device (1) may be bent, when looking at the front of the display device (1), a part of the second peripheral area (PA2) for arranging the gate driving circuit (GDC) may not be visible to the user.

In addition, since the data driving circuit (DDC) and the gate driving circuit (GDC) are arranged facing each other with the display area (DA) between them, the concentration of wires is reduced compared to when the gate driving circuit (GDC) is arranged on one side of the display device (1) together with the data driving circuit (DDC), making wiring design easier.

Referring back to FIG. 2, the peripheral area (PA) may include a pad portion (not shown), which is an area to which electronic components or printed circuit boards may be electrically connected. The pad portion may be exposed without being covered by an insulating layer, and may be electrically connected to a display circuit board (30). The display circuit board (30) may be a flexible printed circuit board. The display circuit board (30) may electrically connect a controller and the pad portion, and supply a signal or power transmitted from the controller. The display circuit board (30) may be disposed in the first peripheral area (PA1) and/or the second peripheral area (PA2) of the display device (1). In some embodiments, a gate driving circuit (GDC) and/or a data driving circuit (DDC) may be disposed in the display circuit board (30).

Referring to FIG. 3a, some of a plurality of pixel circuits (PC) arranged in a row direction (x direction) and a column direction (y direction) are illustrated. Each of a scan line (SL) and a light emitting control line (EL) may extend in a first direction (e.g., x direction), and a data line (DL) may extend in a second direction (e.g., y direction). A gate connection wiring (GCL) connecting the scan line (SL) and the light emitting control line (EL) to a gate driving circuit (GDC) may extend in the second direction (e.g., y direction). The gate connection wiring (GCL) may extend in the same direction as the data line (DL).

In one embodiment, as illustrated in FIG. 3a, the number of gate connection wirings (GCLs) overlapping one pixel circuit (PC) may be one. Pixel circuits (PCs) arranged in the same column may overlap the same gate connection wirings (GCLs). As another example, the number of gate connection wirings (GCLs) overlapping one pixel circuit (PC) may be two or more. That is, pixel circuits (PCs) arranged in the same column may overlap two or more gate connection wirings (GCLs).

In one embodiment, the gate connection wiring (GCL) may be arranged in a different layer from the scan line (SL) and the emission control line (EL). Referring to FIG. 3b, an insulating layer, such as a first gate insulating layer (112) and a second gate insulating layer (113), may be arranged between the gate connection wiring (GCL), the scan line (SL), and the emission control line (EL). In this case, the gate connection wiring (GCL), the scan line (SL), and the emission control line (EL) may be connected through a contact hole (CNT) formed in the first gate insulating layer (112) and the second gate insulating layer (113).

In FIG. 3b, the gate connection wiring (GCL) is illustrated as being disposed on the second gate insulating layer (113), but as another example, the gate connection wiring (GCL) may be disposed on the first gate insulating layer (112). A first gate insulating layer (112) may be interposed between the gate connection wiring (GCL) and the scan line (SL) and the emission control line (EL).

A contact hole (CNT) connecting a scan line (SL) and/or an emission control line (EL) and a gate connection wiring (GCL) may be formed in at least one pixel circuit (PC) among the pixel circuits (PC) arranged in the same row. For example, among a plurality of pixel circuits (PC) arranged in the same row, there may be two or more pixel circuits (PC) connected to the gate connection wiring (GCL) through the contact hole (CNT).

In one embodiment, the gate connection wiring (GCL) may be arranged on the same layer as the data line (DL). Referring to FIG. 3b, the gate connection wiring (GCL) and the data line (DL) may be arranged on the interlayer insulating layer (114).

Hereinafter, a multilayer film laminated on a display device will be described in detail with reference to FIG. 3b.

Referring to FIG. 3b, the display device may include a substrate (100), a buffer layer (R), a pixel circuit layer (PCL), a display element layer (DEL), and a thin film encapsulation layer (TFE).

The substrate (100) may be glass or may include a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate. The substrate (100) including the polymer resin may have flexible, rollable, and bendable characteristics. The substrate (100) may have a multilayer structure including a base layer including the aforementioned polymer resin and a barrier layer (not shown).

The buffer layer (111) may include an inorganic insulator such as silicon nitride, silicon oxynitride, and silicon oxide, and may be a single layer or multilayer including the aforementioned inorganic insulator.

A pixel circuit layer (PCL) may be disposed on a buffer layer (111). The pixel circuit layer (PCL) may include an inorganic insulating layer (IIL), a first planarization layer (115), and a second planarization layer (116) disposed below and/or above a thin film transistor (TFT) and components of the thin film transistor (TFT) included in the pixel circuit (PC). The inorganic insulating layer (IIL) may include a first gate insulating layer (112), a second gate insulating layer (113), and an interlayer insulating layer (114).

A thin film transistor (TFT) includes a semiconductor layer (A), and the semiconductor layer (A) may include polysilicon. Alternatively, the semiconductor layer (A) may include amorphous silicon, an oxide semiconductor, an organic semiconductor, or the like. The semiconductor layer (A) may include a channel region and a drain region and a source region respectively disposed on both sides of the channel region. A gate electrode (G) may overlap the channel region.

The gate electrode (G) may include a low-resistance metal material. The gate electrode (G) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above materials. In one embodiment, the scan line (SL) and the emission control line (EL) may be arranged on the same layer as the gate electrode (G). The scan line (SL) and the emission control line (EL) may be arranged on the first gate insulating layer (112).

The first gate insulating layer (112) between the semiconductor layer (A) and the gate electrode (G) may include an inorganic insulating material such as silicon oxide (SiO ₂ ), silicon nitride (SiN _X ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ).

The second gate insulating layer (113) may be provided to cover the gate electrode (G). The second gate insulating layer (113), similar to the first gate insulating layer (112), may include an inorganic insulating material such as silicon oxide (SiO ₂ ), silicon nitride (SiN _X ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ).

An upper electrode (CE2) of a storage capacitor (Cst) may be arranged on the second gate insulating layer (113). The upper electrode (CE2) may overlap the gate electrode (G) therebelow. At this time, the gate electrode (G) and the upper electrode (CE2) overlapping with the second gate insulating layer (113) therebetween may form a storage capacitor (Cst) of a pixel circuit (PC). That is, the gate electrode (G) may function as a lower electrode (CE1) of the storage capacitor (Cst). In this way, the storage capacitor (Cst) and the thin film transistor (TFT) may be formed to overlap each other. In some embodiments, the storage capacitor (Cst) may be formed so as not to overlap the thin film transistor (TFT).

The upper electrode (CE2) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu), and may be a single layer or multiple layers of the aforementioned materials.

The interlayer insulating layer (114) may cover the upper electrode (CE2). The interlayer insulating layer (114) may include silicon oxide (SiO ₂ ), silicon nitride (SiN _X ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ). The interlayer insulating layer (114) may be a single layer or multiple layers including the above-described inorganic insulator.

The data line (DL), the gate connection wiring (GCL), the drain electrode (D), and the source electrode (S) may each be positioned on the interlayer insulating layer (114). The data line (DL), the gate connection wiring (GCL), the drain electrode (D), and the source electrode (S) may include a material having good conductivity. The data line (DL), the gate connection wiring (GCL), the drain electrode (D), and the source electrode (S) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above-mentioned materials. In one embodiment, the data line (DL), the gate connection wiring (GCL), the drain electrode (D), and the source electrode (S) may have a multilayer structure of Ti/Al/Ti.

The first planarization layer (115) may be arranged to cover the data line (DL), the gate connection wiring (GCL), the drain electrode (D), and the source electrode (S). The first planarization layer (115) may include an organic insulating layer. The first planarization layer (115) may include an organic insulating material, such as a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, and a blend thereof.

The connection electrode (CML) may be arranged on the first planarization layer (115). At this time, the connection electrode (CML) may be connected to the drain electrode (D) or the source electrode (S) through the contact hole of the first planarization layer (115). The connection electrode (CML) may include a material having good conductivity. The connection electrode (CML) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed as a multilayer or single layer including the above materials. In one embodiment, the connection electrode (CML) and the second data connection wiring (DCL2) may have a multilayer structure of Ti/Al/Ti.

The second planarization layer (116) may be arranged to cover the connecting electrode (CML). The second planarization layer (116) may include an organic insulating layer. The second planarization layer (116) may include an organic insulating material, such as a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, and a blend thereof.

A display element layer (DEL) may be arranged on a pixel circuit layer (PCL). The display element layer (DEL) may include a first display element (DE1). The first display element (DE1) may be an organic light emitting diode (OLED). A pixel electrode (211) of the first display element (DE1) may be electrically connected to a connection electrode (CML) through a contact hole of a second planarization layer (116).

The pixel electrode (211) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ : indium oxide), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the pixel electrode (211) may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In yet another embodiment, the pixel electrode (211) may further include a film formed of ITO, IZO, ZnO, or In ₂ O ₃ on/under the aforementioned reflective film.

A pixel defining film (118) having an opening (118OP) exposing a central portion of the pixel electrode (211) may be arranged on the pixel electrode (211). The pixel defining film (118) may include an organic insulating material and/or an inorganic insulating material. The opening (118OP) may define an emission area (hereinafter, referred to as an emission area) (EA1) of light emitted from the first display element (DE1). For example, the width of the opening (118OP) may correspond to the width of the emission area (EA1) of the first display element (DE1).

A spacer (119) may be placed on the pixel defining film (118). The spacer (119) may be used to prevent damage to the substrate (100) in a manufacturing method for manufacturing a display device. When manufacturing a display panel, a mask sheet may be used. At this time, when the mask sheet enters the opening (118OP) of the pixel defining film (118) or adheres closely to the pixel defining film (118) to deposit a deposition material on the substrate (100), a defect in which a part of the substrate (100) is damaged or destroyed by the mask sheet may be prevented.

The spacer (119) may include an organic insulator such as polyimide. Alternatively, the spacer (119) may include an inorganic insulator such as silicon nitride or silicon oxide, or may include an organic insulator and an inorganic insulator.

In one embodiment, the spacer (119) may include a different material from the pixel defining film (118). Or, in another embodiment, the spacer (119) may include the same material as the pixel defining film (118), in which case the pixel defining film (118) and the spacer (119) may be formed together in a mask process using a halftone mask or the like.

An intermediate layer (212) may be arranged on the pixel defining film (118). The intermediate layer (212) may include a light-emitting layer (212b) arranged in an opening (118OP) of the pixel defining film (118). The light-emitting layer (212b) may include a polymer or low-molecular organic material that emits light of a predetermined color.

A first functional layer (212a) and a second functional layer (212c) may be arranged above and below the light-emitting layer (212b), respectively. The first functional layer (212a) may include, for example, a hole transport layer (HTL) or a hole transport layer and a hole injection layer (HIL). The second functional layer (212c) is a component arranged on the light-emitting layer (212b) and may be optional. The second functional layer (212c) may include an electron transport layer (ETL) and/or an electron injection layer (EIL). The first functional layer (212a) and/or the second functional layer (212c) may be a common layer formed to entirely cover the substrate (100), similar to the counter electrode (213) described below.

The counter electrode (213) may be formed of a conductive material having a low work function. For example, the counter electrode (213) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode (213) may further include a layer such as ITO, IZO, ZnO, or In ₂ O ₃ on the (semi-)transparent layer including the aforementioned material.

In some embodiments, a capping layer (not shown) may be further disposed on the counter electrode (213). The capping layer may include LiF, an inorganic material, or/and an organic material.

A thin film encapsulation layer (TFE) may be disposed on the counter electrode (213). In one embodiment, the thin film encapsulation layer (TFE) includes at least one inorganic encapsulation layer and at least one organic encapsulation layer, and FIG. 3c illustrates that the thin film encapsulation layer (TFE) includes a first inorganic encapsulation layer (310), an organic encapsulation layer (320), and a second inorganic encapsulation layer (330) that are sequentially laminated.

The first inorganic sealing layer (310) and the second inorganic sealing layer (330) may include one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic sealing layer (320) may include a polymer-based material. The polymer-based material may include an acrylic resin, an epoxy resin, polyimide, and polyethylene. As an example, the organic sealing layer (320) may include an acrylate.

/2 위상지연자 및/또는

/4 위상지연자를 포함할 수 있다. 편광자 역시 필름타입 또는 액정 코팅타입일 수 있다. 필름타입은 연신형 합성수지 필름을 포함하고, 액정 코팅타입은 소정의 배열로 배열된 액정들을 포함할 수 있다. 위상지연자 및 편광자는 보호필름을 더 포함할 수 있다.A touch electrode layer may be disposed on a thin film encapsulation layer (TFE), although not shown, and an optical function layer may be disposed on the touch electrode layer. The touch electrode layer may obtain coordinate information according to an external input, for example, a touch event. The optical function layer may reduce the reflectivity of light (external light) incident from the outside toward the display device, and/or may improve the color purity of light emitted from the display device. In one embodiment, the optical function layer may include a phase retarder and/or a polarizer. The phase retarder may be a film type or a liquid crystal coating type,

/2 phase delayer and/or

/4 phase retarders may be included. The polarizer may also be a film type or a liquid crystal coating type. The film type may include a stretchable synthetic resin film, and the liquid crystal coating type may include liquid crystals arranged in a predetermined array. The phase retarder and the polarizer may further include a protective film.

In another embodiment, the optical function layer may include a black matrix and color filters. The color filters may be arranged in consideration of the color of light emitted from each pixel of the display device. Each of the color filters may include a red, green, or blue pigment or dye. Alternatively, each of the color filters may further include quantum dots in addition to the aforementioned pigments or dyes. Alternatively, some of the color filters may not include the aforementioned pigments or dyes and may include scattering particles such as titanium oxide.

In another embodiment, the optical functional layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, may destructively interfere, thereby reducing the external light reflectance.

An adhesive member may be placed between the touch electrode layer and the optical function layer. The adhesive member may be any one known in the art without limitation. The adhesive member may be a pressure sensitive adhesive (PSA).

FIGS. 4A and 4B are equivalent circuit diagrams schematically illustrating a pixel circuit that can be applied to a display device according to one embodiment of the present invention.

Referring to FIG. 4a, a pixel circuit (PC) may be connected to a scan line (SL), a data line (DL), and a display element (DE). The display element (DE) may be an organic light emitting diode (OLED).

The pixel circuit (PC) may include a driving thin film transistor (T1), a scan thin film transistor (T2), and a storage capacitor (Cst). The scan thin film transistor (T2) is connected to a scan line (SL) and a data line (DL), and transmits a data voltage (Dm) input through a data line (DL) to the driving thin film transistor (T1) according to a scan signal (Sn) input through the scan line (SL).

The storage capacitor (Cst) is connected to the scan thin film transistor (T2) and the driving voltage line (PL), and stores a voltage corresponding to the difference between the voltage received from the scan thin film transistor (T2) and the driving voltage (ELVDD) supplied to the driving voltage line (PL).

The driving thin film transistor (T1) is connected to the driving voltage line (PL) and the storage capacitor (Cst), and can control the driving current flowing through the organic light emitting diode (OLED) from the driving voltage line (PL) in response to the voltage value stored in the storage capacitor (Cst). The organic light emitting diode (OLED) can emit light having a predetermined brightness by the driving current.

In FIG. 4a, the case where the pixel circuit (PC) includes two thin film transistors and one storage capacitor is described, but the present invention is not limited thereto. For example, the pixel circuit (PC) may include three or more thin film transistors and/or two or more storage capacitors. In one embodiment, the pixel circuit (PC) may include seven thin film transistors and one storage capacitor.

Referring to FIG. 4b, the pixel circuit (PC) may be connected to a scan line (SL), a data line (DL), and a display element (DE). The display element (DE) may be an organic light emitting diode (OLED).

For example, the pixel circuit (PC) includes first to seventh thin film transistors (T1 to T7) and a storage capacitor (Cst), as illustrated in FIG. 4B. The first to seventh thin film transistors (T1 to T7) and the storage capacitor (Cst) are connected to first to third scan lines (SL, SL-1, SL+1) each transmitting first to third scan signals (Sn, Sn-1, Sn+1), a data line (DL) transmitting a data voltage (Dm), an emission control line (EL) transmitting an emission control signal (En), a driving voltage line (PL) transmitting a driving voltage (ELVDD), an initialization voltage line (VL) transmitting an initialization voltage (Vint), and a common electrode to which a common voltage (ELVSS) is applied.

The first thin film transistor (T1) is a driving transistor whose drain current size is determined according to the gate-source voltage, and the second to seventh thin film transistors (T2 to T7) may be switching transistors that are turned on/off according to the gate-source voltage, substantially according to the gate voltage.

The first thin film transistor (T1) may be referred to as a driving thin film transistor, the second thin film transistor (T2) may be referred to as a scan thin film transistor, the third thin film transistor (T3) may be referred to as a compensation thin film transistor, the fourth thin film transistor (T4) may be referred to as a gate initialization thin film transistor, the fifth thin film transistor (T5) may be referred to as a first emission control thin film transistor, the sixth thin film transistor (T6) may be referred to as a second emission control thin film transistor, and the seventh thin film transistor (T7) may be referred to as an anode initialization thin film transistor.

The storage capacitor (Cst) is connected between the driving voltage line (PL) and the driving gate (G1) of the driving thin film transistor (T1). The storage capacitor (Cst) may have an upper electrode (CE2) connected to the driving voltage line (PL) and a lower electrode (CE1) connected to the driving gate (G1) of the driving thin film transistor (T1).

The driving thin film transistor (T1) can control the size of the driving current (I _OLED ) flowing from the driving voltage line (PL) to the organic light emitting diode (OLED) according to the gate-source voltage. The driving thin film transistor (T1) can have a driving gate (G1) connected to the lower electrode (CE1) of the storage capacitor (Cst), a driving source (S1) connected to the driving voltage line (PL) through the first emission control thin film transistor (T5), and a driving drain (D1) connected to the organic light emitting diode (OLED) through the second emission control thin film transistor (T6).

The driving thin film transistor (T1) can output a driving current (I _OLED ) to the organic light emitting diode (OLED) according to the gate-source voltage. The size of the driving current (I _OLED ) is determined based on the difference between the gate-source voltage and the threshold voltage of the driving thin film transistor (T1). The organic light emitting diode (OLED) receives the driving current (I _OLED ) from the driving thin film transistor (T1) and can emit light with brightness according to the size of the driving current (I _OLED ).

The scan thin film transistor (T2) transmits a data voltage (Dm) to the driving source (S1) of the driving thin film transistor (T1) in response to the first scan signal (Sn). The scan thin film transistor (T2) may have a scan gate (G2) connected to the first scan line (SL), a scan source (S2) connected to the data line (DL), and a scan drain (D2) connected to the driving source (S1) of the driving thin film transistor (T1).

The compensation thin film transistor (T3) is connected in series between the driving drain (D1) and the driving gate (G1) of the driving thin film transistor (T1), and connects the driving drain (D1) and the driving gate (G1) of the driving thin film transistor (T1) to each other in response to a first scan signal (Sn). The compensation thin film transistor (T3) may have a compensation gate (G3) connected to the first scan line (SL), a compensation source (S3) connected to the driving drain (D1) of the driving thin film transistor (T1), and a compensation drain (D3) connected to the driving gate (G1) of the driving thin film transistor (T1). Although FIG. 7 illustrates that the compensation thin film transistor (T3) includes two thin film transistors that are connected in series with each other, the compensation thin film transistor (T3) may be composed of a single thin film transistor.

The gate initialization thin film transistor (T4) applies an initialization voltage (Vint) to the driving gate (G1) of the driving thin film transistor (T1) in response to the second scan signal (Sn-1). The gate initialization thin film transistor (T4) may have a first initialization gate (G4) connected to the second scan line (SL-1), a first initialization source (S4) connected to the driving gate (G1) of the driving thin film transistor (T1), and a first initialization drain (D4) connected to the initialization voltage line (VL). Although FIG. 7 illustrates that the gate initialization thin film transistor (T4) includes two thin film transistors connected in series with each other, the gate initialization thin film transistor (T4) may be composed of one thin film transistor.

The anode initialization thin film transistor (T7) applies an initialization voltage (Vint) to the anode of the organic light emitting diode (OLED) in response to a third scan signal (Sn+1). The anode initialization thin film transistor (T7) may have a second initialization gate (G7) connected to the third scan line (SL+1), a second initialization source (S7) connected to the anode of the organic light emitting diode (OLED), and a second initialization drain (D7) connected to an initialization voltage line (VL).

The first light-emitting control thin film transistor (T5) can connect the driving voltage line (PL) and the driving source (S1) of the driving thin film transistor (T1) to each other in response to the light-emitting control signal (En). The first light-emitting control thin film transistor (T5) can have a first light-emitting control gate (G5) connected to the light-emitting control line (EL), a first light-emitting control source (S5) connected to the driving voltage line (PL), and a first light-emitting control drain (D5) connected to the driving source (S1) of the driving thin film transistor (T1).

The second emission control thin film transistor (T6) can connect the driving drain (D1) of the driving thin film transistor (T1) and the anode of the organic light emitting diode (OLED) to each other in response to the emission control signal (En). The second emission control thin film transistor (T6) can have a second emission control gate (G6) connected to the emission control line (EL), a second emission control source (S6) connected to the driving drain (D1) of the driving thin film transistor (T1), and a second emission control drain (D6) connected to the anode of the organic light emitting diode (OLED).

The second scan signal (Sn-1) can be substantially synchronized with the first scan signal (Sn) of the previous row. The third scan signal (Sn+1) can be substantially synchronized with the first scan signal (Sn). According to another example, the third scan signal (Sn+1) can be substantially synchronized with the first scan signal (Sn) of the next row.

In the present embodiment, the first to seventh thin film transistors (T1 to T7) may include a semiconductor layer including silicon. For example, the first to seventh thin film transistors (T1 to T7) may include a semiconductor layer including low temperature poly-silicon (LTPS). The polysilicon material has high electron mobility (100㎠/Vs or more), low energy consumption, and excellent reliability. As another example, the semiconductor layers of the first to seventh thin film transistors (T1 to T7) may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the semiconductor layer (A) may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc. As another example, some of the semiconductor layers among the first to seventh thin film transistors (T1 to T7) may be formed of low-temperature polysilicon (LTPS), and other semiconductor layers may be formed of oxide semiconductors (IGZO, etc.).

Fig. 5 is a schematic plan view of a display device according to one embodiment of the present invention. In Fig. 5, the same reference numerals as in Fig. 2 denote the same elements, and a duplicate description thereof will be omitted.

Referring to FIG. 5, the display device (1) may include a display area (DA) and a peripheral area (PA). A gate driving circuit (GDC) and a data driving circuit (DDC) may be arranged in the peripheral area (PA).

A data driving circuit (DDC) may be placed in a first peripheral area (PA1), and a gate driving circuit (GDC) may be placed in a second peripheral area (PA2). The first peripheral area (PA1) and the second peripheral area (PA2) may be areas positioned to face each other with a display area (DA) interposed therebetween.

A data driving circuit (DDC) can provide a data signal to each pixel (PX) through a data line (DL). The data line (DL) can be connected to the data driving circuit (DDC) through a data connection line (DCL).

A gate driving circuit (GDC) can transmit a gate signal to each pixel (PX) through a gate line (GL). The gate line (GL) can be connected to the gate driving circuit (GDC) through a gate connection line (GCL). The gate driving circuit (GDC) can include a scan driving circuit and/or an emission control driving circuit. The gate line (GL) includes a scan line (SL) and/or an emission control line (EL), and the gate signal can include a scan signal and/or an emission control signal.

An internal gate driving circuit (GDCI) may be arranged in the display area (DA). The internal gate driving circuit (GDCI) may be arranged to overlap with the light-emitting area of the display element. The internal gate driving circuit (GDCI) may be arranged such that each circuit is arranged in the second direction (e.g., the y direction). The internal gate driving circuit (GDCI) may be a scan driving circuit or an emission control driving circuit.

The scan line (SL) and/or the emission control line (EL) may be extended by bypassing each of the internal gate driving circuits (GDCI). For example, the scan line (SL) and/or the emission control line (EL) may be extended in a first direction (e.g., the x direction) across adjacent internal gate driving circuits. In this case, interference between the wires and the circuits can be prevented. An embodiment of the present invention is not limited thereto, and the scan line (SL) and/or the emission control line (EL) may be arranged to overlap the internal gate driving circuit (GDCI).

In one embodiment, when the internal gate driving circuit (GDCI) is a light emission control driving circuit, the gate driving circuit (GDC) arranged in the second peripheral area (PA2) may mean a scan driving circuit. That is, one of the scan driving circuit and the light emission control driving circuit may be arranged in the second peripheral area (PA2), and the other may be arranged in the display area (DA). In this case, as illustrated in FIG. 5, the gate connection wiring (GCL) connects the gate driving circuit (GDC) and the scan line (SL), and the light emission control line (EL) may be connected to the internal gate driving circuit (GDCI).

In one embodiment, when the internal gate driving circuit (GDCI) is a scan driving circuit, the gate driving circuit (GDC) arranged in the second peripheral area (PA2) may mean a light emission control driving circuit. In this case, the gate connection wiring (GCL) connects the gate driving circuit (GDC) and the light emission control line (EL), and the scan line (SL) may be connected to the internal gate driving circuit (GDCI).

In one embodiment, a circuit that can be arranged with a narrower width among the scan driving circuit and the emission control driving circuit can be selected and arranged in the display area (DA). In other words, the width of the internal gate driving circuit (GDCI) arranged in the display area (DA) in the first direction (e.g., the x direction) can be narrower than the width of the gate driving circuit (GDC) arranged in the second peripheral area (PA2) in the second direction (e.g., the y direction).

According to one embodiment of the present invention, a data driving circuit (DDC) may be disposed in a first peripheral area (PA1), a gate driving circuit (GDC) may be disposed in a second peripheral area (PA2), and an internal gate driving circuit (GDCI) may be disposed in a display area (DA). By disposing some of the driving circuits as internal gate driving circuits (GDCI) of the display area (DA), the area of the second peripheral area (PA2) can be reduced without reducing the area of the display area (DA). In addition, it is possible to prevent wiring from being concentrated in the second peripheral area (PA2).

FIG. 6A is a perspective view schematically illustrating a display device according to an embodiment of the present invention, and FIG. 6B is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention. FIG. 6C is a plan view schematically illustrating a portion of a display device according to an embodiment of the present invention, and FIG. 6D is a cross-sectional view schematically illustrating a display device according to an embodiment of the present invention. In FIGS. 6A to 6D, the same reference numerals as in FIGS. 1 to 5 denote the same members, and their redundant descriptions are omitted.

Referring to FIG. 6A, the display device (1) may include a display area (DA) and a peripheral area (PA) located outside the display area (DA). The display area (DA) may display an image through subpixels. The peripheral area (PA) is a non-display area located outside the display area (DA) and does not display an image, and may entirely surround the display area (DA).

The display area (DA) may include a first display area (DA1) that occupies most of the display area (DA) and a second display area (DA2) that corresponds to the component described later with reference to FIG. 6B. The first display area (DA1) may occupy most of the area of the display area (DA). Occupying most of the area may indicate that the area of the first display area (DA1) is about 50% or more of the area of the display area (DA).

The second display area (DA2) is arranged inside the first display area (DA1) and may be entirely surrounded by the first display area (DA1). The display area (DA) may include a third display area (DA3) between the first display area (DA1) and the second display area (DA2). The third display area (DA3) may surround the second display area (DA2), and the first display area (DA1) may surround the third display area (DA3).

The display area (DA) can display an image using two-dimensionally arranged subpixels. In this specification, among the subpixels arranged in the display area (DA), the subpixels arranged in the first display area (DA1) are referred to as first subpixels (P1), the subpixels arranged in the second display area (DA2) are referred to as second subpixels (P2), and the subpixels arranged in the third display area (DA3) are referred to as third subpixels (P3).

The second display area (DA2) and the third display area (DA3) may each have a smaller area than the first display area (DA1). FIG. 1 illustrates that the second display area (DA2) and the third display area (DA3) each have a circular shape. In another embodiment, the second display area (DA2) and the third display area (DA3) may each have an approximately rectangular shape.

FIG. 6a illustrates that the second display area (DA2) and the third display area (DA3) are arranged in the center of the upper side (+y direction) of the display area (DA) which has a roughly rectangular shape when viewed from a direction roughly perpendicular to the upper surface of the display device (1), but the present invention is not limited thereto. The second display area (DA2) and the third display area (DA3) may be arranged, for example, in the upper right or upper left side of the display area (DA).

The second display area (DA2) can implement an image through the second subpixel (P2), and can transmit light and/or sound through the area between the second subpixels (P2). Hereinafter, the area through which light or sound can transmit is referred to as a transmission area (TA). In other words, the second display area (DA2) can include a transmission area (TA) between the second subpixels (P2).

FIG. 6b is a cross-sectional view schematically illustrating a display device according to one embodiment of the present invention.

Referring to FIG. 6b, the display device (1) may include a display panel (10) and a component (20) arranged to overlap the display panel (10). The component (20) may be arranged in a second display area (DA2).

The component (20) may be an electronic element that utilizes light or sound. For example, the electronic element may be a sensor that measures distance, such as a proximity sensor, a sensor that recognizes a part of the user's body (e.g., a fingerprint, an iris, a face, etc.), a small lamp that outputs light, or an image sensor that captures an image (e.g., a camera). The electronic element that utilizes light may utilize light of various wavelength bands, such as visible light, infrared light, or ultraviolet light. The electronic element that utilizes sound may utilize ultrasonic waves or sound of another frequency band.

The second display area (DA2) may include a transparent area (TA) through which light and/or sound, which is output from the component (20) to the outside or travels toward the component (20) from the outside, may be transmitted. In one embodiment, the transparent area (TA) is an area through which light may be transmitted and may correspond to an area between the second subpixels (P2). In the case of the display device (1) according to one embodiment of the present invention, when light is transmitted through the second display area (DA2) including the transparent area (TA), the light transmittance may be about 10% or more, more preferably 25% or more, 40% or more, 50% or more, 85% or more, or 90% or more.

Each of the first subpixel (P1), the second subpixel (P2), and the third subpixel (P3) described above with reference to FIG. 6a can emit light using a light-emitting diode, and each light-emitting diode can be arranged in the display area (DA) of the display panel (10). In this regard, in the present specification, the light-emitting diode corresponding to the first subpixel (P1) and arranged in the first display area (DA1) is referred to as a first light-emitting diode (ED1), the light-emitting diode corresponding to the second subpixel (P2) and arranged in the second display area (DA2) is referred to as a second light-emitting diode (ED2), and the light-emitting diode corresponding to the third subpixel (P3) and arranged in the third display area (DA3) is referred to as a third light-emitting diode (ED3). The first to third light-emitting diodes (ED1, ED2, ED3) can be arranged on the substrate (100).

A protective film (PB) may be placed on the back surface of the substrate (100). The protective film (PB) may include an opening (PB-OP) positioned in the second display area (DA2) to improve the transmittance of the transmission area (TA).

A first light-emitting diode (ED1) is arranged in a first display area (DA1) and is electrically connected to a first subpixel circuit (PC1) arranged in the first display area (DA1). The first subpixel circuit (PC1) may include transistors and a storage capacitor electrically connected to the transistors.

The second light-emitting diode (ED2) is arranged in the second display area (DA2). The second light-emitting diode (ED2) is electrically connected to the second subpixel circuit (PC2), and in order to improve the transmittance and the transmittance area of the transmission area (TA) provided in the second display area (DA2), the second subpixel circuit (PC2) is not arranged in the second display area (DA2). The second subpixel circuit (PC2) is arranged in the third display area (DA3), and the second light-emitting diode (ED2) can be electrically connected to the second subpixel circuit (PC2) through a conductive bus line (CBL).

The conductive bus line (CBL) can electrically connect the second subpixel circuit (PC2) of the third display area (DA3) and the second light-emitting diode (ED2) of the second display area (DA2). The conductive bus line (CBL) can include a conductive material having light-transmitting properties, such as a transparent conductive oxide (TCO). The transparent conductive oxide (TCO) can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ : indium oxide), indium gallium oxide (IGO), and/or aluminum zinc oxide (AZO).

A third light-emitting diode (ED3) is arranged in a third display area (DA3) and is electrically connected to a third subpixel circuit (PC3) arranged in the third display area (DA3). The third subpixel circuit (PC3) may include transistors and a storage capacitor electrically connected to the transistors.

The first to third light-emitting diodes (ED1, ED2, ED3) are light-emitting elements that emit light of a predetermined color and may include organic light-emitting diodes.

The first to third light-emitting diodes (ED1, ED2, ED3) may be covered with an encapsulating layer (300). The encapsulating layer (300) may be a thin film encapsulating layer including an inorganic encapsulating layer including an inorganic insulating material and an organic encapsulating layer including an organic insulating material. The encapsulating layer (300) may be an encapsulating substrate such as a glass material. A sealant including a frit or the like may be disposed between the substrate (100) and the encapsulating substrate. The sealant may be positioned in the peripheral area (PA) and may extend to surround the outer edge of the display area (DA), thereby preventing moisture from penetrating toward the first to third light-emitting diodes (ED1, ED2, ED3) through the side.

The input detection layer (400) may be formed on the sealing layer (300). The input detection layer (400) may obtain coordinate information according to an external input, for example, a touch event of an object such as a finger or a stylus pen. The input detection layer (400) may include a touch electrode and trace lines connected to the touch electrode. The input detection layer (400) may detect an external input using a mutual capping method or a self capping method.

The optical function layer (500) may include an anti-reflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident from the outside toward the display panel (10) through the cover window (600). The anti-reflection layer may include a retarder and a polarizer. When the optical function layer (500) includes a polarizer, the optical function layer (500) may include an opening (510) located in the second display area (DA2), thereby improving the transmittance of the transmission area (TA).

In another embodiment, the anti-reflection layer may include a black matrix and color filters. The color filters may be arranged in consideration of the color of light emitted from each of the first to third light-emitting diodes (ED1, ED2, ED3). When the optical function layer (500) includes a black matrix and color filters, a light-transmitting material may be placed at a position corresponding to the transmission area (TA).

In another embodiment, the antireflection layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer disposed on different layers. The first reflected light and the second reflected light reflected by the first reflective layer and the second reflective layer, respectively, may destructively interfere, thereby reducing the external light reflectance.

The cover window (600) may be disposed on the optical function layer (500). The cover window (600) may be bonded to the optical function layer (500) through an adhesive layer, such as a transparent optically transparent adhesive, interposed therebetween. The cover window (600) may include a glass material and/or a plastic material. The plastic material may include polyethersulfone, polyacrylate, polyether imide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

The cover window (600) may include a flexible cover window. For example, the cover window (600) may include polyimide and/or ultra-thin glass.

FIG. 6c is a plan view showing the shape of the second bending area (BA2) of the display device (1) before it is bent, and FIG. 6d is a schematic cross-sectional view showing the shape of the second bending area (BA2) in a bent state.

Referring to FIGS. 6c and 6d, the gate driving circuit (GDC) disposed in the second peripheral area (PA2) may be disposed to at least partially surround a predetermined area in the second peripheral area (PA2). Alternatively, the gate driving circuit (GDC) may be disposed to avoid a predetermined area in the second peripheral area (PA2).

The predetermined area may be a corresponding area (PADA2) corresponding to the second display area (DA). Specifically, the corresponding area (PADA2) may be an area corresponding to the second display area (DA2) on which the component (20, see FIG. 6b) is placed when viewed in a direction perpendicular to the substrate (100) (e.g., in the z direction). The corresponding area (PADA2) may be an area overlapping the second display area (DA2) when viewed in a direction perpendicular to the substrate (100) (e.g., in the z direction).

As in one embodiment of the present invention, when the area where the gate driving circuit (GDC) disposed in the second peripheral area (PA2) overlaps with the component (20) is reduced or eliminated, interference between the gate driving circuit (GDC) and the component (20) can be prevented during bending.

Fig. 7 is a cross-sectional view schematically illustrating a display device according to one embodiment of the present invention. In Fig. 7, the same reference numerals as in Fig. 3b denote the same members, and a duplicate description thereof will be omitted.

Referring to FIG. 7, the gate driving circuit (GDC) includes a thin film transistor (TFT) and a storage capacitor (Cst), and the thin film transistor (TFT) may include a semiconductor layer (A), a gate electrode (G), a source electrode (S), and a drain electrode (D). The inorganic insulating layer (IIL) disposed on the substrate (100) may include a buffer layer (111), a first gate insulating layer (112), a second gate insulating layer (113), and an interlayer insulating layer (114).

The inorganic insulating layer (IIL) may include a groove (GV). The groove (GV) may be a shape in which a portion of the inorganic insulating layer (IIL) is removed in a trench shape. For example, the groove (GV) may be a shape in which an opening of the buffer layer (111), an opening of the first gate insulating layer (112), an opening of the second gate insulating layer (113), and an opening of the interlayer insulating layer (114) overlap in a third direction (e.g., the z direction). Although FIG. 7 illustrates that the groove (GV) is formed to a depth that exposes the upper surface of the substrate (100), the embodiments of the present invention are not limited thereto, and the depth of the groove (GV) may be formed in various ways. For example, the groove (GV) may be formed to a depth that exposes the upper surface of the buffer layer (111).

The gate driving circuit (GDC) may include a first gate driving circuit (GDC1), a second gate driving circuit (GDC2), a third gate driving circuit (GDC3), and a fourth gate driving circuit (GDC4). The first gate driving circuit (GDC1), the second gate driving circuit (GDC2), the third gate driving circuit (GDC3), and the fourth gate driving circuit (GDC4) may be circuits that each transmit different signals to a pixel. For example, referring to FIG. 4B together, the first gate driving circuit (GDC1) may be a circuit that transmits a first scan signal (Sn), the second gate driving circuit (GDC2) may be a circuit that transmits a second scan signal (Sn-1), the third gate driving circuit (GDC3) may be a circuit that transmits a third scan signal (Sn+1), and the fourth gate driving circuit (GDC4) may be a circuit that transmits an emission control signal (Em).

The grooves (GV) can be positioned to surround each of the gate driving circuits (GDC). The grooves (GV) can be formed along an edge of one gate driving circuit (GDC). Alternatively, the grooves (GV) can be formed to surround adjacent predetermined gate driving circuits (GDC). The grooves (GV) can have an approximately rectangular shape when viewed in a plane (in the z direction).

The groove (GV) can be located between adjacent gate driving circuits (GDC). As shown in Fig. 7, the groove (GV) can be located between the first gate driving circuit (GDC1) and the second gate driving circuit (GDC2), between the second gate driving circuit (GDC2) and the third gate driving circuit (GDC3), and between the third gate driving circuit (GDC3) and the fourth gate driving circuit (GDC4).

The first planarization layer (115) may be embedded in the groove (GV). The first planarization layer (115) may be an organic insulating layer. Since the first planarization layer (115) embedded in the groove (GV) formed in the inorganic insulating layer (IL) includes an organic material, it is possible to prevent or reduce a crack formed in the inorganic insulating layer (IL) in one pixel from being transmitted or grown into an adjacent pixel due to an impact from the outside. In particular, it can be robust against an impact occurring in the process of bending the second bending area (BA2) adjacent to the gate driving circuit (GDC).

The description of the groove (GV) described above can be applied not only to the gate driving circuit (GDC) but also to the data driving circuit (DDC). For example, the groove (GV) is arranged between adjacent data driving circuits (DDC), and an organic insulating layer is embedded in the groove (GV), so that the display device (1) can be robust to shocks, etc. that occur when bending the first bending area (BA1).

So far, only the display device has been mainly described, but the present invention is not limited thereto. For example, a display panel manufacturing method for manufacturing such a display panel and a display device manufacturing method for manufacturing a display device are also within the scope of the present invention.

Although the present invention has been described with reference to the embodiments shown in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the appended claims.

1: Display device
10: Display panel
GDC: Gate Drive Circuit
GDCI: Internal Gate Drive Circuit
DDC: Data Drive Circuit
GCL: Gate Connection Wiring
DCL: Data Link Wiring
DE: Display Element
PA1: Peripheral area 1
PA2: Second peripheral area
GV: Groove
PADA2: Response Area

Claims (20)

A substrate including a peripheral region including a first peripheral region having a first bending region and a second peripheral region having a second bending region, and a display region;
The above first bending and second bending regions have signal lines within the organic film and are bent 180 degrees from behind the light-emitting portion to apply signals to the display regions, respectively;
A pixel arranged on the display area and including a display element;
Data lines, driving chips and power wiring arranged in the first peripheral area;
Gate lines and driving circuits arranged in the second peripheral area;
Data lines connected to the above data driving chip and the above pixels;
A gate line connected to the above gate driving circuit and the above pixel;
A gate connection wiring, one side of which is connected to the gate driving circuit and the other side of which is connected to the gate line;
A display device, wherein the first peripheral area and the second peripheral area face each other with the display area interposed therebetween. In the first paragraph,
A display device, wherein the gate connection wiring overlaps the display area. In the first paragraph,
A display device, comprising a display circuit board attached to the first peripheral area or the second peripheral area. In the first paragraph,
A display device, wherein the gate line extends in a first direction, and the data line and the gate connection wiring extend in a second direction intersecting the first direction. In the first paragraph,
The above first bending region is located between the display region and the data driving circuit,
A display device, wherein the second bending region is located between the display region and the gate driving circuit. In the first paragraph,
A display device further comprising an internal gate driving circuit arranged in the display area. In Article 6,
A display device, wherein the internal gate driving circuit is provided to transmit a light emission control signal to the pixel. In the first paragraph,
A first insulating layer disposed in a first peripheral area on the substrate and having a groove surrounding the data driving circuit; and
A display device further comprising a second insulating layer, at least a portion of which is embedded in the groove. In the first paragraph,
A first insulating layer disposed in a second peripheral area on the substrate and having a groove surrounding the gate driving circuit; and
A display device further comprising a second insulating layer, at least a portion of which is embedded in the groove. In the first paragraph,
The display area includes a first display area and a second display area at least partially surrounded by the first display area,
A display device, wherein the gate driving circuit is arranged to at least partially surround a portion of the second peripheral area that overlaps the second display area when viewed in a direction perpendicular to the substrate. A substrate including a first peripheral region including a first bending region, a peripheral region including a second peripheral region facing the first peripheral region, and a display region disposed between the first peripheral region and the second peripheral region;
A pixel arranged on the display area and including a display element;
A data driving circuit arranged in the first peripheral area;
A gate driving circuit arranged in the second peripheral area;
a gate line connected to the gate driving circuit and extending in the first direction and connected to the pixel; and
A display device, comprising: a data line connected to the data driving circuit and extending in a second direction intersecting the first direction and connected to the pixel; In Article 11,
A display device, wherein the second peripheral region includes a second bending region facing the first bending region in the second direction. In Article 12,
The above first bending region is located between the display region and the data driving circuit,
A display device, wherein the second bending region is located between the display region and the gate driving circuit. In Article 11,
A display device further comprising a gate connection wiring extending in the second direction, one end of which is connected to the gate driving circuit and the other end of which is connected to the gate line. In Article 11,
A display device further comprising a display circuit board attached to the first peripheral area or the second peripheral area. In Article 11,
A display device further comprising an internal gate driving circuit arranged along the second direction in the display area. In the first paragraph,
A display device further comprising: a first insulating layer disposed on the substrate and having a groove surrounding each of the gate driving circuits or each of the data driving circuits; In Article 17,
A display device further comprising a second insulating layer, at least a portion of which is embedded in the groove. In Article 11,
The display area further includes a first display area and a second display area at least partially surrounded by the first display area,
A display device further comprising a component arranged to correspond to the second display area at the lower portion of the substrate. In Article 19,
A display device, wherein the gate driving circuit is arranged to at least partially surround a portion of the second peripheral area corresponding to the component when viewed in a direction perpendicular to the substrate.

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