KR20240157035A - store - Google Patents

Abstract

A memory device capable of miniaturization or high integration is provided. A memory cell having a capacitor and a transistor on the capacitor, a first insulator on the capacitor, and a second insulator on the first insulator, the transistor having a first conductor under the first insulator, an oxide semiconductor arranged in contact with an upper surface of the first conductor, a second conductor arranged between the first insulator and the second insulator and in contact with the oxide semiconductor, a third insulator on the oxide semiconductor, and a third conductor on the third insulator, a first opening reaching the first conductor is formed in the first insulator, the second conductor, and the second insulator, and at least a part of the oxide semiconductor, at least a part of the third insulator, and at least a part of the third conductor are arranged within the first opening, the capacitor having a fourth conductor, a fourth insulator on the fourth conductor, and a first conductor on the fourth insulator.

Description

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One embodiment of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Or, one embodiment of the present invention relates to a method for manufacturing a memory device or a semiconductor device. Or, one embodiment of the present invention relates to a semiconductor wafer and a module.

In addition, in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, calculation devices, and memory devices are types of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, etc. may be said to have semiconductor devices.

In addition, one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

In recent years, the development of semiconductor devices has been in progress, and LSI, CPU, memory, etc. are mainly used in semiconductor devices. CPU has a semiconductor integrated circuit (at least transistors and memory) formed into a chip by processing a semiconductor wafer, and is an assembly of semiconductor elements with electrodes, which are connection terminals, formed.

Semiconductor circuits (IC chips), such as LSI, CPU, and memory, are mounted on circuit boards, such as printed wiring boards, and are used as one of the components of various electronic devices.

Also, a technology for forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as materials for semiconductor thin films that can be applied to transistors, but oxide semiconductors are attracting attention as other materials.

In addition, it is known that transistors using oxide semiconductors have very low leakage current in the non-conducting state. For example, patent document 1 discloses a CPU with low power consumption, etc. that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. In addition, for example, patent document 2 discloses a memory device that can retain memory contents for a long period of time, etc. that utilizes the characteristic of low leakage current of transistors using oxide semiconductors.

In addition, as electronic devices have become smaller and lighter in recent years, there has been an increasing demand for integrated circuits with higher densities. In addition, there has been a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide a plurality of overlapping memory cells.

Japanese Patent Publication No. 2012-257187 Japanese Patent Publication No. 2011-151383 International Publication No. WO2021/053473

M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53

One aspect of the present invention has as one of its objects the provision of a memory device capable of miniaturization or high integration. Or, one of its objects is the provision of a memory device with a high operating speed. Or, one of its objects is the provision of a memory device with good electrical characteristics. Or, one of its objects is the provision of a memory device with little variation in the electrical characteristics of a transistor. Or, one of its objects is the provision of a memory device with good reliability. Or, one of its objects is the provision of a memory device with a high on-state current. Or, one of its objects is the provision of a memory device with low power consumption. Or, one of its objects is the provision of a novel memory device. Or, one of its objects is the provision of a method for manufacturing a novel memory device.

In addition, the description of these tasks does not interfere with the existence of other tasks. In addition, it is not necessary for one embodiment of the present invention to solve all of these tasks. In addition, tasks other than these are automatically apparent from the description of the specification, drawings, claims, etc., and tasks other than these can be extracted from the description of the specification, drawings, claims, etc.

One embodiment of the present invention is a memory device having a capacitor, a transistor over the capacitor, a first insulator over the capacitor, and a second insulator over the first insulator, wherein the transistor has a first conductor under the first insulator, an oxide semiconductor arranged in contact with an upper surface of the first conductor, a second conductor arranged between the first insulator and the second insulator and in contact with the oxide semiconductor, a third insulator over the oxide semiconductor, and a third conductor over the third insulator, wherein a first opening is formed in the first insulator, the second conductor, and the second insulator reaching the first conductor, and at least a part of the oxide semiconductor, at least a part of the third insulator, and at least a part of the third conductor are arranged within the first opening, and the capacitor has a fourth conductor, a fourth insulator over the fourth conductor, and the first conductor over the fourth insulator.

Another aspect of the present invention has a capacitor, a transistor on the capacitor, a first layer and a second layer each including a first insulator on the capacitor, and a second insulator on the first insulator, the second layer being laminated on the first layer, the transistor having a first conductor below the first insulator, an oxide semiconductor arranged in contact with an upper surface of the first conductor, a second conductor arranged between the first insulator and the second insulator and in contact with the oxide semiconductor, a third insulator on the oxide semiconductor, and a third conductor on the third insulator, a first opening reaching the first conductor is formed in the first insulator, the second conductor, and the second insulator, and at least a part of the oxide semiconductor, at least a part of the third insulator, and at least a part of the third conductor are arranged within the first opening, and the capacitor having a fourth conductor, a fourth insulator on the fourth conductor, and a first insulator on the fourth insulator. A memory device having a conductor, a second opening formed in a second insulator of a first layer and a first insulator of a second layer, and a fifth conductor within the second opening, the fifth conductor being in contact with an upper surface of the second conductor of the first layer and also in contact with a lower surface of the second conductor of the second layer.

In the above memory device, it is preferable that the sixth conductor is formed so as to be in contact with the upper surface of the third conductor, the second conductor is formed so as to extend in the first direction, the sixth conductor is formed so as to extend in the second direction, and the first direction and the second direction intersect each other.

In addition, in the above memory device, it is preferable that the first conductor functions as one of the source electrode and the drain electrode, the second conductor functions as the other of the source electrode and the drain electrode, and the third conductor functions as the gate electrode.

Additionally, in the above memory device, it is preferable that a portion of the oxide semiconductor, a portion of the third insulator, and a portion of the third conductor are positioned on the second insulator.

In addition, in the above memory device, it is preferable that the side edge of the oxide semiconductor and the side edge of the third insulator substantially coincide when viewed from a plane.

In addition, in the above memory device, it is preferable that the side end of the third conductor is located inward relative to the side end of the oxide semiconductor and the side end of the third insulator when viewed from a plane.

In addition, in the above memory device, it is preferable that a fifth insulator be provided between the third insulator and the third conductor, and that the fifth insulator covers the side end of the oxide semiconductor and the side end of the third insulator. In addition, in the above memory device, it is preferable that the fifth insulator is silicon nitride.

In addition, in the above memory device, it is preferable that the oxide semiconductor has one or more selected from In, Ga, and Zn. In addition, in the above memory device, it is preferable that the oxide semiconductor has a layered crystal substantially parallel to the sidewall of the first opening. In addition, in the above memory device, it is preferable that the concentration of carbon in the oxide semiconductor is less than 1×10 ²⁰ atoms/cm ³ .

According to one embodiment of the present invention, a memory device capable of miniaturization or high integration can be provided. Or a memory device having a high operating speed can be provided. Or a memory device having good reliability can be provided. Or a memory device having little variation in the electrical characteristics of a transistor can be provided. Or a memory device having good electrical characteristics can be provided. Or a memory device having a high on-state current can be provided. Or a memory device having low power consumption can be provided. Or a novel memory device can be provided. Or a method of manufacturing a novel memory device can be provided.

In addition, the description of these effects does not preclude the existence of other effects. In addition, one embodiment of the present invention does not need to have all of these effects. In addition, effects other than these are automatically apparent from the description of the specification, drawings, claims, etc., and effects other than these can be extracted from the description of the specification, drawings, claims, etc.

Fig. 1 (A) is a plan view of a memory device according to one embodiment of the present invention. Figs. 1 (B) to (D) are cross-sectional views of a memory device according to one embodiment of the present invention. Fig. 1 (E) is a circuit diagram for explaining the configuration of a memory device according to one embodiment of the present invention.
Fig. 2 (A) is a plan view showing a method for manufacturing a memory device which is one embodiment of the present invention. Figs. 2 (B) and (C) are cross-sectional views showing a method for manufacturing a memory device which is one embodiment of the present invention.
Fig. 3 (A) is a plan view showing a method for manufacturing a memory device which is one embodiment of the present invention. Figs. 3 (B) and (C) are cross-sectional views showing a method for manufacturing a memory device which is one embodiment of the present invention.
Fig. 4 (A) is a plan view showing a method for manufacturing a memory device, which is one embodiment of the present invention. Figs. 4 (B) and (C) are cross-sectional views showing a method for manufacturing a memory device, which is one embodiment of the present invention.
Fig. 5 (A) is a plan view showing a method for manufacturing a memory device which is one embodiment of the present invention. Figs. 5 (B) and (C) are cross-sectional views showing a method for manufacturing a memory device which is one embodiment of the present invention.
Fig. 6 (A) is a plan view showing a method for manufacturing a memory device, which is one embodiment of the present invention. Figs. 6 (B) and (C) are cross-sectional views showing a method for manufacturing a memory device, which is one embodiment of the present invention.
Fig. 7(A) is a plan view showing a method for manufacturing a memory device which is one embodiment of the present invention. Figs. 7(B) and (C) are cross-sectional views showing a method for manufacturing a memory device which is one embodiment of the present invention.
Fig. 8 (A) is a plan view showing a method for manufacturing a memory device which is one embodiment of the present invention. Figs. 8 (B) and (C) are cross-sectional views showing a method for manufacturing a memory device which is one embodiment of the present invention.
Figures 9 (A) to (C) are cross-sectional views of a memory device according to one embodiment of the present invention.
Fig. 10(A) is a plan view of a memory device which is one embodiment of the present invention. Fig. 10(B) is a cross-sectional view of a memory device which is one embodiment of the present invention.
Fig. 11(A) is a plan view of a memory device which is one embodiment of the present invention. Fig. 11(B) is a cross-sectional view of a memory device which is one embodiment of the present invention.
Figures 12(A) to (E) are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention.
Figures 13(A) to (D) are cross-sectional views of a metal oxide according to one embodiment of the present invention.
Figures 14(A) to (D) are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention.
Figures 15 (A) to (C) are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention.
Figure 16 is a block diagram illustrating an example configuration of a memory device.
Figures 17 (A) and (B) are schematic diagrams and circuit diagrams explaining an example configuration of a memory device.
Figures 18 (A) and (B) are schematic diagrams explaining an example configuration of a memory device.
Figure 19 is a circuit diagram explaining an example of a configuration of a memory device.
Figures 20(A) and (B) are schematic diagrams of a semiconductor device according to one embodiment of the present invention.
Figures 21 (A) and (B) are drawings explaining examples of electronic components.
Figures 22 (A) to (E) are schematic diagrams of a memory device according to one embodiment of the present invention.
Figures 23 (A) to (H) are drawings showing an electronic device according to one embodiment of the present invention.
Figure 24 is a drawing showing an example of a space device.

Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments may be implemented in many different forms, and that the forms and details thereof may be variously changed without departing from the spirit and scope thereof. Accordingly, the present invention should not be interpreted as being limited to the description of the embodiments below.

In addition, the size, layer thickness, or area in the drawing may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. In addition, the drawing schematically shows an ideal example, and is not limited to the shapes or values shown in the drawing. For example, in an actual manufacturing process, there are cases where layers or resist masks, etc. are unintentionally reduced by processes such as etching, but this may not be reflected in the drawing in order to facilitate understanding. In addition, in the drawing, the same symbol is commonly used in different drawings for the same part or part having the same function, and repeated explanations for this are sometimes omitted. In addition, when indicating a part having the same function, the hatch pattern is the same and no special symbol is sometimes attached.

In addition, in particular, in plan views (also called "top views") or perspective views, etc., descriptions of some components may be omitted to facilitate understanding of the invention. In addition, descriptions of some hidden lines may be omitted.

In addition, ordinal numbers such as first, second, etc. in this specification and the like are used for convenience and do not indicate the process order or the stacking order. Therefore, for example, "first" may be appropriately replaced with "second" or "third". In addition, there are cases where ordinal numbers described in this specification and the like do not match with ordinal numbers used to specify one embodiment of the present invention.

In addition, phrases indicating arrangement such as "above" and "below" in this specification and the like are used for convenience in explaining the positional relationship between components with reference to drawings. In addition, the positional relationship between components changes appropriately depending on the direction in which each configuration is described. Therefore, it is not limited to the phrases described in the specification, and can be appropriately changed depending on the situation.

For example, in this specification, etc., when X and Y are connected, it means that X and Y are electrically connected. Here, when X and Y are electrically connected, it means a connection that can transmit an electric signal between X and Y when an object (an element such as a switch, a transistor element, or a diode, or a circuit including the element and wiring, etc.) exists between X and Y. In addition, when X and Y are electrically connected, it includes a case where X and Y are directly connected. Here, when X and Y are directly connected, it means a connection that can transmit an electric signal between X and Y through wiring (or electrodes), etc., without going through the object. In other words, a direct connection means a connection that can be regarded as the same circuit diagram when represented as an equivalent circuit.

In addition, in this specification and the like, a transistor is a device having at least three terminals including a gate, a drain, and a source. And it has a region (hereinafter, also referred to as a channel formation region) in which a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. In addition, in this specification and the like, the channel formation region refers to a region through which current mainly flows.

In addition, the functions of the source and drain may be interchanged when transistors of different polarities are used or when the direction of current changes in circuit operation. Therefore, in this specification and elsewhere, the terms source and drain may be used interchangeably.

Also, the impurity of a semiconductor refers to, for example, something other than the main component that constitutes the semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be considered an impurity. By including an impurity, for example, the density of defect states of the semiconductor may increase, or the crystallinity may decrease. If the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor may include, for example, group 1 elements, group 2 elements, group 13 elements, group 14 elements, group 15 elements, transition metals other than the main components of the oxide semiconductor, and examples thereof include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In addition, water may also function as an impurity. In addition, for example, the mixing of impurities may cause oxygen vacancies (V _O : also called oxygen vacancies) to be formed in an oxide semiconductor.

In addition, as used herein, silicon oxynitride refers to a composition having a higher oxygen content than nitrogen. In addition, silicon nitride refers to a composition having a higher nitrogen content than oxygen. In addition, aluminum oxynitride refers to a composition having a higher oxygen content than nitrogen. In addition, aluminum oxynitride refers to a composition having a higher nitrogen content than oxygen. In addition, hafnium oxynitride refers to a composition having a higher oxygen content than nitrogen. In addition, hafnium oxynitride refers to a composition having a higher nitrogen content than oxygen.

In addition, the term "insulator" in this specification and elsewhere may be replaced with insulating film or insulating layer. In addition, the term "conductor" may be replaced with conductive film or conductive layer. In addition, the term "semiconductor" may be replaced with semiconductor film or semiconductor layer.

In addition, in this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, a case of -5° or more and 5° or less is also included. In addition, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. In addition, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, a case of 85° or more and 95° or less is also included. In addition, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

In addition, in this specification and elsewhere, "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from a reference potential, and for example, if the reference potential is the ground potential (ground potential), "voltage" can be interchanged with "potential." In addition, the ground potential does not necessarily mean 0 V. In addition, potential is relative, and as the reference potential changes, the potential supplied to wiring, the potential applied to circuits, etc., the potential output from circuits, etc. also change.

In cases where the same symbol is used for multiple elements in this specification and there is a need to specifically distinguish them, the symbol may be described by adding an identifying symbol such as “_1”, "[n]", or "[m,n]".

In addition, in this specification and the like, "the heights are the same or substantially the same" means a configuration that, when viewed in cross-section, has the same height as a reference surface (e.g., a flat surface such as a substrate surface). For example, in a manufacturing process of a memory device, there are cases where a surface of a single layer or multiple layers is exposed by performing a flattening process (typically, CMP process). In this case, the surface to be processed on which the CMP process has been performed has the same height as the reference surface. However, depending on the processing device, processing method, or material of the surface to be processed used for the CMP process, there are cases where the heights of the multiple layers are different from each other. In this specification and the like, this case is also included in "the heights are the same or substantially the same." For example, if there are two layers (here, the first layer and the second layer) having heights with respect to a reference surface, and the difference between the height of the upper surface of the first layer and the height of the upper surface of the second layer is 20 nm or less, it is also said that "the heights are the same or substantially the same."

In addition, in this specification and the like, "the ends coincide or substantially coincide" means that, when viewed in a plan view, at least a part of the outlines overlap between the laminated layers. For example, this category includes cases where the upper and lower layers are processed using the same mask pattern or partly the same mask pattern. However, strictly speaking, there are cases where the outlines do not overlap and the outline of the upper layer is located inside the outline of the lower layer, or the outline of the upper layer is located outside the outline of the lower layer, and in these cases, "the ends coincide or substantially coincide" is also said.

(Embodiment 1)

In this embodiment, an example of a memory device according to one embodiment of the present invention and a method for manufacturing the same will be described using FIGS. 1 to 11. The memory device according to one embodiment of the present invention has a transistor and a capacitor element.

<Example of memory device configuration>

Hereinafter, a configuration of a memory device having a transistor and a capacitor will be described using FIG. 1. FIGS. 1(A) to 1(D) are a plan view and a cross-sectional view of a memory device having a transistor (200) and a capacitor (100). FIG. 1(A) is a plan view of the memory device. In addition, FIGS. 1(B) to 1(D) are cross-sectional views of the memory device. Here, FIG. 1(B) is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in FIG. 1(A). In addition, FIG. 1(C) is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 1(A). In addition, FIG. 1(D) is a cross-sectional view of a portion of a transistor (200). In addition, some elements are omitted in the plan view of FIG. 1(A) for clarity of the drawing.

In addition, the Z direction shown in (A) of Fig. 1 is parallel to the channel length direction of the transistor (200), the Y direction is perpendicular to the Z direction, and the X direction is perpendicular to the Z direction and the Y direction. In addition, the X direction, the Y direction, and the Z direction shown in (A) of Fig. 1 are also illustrated in (B) to (D) of Figs.

A memory device of one embodiment of the present invention has an insulator (140) on a substrate (not shown), a capacitor (100) on the insulator (140), a transistor (200) on the capacitor (100), an insulator (280) on the insulator (140) and the capacitor (100), an insulator (281) and a conductor (240) on the insulator (280), an insulator (285) on the insulator (281) and the conductor (240), an insulator (287) on the insulator (285), and an insulator (289) and a conductor (265) on the insulator (287). The insulator (140), the insulator (280), the insulator (281), the insulator (285), the insulator (287), and the insulator (289) function as interlayer films.

A transistor (200) has a conductor (120) under an insulator (280), an oxide semiconductor (230) arranged in contact with an upper surface of the conductor (120), a conductor (240) in contact with a part of the oxide semiconductor, an insulator (250) over the oxide semiconductor (230), and a conductor (260) over the insulator (250). Here, the oxide semiconductor (230) functions as a semiconductor layer, the conductor (260) functions as a gate electrode, the conductor (120) functions as one of a source electrode and a drain electrode, the conductor (240) functions as the other of the source electrode and the drain electrode, and the insulator (250) functions as a gate insulator.

As shown in (B) and (C) of FIG. 1, an opening (290) is formed in the insulator (280), the conductor (240), and the insulator (285) to reach the conductor (120). At least a portion of the oxide semiconductor (230), at least a portion of the insulator (250), and at least a portion of the conductor (260) are arranged within the opening (290).

The capacitor (100) has a conductor (110) on an insulator (140), an insulator (130) on the conductor (110), and a conductor (120) on the insulator (130). The conductor (110) functions as a lower electrode, the conductor (120) functions as an upper electrode, and the insulator (130) functions as a dielectric. That is, the capacitor (100) constitutes a MIM (Metal-Insulator-Metal) capacitor.

The transistor (200) and the capacitor (100) shown in the present embodiment can be used as a memory cell of a memory device (hereinafter, sometimes referred to as a memory cell (150)). Here, as shown in (B) and (C) of FIG. 1, the transistor (200) is provided to overlap with the capacitor (100). In particular, since the conductor (120) functions as one of the source electrode and the drain electrode of the transistor (200) and also functions as the upper electrode of the capacitor (100), the transistor (200) and the capacitor (100) share a part of the structure. By having this structure, the transistor (200) and the capacitor (100) can be provided without significantly increasing the occupied area when viewed from a planar view. Since the area of the memory cell (150) can be reduced, the memory cell (150) can be arranged at a high density, and the memory capacity of the memory device can be increased. In other words, the memory device can be highly integrated.

A circuit diagram of a memory device described in this embodiment is shown in Fig. 1 (E). As shown in Fig. 1 (E), the configurations shown in Figs. 1 (A) to (C) function as memory cells of the memory device. One memory cell has a transistor (Tr) and a capacitor element (C). Here, the transistor (Tr) corresponds to a transistor (200), and the capacitor element (C) corresponds to a capacitor element (100).

In the memory cell, one of the source and drain of the transistor (Tr) is connected to one electrode of the capacitor (C). The other of the source and drain of the transistor (Tr) is connected to the wiring (BL). The gate of the transistor (Tr) is connected to the wiring (WL). The other electrode of the capacitor (C) is connected to the wiring (PL).

Here, the wiring (BL) corresponds to the conductor (240), the wiring (WL) corresponds to the conductor (265), and the wiring (PL) corresponds to the conductor (110). As shown in (A) to (C) of FIG. 1, it is preferable that the conductor (265) is formed to extend in the Y direction, and the conductor (240) is formed to extend in the X direction. By having this configuration, the wiring (BL) and the wiring (WL) are provided to intersect each other. In addition, in (E) of FIG. 1, the wiring (PL) is provided parallel to the wiring (WL), but the present invention is not limited thereto. For example, the wiring (PL) (conductor (110)) may be provided parallel to the wiring (BL), or the wiring (PL) (conductor (110)) may be provided in a plane.

Also, the memory cell will be described in detail in a later embodiment.

[Transistor (200)]

As shown in (A) to (C) of FIG. 1, the transistor (200) can be configured to have a conductor (120) provided in contact with an insulator (130), an oxide semiconductor (230) provided in contact with the upper surface of the conductor (120), the side surface of the insulator (280), the side surface of the conductor (240), the side surface and the upper surface of the insulator (285), an insulator (250) provided in contact with the upper surface of the oxide semiconductor (230), a conductor (240) provided to be embedded in the insulator (281), a conductor (260) provided in contact with the upper surface of the insulator (250), and a conductor (265) provided in contact with the upper surface of the conductor (260) and embedded in the insulator (289).

At least a portion of the transistor (200) is disposed within the opening (290). The opening (290) may be provided in a cylindrical shape as shown in (A) to (D) of FIG. 1. In this case, the opening (290) is circular when viewed from a plan view, and is rectangular when viewed from a cross-section. Here, the bottom surface of the opening (290) is the upper surface of the conductor (120), and the side walls of the opening (290) are the side surfaces of the insulator (280), the side surfaces of the conductor (240), and the side surfaces of the insulator (285).

In addition, in the present embodiment, the opening (290) is provided so that the sidewall of the opening (290) is substantially perpendicular to the upper surface of the conductor (120), but the present invention is not limited thereto. For example, the sidewall of the opening (290) may have a tapered shape. By making the sidewall of the opening (290) into a tapered shape, the covering property of the oxide semiconductor (230) or the insulator (250), etc., is improved, and defects such as cavities can be reduced.

In addition, in this specification and the like, a tapered shape refers to a shape in which at least a portion of a side surface of a structure is provided at an angle relative to a substrate surface or a formation surface. For example, it has a region in which the angle formed by the inclined side surface and the substrate surface (hereinafter sometimes referred to as a taper angle) is less than 90°. In addition, the side surface and the substrate surface of the structure do not necessarily need to be completely flat, and may have an approximately flat shape with a slight curvature or an approximately flat shape with a slight unevenness.

In addition, in this embodiment, an example is shown in which the opening (290) is circular when viewed from a plan view, but the present invention is not limited thereto. For example, the opening (290) may have a shape that is approximately circular, such as an ellipse, a polygon, such as a square, or a polygon with rounded corners, such as a square, when viewed from a plan view.

The portions arranged within the opening (290) of the oxide semiconductor (230), the insulator (250), and the conductor (260) are provided to reflect the shape of the opening (290). Accordingly, the oxide semiconductor (230) is provided to cover the bottom surface and side walls of the opening (290), the insulator (250) is provided to cover the oxide semiconductor (230), and the conductor (260) is provided to fill the concave portion of the insulator (250) reflecting the shape of the opening (290). Here, the oxide semiconductor (230) contacts the upper surface of the conductor (120) at the bottom of the opening (290) and contacts the side surface of the conductor (240) at the side walls of the opening (290).

As described above, the conductor (260) functions as a gate electrode of the transistor (200), the conductor (120) functions as one of the source electrode and the drain electrode of the transistor (200), and the conductor (240) functions as the other of the source electrode and the drain electrode of the transistor (200). Therefore, at least a portion of a region of the oxide semiconductor (230) in contact with the conductor (120) and its vicinity functions as one of the source region and the drain region, and at least a portion of a region of the oxide semiconductor (230) in contact with the conductor (240) and its vicinity functions as the other of the source region and the drain region. Here, (D) of FIG. 1 is a cross-sectional view showing an XY plane including the conductor (240). As shown in (D) of FIG. 1, the conductor (240) is in contact with the entire outer periphery of the oxide semiconductor (230). Therefore, the other of the source region and drain region of the transistor (200) can be formed on the entire outer periphery of the portion formed in the same layer as the conductor (240) among the oxide semiconductor (230).

At least a portion of a region between a region functioning as one of the source region and the drain region of the oxide semiconductor (230) and a region functioning as the other of the source region and the drain region functions as a channel forming region.

Here, the channel formation region of the transistor (200) is located in the region between the conductor (120) and the conductor (240) of the oxide semiconductor (230). In addition, it can be said that the channel formation region of the transistor (200) is located in the region in contact with the insulator (280) of the oxide semiconductor (230) or in the vicinity thereof. In other words, it can be said that the channel length of the transistor (200) is determined according to the thickness of the insulator (280) over the conductor (120).

In conventional transistors, the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the film thickness of the insulator (280). Therefore, the channel length of the transistor (200) can be made into a very fine structure (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more or 5 nm or more) that is less than the exposure limit of photolithography. As a result, the on current of the transistor (200) can be increased and the frequency characteristics can be improved. Therefore, the read speed and write speed of the memory cell (150) can be improved, so that a memory device having a high operating speed can be provided.

In addition, as described above, a channel formation region, a source region, and a drain region can be formed within the opening (290). This allows the occupied area of the transistor (200) to be reduced compared to a conventional transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows the memory device to be highly integrated, thereby increasing the memory capacity per unit area.

Also, in the XY plane including the channel formation region of the oxide semiconductor (230), the oxide semiconductor (230), the insulator (250), and the conductor (260) are provided concentrically, similarly to (D) of FIG. 1. Therefore, the side surface of the conductor (260) provided at the center faces the side surface of the oxide semiconductor (230) with the insulator (250) interposed therebetween. That is, when viewed in the plane, the entire periphery of the oxide semiconductor (230) becomes the channel formation region. At this time, for example, the channel width of the transistor (200) is determined according to the length of the outer periphery of the oxide semiconductor (230). By providing the oxide semiconductor (230), the insulator (250), and the conductor (260) in this way, the channel width per unit area can be increased, thereby increasing the on-state current.

In addition, by forming the opening (290) so as to be circular when viewed from a plane, the oxide semiconductor (230), the insulator (250), and the conductor (260) are provided in a concentric shape. Accordingly, since the distance between the conductor (260) and the oxide semiconductor (230) becomes substantially uniform, a gate electric field can be applied substantially uniformly to the oxide semiconductor (230).

It is preferable that the channel formation region of the transistor (200) has fewer oxygen vacancies or lower concentrations of impurities such as hydrogen, nitrogen, and metal elements than the source region and the drain region. In addition, since hydrogen near the oxygen vacancies may form defects in which hydrogen enters the oxygen vacancies (hereinafter sometimes referred to as V _O H) and generate electrons that become carriers, it is preferable that V _O H is also reduced in the channel formation region. In this way, the channel formation region of the transistor (200) is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor (200) can be said to be i-type (intrinsic) or substantially i-type.

In addition, the source region and drain region of the transistor (200) are regions with increased carrier concentration and low resistance due to having many oxygen vacancies, many V _O H, or high concentrations of impurities such as hydrogen, nitrogen, and metal elements compared to the channel formation region. In other words, the source region and drain region of the transistor (200) are n-type regions with high carrier concentration and low resistance compared to the channel formation region.

In addition, a part of the oxide semiconductor (230), a part of the insulator (250), and a part of the conductor (260) are positioned outside the opening (290), that is, on the insulator (285). Here, a structure may be formed in which a part of the oxide semiconductor (230) is in contact with the upper surface of the insulator (285). In addition, as shown in (B) and (C) of FIG. 1, a structure may be formed in which the side end of the oxide semiconductor (230) and the side end of the insulator (250) substantially coincide with each other. By forming the oxide semiconductor (230) and the insulator (250) using the same mask, the manufacturing process of the memory device may be simplified.

Alternatively, the insulator (250) may be structured to cover the side end of the oxide semiconductor (230). As a result, the conductor (260) and the oxide semiconductor (230) can be prevented from being short-circuited.

In addition, as shown in (B) and (C) of Fig. 1, it is preferable that the side end of the conductor (260) is positioned closer to the side end of the oxide semiconductor (230) and the side end of the insulator (250). As a result, the conductor (260) and the oxide semiconductor (230) can be prevented from being short-circuited.

The metal oxide used as the oxide semiconductor (230) preferably has a band gap of 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide having a large band gap, the off-state current of the transistor can be reduced. Since the transistor (200) has a low off-state current, by using it in a memory cell, the memory content can be retained for a long period of time. That is, since the refresh operation is unnecessary or the frequency of the refresh operation is very low, the power consumption of the memory device can be sufficiently reduced.

As the oxide semiconductor (230), it is preferable to use, for example, a metal oxide such as indium oxide, gallium oxide, and zinc oxide. In addition, it is preferable to use, as the oxide semiconductor (230), a metal oxide having two or three elements selected from indium, the element M, and zinc. In addition, the element M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. In particular, it is preferable that the element M is one or more elements selected from aluminum, gallium, yttrium, and tin. In addition, a metal oxide having indium, the element M, and zinc is sometimes expressed as In-M-Zn oxide.

In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), gallium (Ga), zinc (Zn), and tin (Sn) (IGZTO) may be used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) may be used for the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (IAGZO or IGAZO) may be used for the semiconductor layer of the transistor.

In addition, the oxide semiconductor (230) may have a stacked structure of multiple oxide layers having different chemical compositions. For example, it may have a structure in which multiple types selected from the above metal oxides are appropriately stacked.

In addition, as the oxide semiconductor (230), it is preferable to use a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or nearby, In:M:Zn=1:1:0.5 [atomic ratio] or nearby, In:M:Zn=1:1:1 [atomic ratio] or nearby, In:M:Zn=1:1:1.2 [atomic ratio] or nearby, or In:M:Zn=1:1:2 [atomic ratio] or nearby, or In:M:Zn=4:2:3 [atomic ratio] or nearby. In addition, the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, it is preferable to use gallium as the element M.

In addition, when a metal oxide is formed into a film by a sputtering method, the atomic ratio is not limited to the atomic ratio of the formed metal oxide, and may be the atomic ratio of the sputtering target used for forming the metal oxide film.

It is preferable that the oxide semiconductor (230) has crystallinity. In particular, it is preferable to use a CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide semiconductor (230).

It is preferable that the CAAC-OS has multiple layered crystal regions, and that the c-axis is oriented in the normal direction to the formation surface. For example, it is preferable that the oxide semiconductor (230) has layered crystals that are substantially parallel to the sidewall of the opening (290), particularly, the sidewall of the insulator (280). By forming it in this configuration, the layered crystals of the oxide semiconductor (230) are formed substantially parallel to the channel length direction of the transistor (200), so that the on-state current of the transistor can be increased.

CAAC-OS is a metal oxide having a high crystallinity and a dense structure, and few impurities and defects (e.g., oxygen vacancies). In particular, by performing a heat treatment at a temperature (e.g., 400° C. or higher and 600° C. or lower) at which the metal oxide does not polycrystallize after formation of the metal oxide, a CAAC-OS having a higher crystallinity and a dense structure can be obtained. By further increasing the density of the CAAC-OS in this way, diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

In addition, since it is difficult to clearly identify grain boundaries in CAAC-OS, it can be said that it is difficult for a decrease in electron mobility due to grain boundaries to occur. Therefore, metal oxides having CAAC-OS have stable physical properties. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

In addition, by using an oxide having crystallinity such as CAAC-OS as the oxide semiconductor (230), the extraction of oxygen from the oxide semiconductor (230) by the source electrode or the drain electrode can be reduced. Accordingly, since the extraction of oxygen from the oxide semiconductor (230) can be reduced even when heat treatment is performed, the transistor (200) is stable against high temperatures (so-called thermal budget) in the manufacturing process.

The insulator (250) functions as a gate insulator. As the insulator (250), an insulator described in the item of <<Insulator>> described below can be used in a single layer or a laminated form. For example, silicon oxide or silicon oxynitride can be used as the insulator (250). Silicon oxide and silicon oxynitride are preferable because they are stable against heat.

In addition, as an insulator (250), an insulator having a high dielectric constant, so-called high-k material, described in the item of <<Insulator>> described below may be used. For example, hafnium oxide or aluminum oxide may be used.

The film thickness of the insulator (250) is preferably 1 nm or more and 20 nm or less, more preferably 0.5 nm or more and 15 nm or less, and even more preferably 0.5 nm or more and 10 nm or less. It is preferable that the insulator (250) have a region of the film thickness as described above, at least in a portion.

It is desirable that the concentration of impurities such as water and hydrogen in the insulator (250) be reduced. This makes it possible to suppress impurities such as water and hydrogen from being mixed into the channel formation region of the oxide semiconductor (230).

The conductor (260) functions as a gate electrode. As the conductor (260), a conductor described in the section of <<Conductor>> described below can be used in a single layer or a laminated form. For example, a highly conductive conductive material such as tungsten can be used as the conductor (260).

In addition, it is preferable to use a conductive material that is difficult to oxidize or a conductive material having a function of suppressing the diffusion of oxygen, etc., for the conductor (260). As the conductive material, a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride, etc.) and a conductive material containing oxygen (for example, ruthenium oxide, etc.) can be mentioned. As a result, it is possible to suppress the conductivity of the conductor (260) from decreasing. In addition, the conductor (260) may have a laminated structure, and for example, it may have a structure in which tungsten is laminated on titanium nitride.

It is preferable that the conductor (260) be provided to be embedded in the insulator (287). At this time, it is preferable that the height of the upper surface of the conductor (260) and the height of the upper surface of the insulator (287) are identical or substantially identical.

In addition, in (B) and (C) of FIG. 1, the conductor (260) is provided to fill the opening (290), but the present invention is not limited thereto. For example, there is a case where a concave portion reflecting the shape of the opening (290) is formed in the central portion of the conductor (260). In addition, the concave portion may be configured to be filled with an inorganic insulating material, etc.

The conductor (120) functions as one of the source electrode and the drain electrode, and as the upper electrode of the capacitor element (100). As the conductor (120), a conductor described in the item of <<Conductor>> described below can be used in a single layer or laminated form.

As with the conductor (260), it is preferable to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen, etc. for the conductor (120). For example, titanium nitride or tantalum nitride, etc. can be used. In addition, for example, a structure in which tantalum nitride is laminated on titanium nitride may be used. In this case, the titanium nitride is in contact with the insulator (130), and the tantalum nitride is in contact with the oxide semiconductor (230).

By forming the conductor (120) into the structure described above, excessive oxidation of the conductor (120) by the oxide semiconductor (230) can be reduced. In addition, when an oxide insulator is used for the insulator (130), excessive oxidation of the conductor (120) by the insulator (130) can be reduced.

In addition, although (B) and (C) of FIG. 1 show a configuration in which the upper surface of the conductor (120) is flat, the present invention is not limited thereto. A configuration in which a concave portion overlapping with the opening (290) is formed on the upper surface of the conductor (120) may be used. By forming a configuration in which at least a portion of the oxide semiconductor (230), the insulator (250), and the conductor (260) are formed to fill the concave portion, it is easy to apply the gate electric field of the conductor (260) to the vicinity of the conductor (120) of the oxide semiconductor (230).

The conductor (240) functions as the other of the source electrode and the drain electrode. As the conductor (240), a conductor described in the item of <<Conductor>> described below can be used in a single layer or a laminated form. For example, a highly conductive conductive material such as tungsten can be used as the conductor (240).

As with the conductor (260), it is preferable to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen for the conductor (240). For example, titanium nitride or tantalum nitride can be used. By using this configuration, it is possible to reduce excessive oxidation of the conductor (240) due to the oxide semiconductor (230).

In addition, for example, a structure in which tungsten is laminated on titanium nitride may be used. By providing tungsten in this manner, the conductivity of the conductor (240) can be improved so that it can function sufficiently as a wiring (BL).

It is preferable that the conductor (240) be provided so as to be embedded in the insulator (281). At this time, it is preferable that the height of the upper surface of the conductor (240) and the height of the upper surface of the insulator (281) are identical or substantially identical.

The conductor (265) functions as a wiring (WL) electrically connected to the gate of the transistor (200). As the conductor (265), a conductor described in the item of <<Conductor>> described below can be used in a single layer or a laminated layer. For example, a highly conductive conductive material such as tungsten can be used as the conductor (265).

It is preferable that the conductor (265) be provided to be embedded in the insulator (289). At this time, it is preferable that the height of the upper surface of the conductor (265) and the height of the upper surface of the insulator (289) are identical or substantially identical.

In (B) of Fig. 1, the side end of the conductor (265) substantially coincides with the side end of the conductor (260), but the present invention is not limited thereto. For example, the side end of the conductor (265) may be located outside the side end of the conductor (260), or may be located inside the side end of the conductor (260).

Since the insulator (140), the insulator (280), the insulator (281), the insulator (285), the insulator (287), and the insulator (289) function as an interlayer film, it is preferable that they have a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance that occurs between the wirings can be reduced. As the insulator (140), the insulator (280), the insulator (281), the insulator (285), the insulator (287), and the insulator (289), an insulator with a low dielectric constant described in the item of <<Insulator>> described below can be used in a single layer or a laminated form. For example, silicon oxide, silicon oxynitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide having pores, etc. can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable.

In addition, it is preferable that the concentration of impurities such as water and hydrogen in the insulator (140), insulator (280), insulator (281), insulator (285), insulator (287), and insulator (289) be reduced. This makes it possible to suppress impurities such as water and hydrogen from being mixed into the channel formation region of the oxide semiconductor (230).

In addition, it is preferable to use an insulator (280) disposed near the channel formation region that includes oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). By performing heat treatment on the insulator (280) that includes excess oxygen, oxygen can be supplied from the insulator (280) to the channel formation region of the oxide semiconductor (230), thereby reducing oxygen vacancies and V _O H. As a result, the electrical characteristics of the transistor (200) can be stabilized and the reliability can be improved.

[Capacitor element (100)]

The capacitor (100) has a conductor (110), an insulator (130), and a conductor (120). The conductor (110) functions as one of a pair of electrodes (also called a lower electrode) of the capacitor (100), the conductor (120) functions as the other of a pair of electrodes (also called an upper electrode) of the capacitor (100), and the insulator (130) functions as a dielectric of the capacitor (100).

A conductor (110) is provided on an insulator (140). The conductor (110) functions as a wiring (PL) and may be provided by extending in the Y direction, for example. As the conductor (110), a conductor described in the item of <<Conductor>> described below may be used in a single layer or a laminated form. For example, a highly conductive conductive material such as tungsten may be used for the conductor (110). By using a highly conductive conductive material in this way, the conductivity of the conductor (110) is improved, and it can sufficiently function as a wiring (PL).

In addition, it is preferable to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen by laminating it on the conductor (110). For example, it may be a structure in which titanium nitride is laminated on tungsten. By using such a configuration, it is possible to reduce excessive oxidation of the conductor (110) by the insulator (130).

An insulator (130) is provided on the conductor (110). It is preferable to use a high-k material (a material having a high relative permittivity) for the insulator (130).

In addition, as an insulator of a high-k material, an oxide, an oxynitride, an oxynitride, or a nitride containing at least one metal element selected from aluminum, hafnium, zirconium, and gallium may be used. In addition, silicon may be contained in the oxide, oxynitride, oxynitride, or nitride. In addition, an insulating layer made of the above materials may be laminated and used.

For example, as an insulator of a high-k material, aluminum oxide, hafnium oxide, zirconium oxide, an oxide having aluminum and hafnium, an oxynitride having aluminum and hafnium, an oxide having silicon and hafnium, an oxynitride having silicon and hafnium, an oxide having silicon and zirconium, an oxynitride having silicon and zirconium, an oxide having hafnium and zirconium, an oxynitride having hafnium and zirconium, and an oxynitride having hafnium and zirconium can be used. By using such a high-k material, the insulator (130) can be made thick enough to suppress leakage current, and the electrostatic capacitance of the capacitor element (100) can be sufficiently secured.

In addition, it is preferable to laminate and use an insulating layer made of the above materials, and it is preferable to use a laminated structure of a high-k material and a material having a higher dielectric strength than the high-k material. For example, as the insulator (130), an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are laminated in this order can be used. In addition, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are laminated in this order can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are laminated in this order can be used. By laminating and using an insulator having a relatively high dielectric strength such as aluminum oxide, the dielectric strength is improved, so that electrostatic breakdown of the capacitor element (100) can be suppressed.

In addition, a structure may be adopted in which the side end of the conductor (110) and the side end of the insulator (130) substantially coincide with each other. By adopting such a structure, the conductor (110) and the insulator (130) can be formed using the same mask, thereby simplifying the manufacturing process of the memory device.

Alternatively, the insulator (130) may be structured to cover the side end of the conductor (110). This can prevent the conductor (110) and the conductor (120) from being short-circuited.

It is preferable to provide the conductor (120) as described in the item of [Transistor (200)]. Here, since the electrostatic capacitance of the capacitive element (100) depends on the area of the conductor (120), it is preferable to appropriately set the area of the island-shaped conductor (120) according to the design value of the capacitive element (100). For example, by increasing the area of the island-shaped conductor (120), the electrostatic capacitance of the capacitive element (100) can be increased. In this way, by increasing the electrostatic capacitance per unit area of the capacitive element (100), the read operation of the memory device can be performed stably.

<Materials of memory devices>

Below, the constituent materials that can be used in the memory device are described.

<<Board>>

As a substrate forming the transistor (200) and the capacitor element (100), for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. As an insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), a resin substrate, etc. In addition, as a semiconductor substrate, for example, a semiconductor substrate using silicon or germanium as a material, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, etc. In addition, there is a semiconductor substrate having an insulating region inside the semiconductor substrate described above, for example, an SOI (Silicon On Insulator) substrate, etc. In addition, as a conductive substrate, there is a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. In addition, there is a substrate having a metal nitride, a substrate having a metal oxide, etc. In addition, there is a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductive substrate, etc. Alternatively, elements provided on these substrates may be used. Elements provided on the substrate include capacitive elements, resistive elements, switching elements, light-emitting elements, memory elements, etc.

<<Insulator>>

As insulators, there are oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides that have insulating properties.

For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur as the gate insulator becomes thinner. By using a high-k material for the insulator that functions as the gate insulator, the voltage during transistor operation can be reduced while maintaining the physical film thickness. On the other hand, by using a material with low dielectric constant for the insulator that functions as the interlayer film, the parasitic capacitance that occurs between the wiring can be reduced. Therefore, it is advisable to select a material according to the function of the insulator.

Insulators with high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, or nitrides having silicon and hafnium.

Insulators with low dielectric constants include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

In addition, it is preferable that the insulator functioning as a gate insulator be an insulator having a region including oxygen that is released by heating. For example, when silicon oxide or silicon oxynitride having a region including oxygen that is released by heating is in contact with the oxide semiconductor (230), the oxygen vacancy of the oxide semiconductor (230) can be compensated for.

<<Challenge Full Story>>

For the conductor, it is preferable to use a metal element selected from among aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, a nitride containing tungsten, titanium, and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen. In addition, a semiconductor with high electrical conductivity, represented by polycrystalline silicon containing impurity elements such as phosphorus, and a silicide such as nickel silicide may be used.

In addition, the conductive layers formed of the above materials may be laminated and used in multiple layers. For example, a laminated structure may be used in which the material including the above-described metal element and the conductive material including oxygen are combined. In addition, a laminated structure may be used in which the material including the above-described metal element and the conductive material including nitrogen are combined. In addition, a laminated structure may be used in which the material including the above-described metal element, the conductive material including oxygen, and the conductive material including nitrogen are combined.

<<Metal oxide>>

As the oxide semiconductor (230), it is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor. Hereinafter, reference may be made to the above description for the metal oxide that can be applied to the oxide semiconductor (230) according to the present invention.

In addition, in this specification and elsewhere, metal oxides containing nitrogen are sometimes collectively referred to as metal oxides. Additionally, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

Hereinafter, oxides containing indium (In), gallium (Ga), and zinc (Zn) will be described as examples of metal oxides. In addition, oxides containing indium (In), gallium (Ga), and zinc (Zn) are sometimes called In-Ga-Zn oxides.

<Classification of crystal structures>

The crystal structures of oxide semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), single crystal, and poly crystal.

In addition, the crystal structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, it can be evaluated using an XRD spectrum obtained by a GIXD (Grazing-Incidence XRD) measurement. The GIXD method is also called a thin film method or a Seemann-Bohlin method. In addition, in the following, the XRD spectrum obtained by a GIXD measurement is sometimes simply referred to as an XRD spectrum.

For example, in a quartz glass substrate, the shape of the peak of the XRD spectrum is almost symmetrical. On the other hand, in an In-Ga-Zn oxide film having a crystal structure, the shape of the peak of the XRD spectrum is asymmetrical. The asymmetrical shape of the peak of the XRD spectrum indicates the presence of crystals in the film or the substrate. In other words, if the shape of the peak of the XRD spectrum is not symmetrical, the film or the substrate cannot be said to be in an amorphous state.

In addition, the crystal structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by a nanobeam electron diffraction (NBED) method. For example, a halo is observed in the diffraction pattern of a quartz glass substrate, so it can be confirmed that the quartz glass is in an amorphous state. In addition, a spot-shaped pattern, not a halo, is observed in the diffraction pattern of an In-Ga-Zn oxide film formed at room temperature. Therefore, it is presumed that the In-Ga-Zn oxide film formed at room temperature is in an intermediate state that is neither a single crystal nor a polycrystalline nor an amorphous state, and that it cannot be concluded that it is in an amorphous state.

<<Structure of oxide semiconductor>>

In addition, oxide semiconductors are sometimes classified in a different way from the above when focusing on the structure. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors include, for example, the CAAC-OS and nc-OS described above. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductors), amorphous oxide semiconductors, etc.

Here we describe in detail the CAAC-OS, nc-OS, and a-like OS described above.

[CAAC-OS]

CAAC-OS has a plurality of crystal regions, and the plurality of crystal regions are oxide semiconductors whose c-axis is oriented in a specific direction. In addition, the specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the formation surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. In addition, the crystal region refers to a region having periodicity in the atomic arrangement. In addition, if the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region where the lattice arrangement is aligned. In addition, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and the region may have strain. In addition, strain refers to a part where the direction of the lattice arrangement changes between the region where the lattice arrangement is aligned and another region where the lattice arrangement is aligned in the region where the plurality of crystal regions are connected. In other words, CAAC-OS is an oxide semiconductor that has a c-axis orientation and does not have a clear orientation in the a-b plane direction.

In addition, each of the plurality of crystal regions is composed of one or more microcrystals (crystals having a maximum diameter of less than 10 nm). When the crystal region is composed of one microcrystal, the maximum diameter of the crystal region is less than 10 nm. In addition, when the crystal region is composed of a plurality of microcrystals, the maximum diameter of the crystal region may be on the order of several tens of nm.

Also in In-Ga-Zn oxide, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer having indium (In) and oxygen (hereinafter, In layer) and a layer having gallium (Ga), zinc (Zn), and oxygen (hereinafter, (Ga,Zn) layer) are stacked. Also, indium and gallium can substitute for each other. Therefore, indium may be included in the (Ga,Zn) layer. Also, gallium may be included in the In layer. Also, zinc may be included in the In layer. The layered structure is observed as a lattice pattern, for example, in a high-resolution TEM (Transmission Electron Microscope) image.

For example, when performing structural analysis of a CAAC-OS film using an XRD device, in an out-of-plane XRD measurement using a θ/2θ scan, a peak indicating the c-axis orientation is detected at or near 2θ=31°. In addition, the position (value of 2θ) of the peak indicating the c-axis orientation may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

In addition, for example, multiple bright points (spots) are observed in the electron diffraction pattern of a CAAC-OS film. In addition, some spots and others are observed at positions that are point-symmetrical about the spot of the incident electron beam that has passed through the sample (also called a direct spot) as the center of symmetry.

When the crystal region is observed from the above-mentioned specific direction, the lattice arrangement within the crystal region is basically a hexagonal lattice, but the unit cell is not limited to a regular hexagon and may be an irregular hexagon. In addition, there are cases where a lattice arrangement such as a pentagon or a heptagon is included in the above-mentioned deformation. In addition, in CAAC-OS, a clear grain boundary cannot be confirmed even in the vicinity of the deformation. In other words, it can be seen that the formation of the grain boundary is suppressed by the deformation of the lattice arrangement. This is thought to be because CAAC-OS can tolerate deformation due to the fact that the arrangement of oxygen atoms in the a-b plane direction is not dense and the bonding distance between atoms changes due to the substitution of metal atoms.

Also, a crystal structure in which clear grain boundaries are identified is the so-called polycrystal. The grain boundaries become recombination centers, and there is a high possibility that carriers will be captured, causing a decrease in the on-state current of the transistor, a decrease in the field-effect mobility, etc. Therefore, CAAC-OS in which clear grain boundaries are not identified is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of the transistor. Also, in order to form a CAAC-OS, a composition having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that CAAC-OS is unlikely to experience a decrease in electron mobility due to grain boundaries. In addition, since the crystallinity of oxide semiconductors can be reduced due to the mixing of impurities, the creation of defects, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, oxide semiconductors having CAAC-OS have stable physical properties. Therefore, oxide semiconductors having CAAC-OS are resistant to heat and have high reliability. In addition, CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, if CAAC-OS is used in a transistor having a metal oxide in the channel formation region (sometimes called an OS transistor), the degree of freedom in the manufacturing process can be increased.

[nc-OS]

nc-OS has periodicity in the atomic arrangement in a microscopic region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, nc-OS has microscopic crystals. In addition, since the microscopic crystals have a size of, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, they are also called nanocrystals. In addition, in nc-OS, there is no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, nc-OS may not be distinguished from a-like OS or an amorphous oxide semiconductor depending on the analysis method. For example, when performing structural analysis of a nc-OS film using an XRD device, no peak indicating crystallinity is detected in an out-of-plane XRD measurement using a θ/2θ scan. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than the nanocrystal (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to the size of the nanocrystal or smaller than the nanocrystal (for example, 1 nm or more and 30 nm or less), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot is sometimes acquired.

[a-like OS]

a-like OS is an oxide semiconductor having a structure intermediate between nc-OS and amorphous oxide semiconductor. a-like OS has a cavity or low-density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS. In addition, a-like OS has a higher hydrogen concentration in the film than nc-OS and CAAC-OS.

Oxide semiconductors take on various structures, each of which has different characteristics. An oxide semiconductor of one embodiment of the present invention may include two or more types of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a nc-OS, and a CAAC-OS.

<Transistor having oxide semiconductor>

By using the above oxide semiconductor in a transistor, a transistor with high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.

It is preferable to use an oxide semiconductor having a low carrier concentration for the channel formation region of the transistor. For example, the carrier concentration of the oxide semiconductor is 1×10 ¹⁷ cm ^-3 or less, preferably 1×10 ¹⁵ cm ^-3 or less, more preferably 1×10 ¹³ cm ^-3 or less, more preferably 1×10 ¹¹ cm ^-3 or less, more preferably less than 1×10 ¹⁰ cm ^-3 and 1×10 ^-9 cm ^-3 or more. In addition, when lowering the carrier concentration of the oxide semiconductor film, it is preferable to lower the impurity concentration in the oxide semiconductor film and lower the defect state density.

In addition, since high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor films have a low defect state density, the trap state density may also be low.

In addition, charges captured in the trap states of oxide semiconductors take a long time to disappear and sometimes act like fixed charges. Therefore, transistors in which a channel formation region is formed in an oxide semiconductor with a high trap state density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is also desirable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. In addition, an impurity in the oxide semiconductor refers to, for example, a substance other than the main component that constitutes the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be called an impurity.

<Impurity>

Here, the influence of each impurity within the oxide semiconductor is explained.

When silicon or carbon, which is one of the Group 14 elements, is included in an oxide semiconductor, a defect level is formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) is set to 2×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁷ atoms/cm ³ or less.

In addition, when an alkali metal or alkaline earth metal is included in an oxide semiconductor, a defect state may be formed and a carrier may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal tends to have normally-on characteristics. Therefore, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

In addition, when nitrogen is included in the oxide semiconductor, carrier electrons are generated and the carrier concentration increases, making it easy to become n-type. Therefore, a transistor that uses an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Or, when nitrogen is included in the oxide semiconductor, a trap level may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5×10 ¹⁹ atoms/cm ³ , preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, and more preferably 5×10 ¹⁷ atoms/cm ³ or less.

In addition, since hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to become water, there are cases where an oxygen vacancy is formed. When hydrogen enters the oxygen vacancy, there are cases where electrons as carriers are generated. In addition, there are cases where some of the hydrogen bonds with oxygen bonded to a metal atom, electrons as carriers are generated. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. Therefore, it is desirable that the hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 1×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm ³ , and even more preferably less than 1×10 ¹⁸ atoms/cm ³ .

By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

<<Other semiconductor materials>>

The semiconductor material that can be used for the oxide semiconductor (230) is not limited to the metal oxide described above. A semiconductor material having a band gap (a semiconductor material other than a zero gap semiconductor) may be used for the oxide semiconductor (230). For example, it is preferable to use a single-element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, a layered material (also called an atomic layer material, a two-dimensional material, etc.) that functions as a semiconductor, etc. as the semiconductor material. In particular, it is suitable to use a layered material that functions as a semiconductor as the semiconductor material.

Here, in this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. In the layered crystal structure, layers formed by covalent bonds or ionic bonds are laminated by bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer (monolayer), that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in a channel forming region, a transistor with high on-state current can be provided.

Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

For the oxide semiconductor (230), it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specific examples of the transition metal chalcogenide that can be applied as the oxide semiconductor (230) include molybdenum sulfide (typically MoS ₂ ), molybdenum selenide (typically MoSe ₂ ), molybdenum tellurium (typically MoTe ₂ ), tungsten sulfide (typically WS ₂ ), tungsten selenide (typically WSe ₂ ), tungsten tellurium (typically WTe ₂ ), hafnium sulfide (typically HfS ₂ ), hafnium selenide (typically HfSe ₂ ), zirconium sulfide (typically ZrS ₂ ), and zirconium selenide (typically ZrSe ₂ ). By applying the above-described transition metal chalcogenide to an oxide semiconductor (230), a memory device having a high on-state current can be provided.

<Example of a method for manufacturing a semiconductor device>

Next, a method for manufacturing a memory device, which is one embodiment of the present invention, shown in (A) to (D) of Figs. 1 will be described using (A) to (C) of Figs. 2 to 8.

(A) of each drawing is a plan view. In addition, (B) of each drawing is a cross-sectional view corresponding to the part indicated by the dashed-dotted line A1-A2 in (A) of each drawing. In addition, (C) of each drawing is a cross-sectional view corresponding to the part indicated by the dashed-dotted line A3-A4 in (A) of each drawing. In addition, in the plan view of (A) of each drawing, some elements are omitted for clarity of the drawing.

Hereinafter, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed into a film by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In addition, as a sputtering method, there are RF sputtering method that uses high-frequency power as a power source for sputtering, DC sputtering method that uses direct current power, and pulse DC sputtering method that changes the voltage applied to the electrode in a pulsed manner. RF sputtering method is mainly used when forming an insulating film, and DC sputtering method is mainly used when forming a metal conductive film. In addition, pulse DC sputtering method is mainly used when forming a film of compounds such as oxides, nitrides, and carbides by a reactive sputtering method.

In addition, the CVD method can be classified into the plasma CVD (PECVD) method that uses plasma, the thermal CVD (TCVD: Thermal CVD) method that uses heat, and the photo CVD (Photo CVD) method that uses light. In addition, depending on the raw material gas used, it can be classified into the metal CVD (MCVD: Metal CVD) method and the metal organic CVD (MOCVD: Metal Organic CVD) method.

By the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. In addition, since the thermal CVD method does not use plasma, it is a film formation method that can reduce plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitor elements, etc.) included in a memory device may receive charges from plasma and be charged up. At this time, the accumulated charges may cause the wiring, electrodes, elements, etc. included in the memory device to be destroyed. On the other hand, in the case of the thermal CVD method that does not use plasma, since such plasma damage does not occur, the yield of the memory device can be increased. In addition, since the thermal CVD method does not cause plasma damage during film formation, a film with fewer defects can be obtained.

In addition, as ALD methods, thermal ALD methods that perform the reaction of precursors and reactants using only thermal energy, and PEALD methods that use plasma-excited reactants can be used.

The CVD method and the ALD method are different from the sputtering method in which particles emitted from a target, etc. are deposited. Therefore, they are film-forming methods that are less affected by the shape of the object to be treated and have good step coverage. In particular, the ALD method is suitable for covering the surface of an opening with a high aspect ratio, etc., because it has excellent step coverage and thickness uniformity. However, since the ALD method has a relatively slow film-forming speed, it is sometimes desirable to use it in combination with other film-forming methods such as the CVD method that has a fast film-forming speed.

In addition, the CVD method can form a film having an arbitrary composition by changing the flow rate ratio of the raw material gas. For example, the CVD method can form a film with a continuously changed composition by changing the flow rate ratio of the raw material gas while forming a film. When forming a film while changing the flow rate ratio of the raw material gas, the time required for return or pressure adjustment is omitted, so the time required for forming a film can be shortened compared to when forming a film using multiple film forming chambers. Therefore, there are cases where the productivity of the memory device can be increased.

In addition, in the ALD method, a film having an arbitrary composition can be formed by simultaneously introducing multiple different types of precursors. Or, when multiple different types of precursors are introduced, a film having an arbitrary composition can be formed by controlling the number of cycles of each precursor.

First, a substrate (not shown) is prepared, and an insulator (140) is formed on the substrate (see (A) to (C) of FIG. 2). The insulating material described above may be used appropriately for the insulator (140). The film formation of the insulator (140) may be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, a conductor (110) is formed on an insulator (140). The conductor (110) may be formed by appropriately using the conductive material described above. The film forming of the conductor (110) may be formed by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it may be formed by using a CVD method as the conductor (110) to form a laminated film in which tungsten and titanium nitride are formed in this order.

In addition, the conductor (110) may be processed into a shape that extends in the X direction or Y direction. The processing of the conductor (110) may be performed using a lithography method. A dry etching method or a wet etching method may be used for the processing. Processing using a dry etching method is suitable for fine processing.

Next, an insulator (130) is formed on the conductor (110). It is preferable to use the above-described High-k material appropriately for the insulator (130). It is preferable to use a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. appropriately for the film formation of the insulator (130). For example, it is preferable to form a laminated film in which zirconium oxide, aluminum oxide, and zirconium oxide are formed in this order using the ALD method as the insulator (130).

Next, a conductive film to be a conductor (120) is formed on an insulator (130). The conductive material described above may be used appropriately for the conductive film to be the conductor (120). The sputtering method, CVD method, MBE method, PLD method, ALD method, etc. may be used appropriately for the formation of the conductive film to be the conductor (120). For example, as the conductive film to be the conductor (120), it may be preferable to form a laminated film in which titanium nitride and tantalum nitride are formed in this order using the CVD method.

Next, the conductive film to be the conductor (120) is processed to form the conductor (120) (see (A) to (C) of FIG. 2). The formation of the conductor (120) may be performed by a lithography method. A dry etching method or a wet etching method may be used for the processing. Processing by the dry etching method is suitable for microprocessing. Here, the conductor (120) may be formed in an island shape. Since the electrostatic capacitance of the capacitor (100) depends on the area of the conductor (120), it may be appropriate to set the area of the island-shaped conductor (120) according to the design value of the capacitor (100).

In this manner, a capacitor (100) having a conductor (110), an insulator (130), and a conductor (120) can be formed.

In addition, in the lithography method, first, a resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Then, by performing an etching process using the resist mask, a conductor, a semiconductor, or an insulator, etc., can be processed into a desired shape. For example, it is preferable to form a resist mask by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. In addition, an immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and then exposed. In addition, an electron beam or an ion beam may be used instead of the light described above. In addition, a mask is unnecessary when an electron beam or an ion beam is used. In addition, the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after a dry etching process, or performing a dry etching process after a wet etching process.

In addition, as a dry etching device, a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used. The capacitively coupled plasma etching device having parallel plate electrodes may have a configuration that applies a high-frequency voltage to one of the parallel plate electrodes. Or, it may have a configuration that applies a plurality of different high-frequency voltages to one of the parallel plate electrodes. Or, it may have a configuration that applies a high-frequency voltage having the same frequency to each of the parallel plate electrodes. Or, it may have a configuration that applies high-frequency voltages having different frequencies to each of the parallel plate electrodes. Or, a dry etching device having a high-density plasma source can be used. As a dry etching device having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching device can be used.

Next, an insulator (280) is formed on the insulator (130) and the conductor (120) (see (A) to (C) of FIG. 3). The insulating material described above may be suitably used for the insulator (280). The sputtering method, the CVD method, the MBE method, the PLD method, the ALD method, etc. may be suitably used for the film formation of the insulator (280). For example, as the insulator (280), it may be suitably used to form a silicon oxide film using the sputtering method. In addition, it is preferable to perform a CMP (Chemical Mechanical Polishing) treatment on the insulator (280) after the film formation to flatten the upper surface.

Here, since the film thickness of the insulator (280) on the conductor (120) corresponds to the channel length of the transistor (200), it is good to appropriately set the film thickness of the insulator (280) according to the design value of the channel length of the transistor (200).

In addition, by forming a film of the insulator (280) by a sputtering method in an atmosphere containing oxygen, an insulator (280) containing excess oxygen can be formed. In addition, by using a sputtering method that does not require the use of a molecule containing hydrogen as a film forming gas, the hydrogen concentration in the insulator (280) can be reduced. By forming a film of the insulator (280) in this manner, oxygen can be supplied from the insulator (280) to the channel forming region of the oxide semiconductor (230), thereby reducing oxygen vacancies and VoH.

Next, an insulator (281) is formed on the insulator (280). As with the insulator (280), it is preferable to use the insulating material described above for the insulator (281). For the film formation of the insulator (281), a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like is preferably used. For example, as the insulator (281), it is preferable to form a silicon oxide film using a sputtering method. In addition, after forming the insulator (281), it is preferable to perform a CMP process to flatten the upper surface.

Next, a groove-shaped opening reaching the insulator (280) is formed in the insulator (281) (see (A) to (C) of FIG. 3). Since a conductor (240) functioning as a wiring is formed within the opening, it is preferable that the opening be provided to extend in the X direction. It is preferable that the formation of the opening be performed using a lithography method. In addition, a dry etching method or a wet etching method can be used for the etching of the opening. Processing by the dry etching method is suitable for microprocessing.

In addition, it is also possible to configure the insulator (280) to have a laminated structure and provide an insulator that functions as an etching stopper film on the uppermost surface of the insulator (280). For example, when silicon oxide or silicon oxynitride is used for the insulator (281) forming the groove, it is preferable to use silicon nitride, aluminum oxide, or hafnium oxide as the etching stopper film.

Next, a conductive film to be a conductor (240) is formed to fill the opening of the insulator (281). The conductive material described above may be used appropriately for the conductive film to be the conductor (240). The sputtering method, the CVD method, the MBE method, the PLD method, the ALD method, etc. may be used appropriately for the formation of the conductive film to be the conductor (240). For example, it may be preferable to form a laminated film in which tantalum nitride and tungsten are formed in this order using the sputtering method as the conductive film to be the conductor (240).

Next, a part of the conductive film that becomes the conductor (240) on the insulator (281) is removed to form the conductor (240) within the opening of the insulator (281) (see (A) to (C) of FIG. 3). For the formation of the conductor (240), it is preferable to perform CMP treatment on the conductive film that becomes the conductor (240) until the upper surface of the insulator (281) is exposed.

Next, an insulator (285) is formed on the conductor (240) and the insulator (281). As with the insulator (280), the insulating material described above may be suitably used for the insulator (285). For the film formation of the insulator (285), a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like may be suitably used. For example, as the insulator (285), a silicon oxide film may be formed using a sputtering method. In addition, after the film formation of the insulator (285), it is preferable to perform CMP treatment to flatten the upper surface.

Next, a part of the insulator (285), a part of the conductor (240), and a part of the insulator (280) are processed to form an opening (290) that reaches the conductor (120) (see (A) to (C) of FIG. 4). The formation of the opening (290) may be performed by a lithography method. In addition, although the opening (290) in FIG. 4 (A) has a circular shape when viewed from a planar surface, it is not limited thereto. For example, the opening may have a roughly circular shape such as an ellipse, a polygon such as a square, or a shape in which the corners of a polygon such as a square are rounded when viewed from a planar surface.

It is preferable that the width of the opening (290) is fine. For example, it is preferable that the width of the opening (290) is 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and 1 nm or more, or 5 nm or more. In order to finely process the opening (290) in this way, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

Since the opening (290) has a high aspect ratio, it is preferable to process a part of the insulator (285), a part of the conductor (240), and a part of the insulator (280) using anisotropic etching. In particular, processing by a dry etching method is preferable because it is suitable for micro-processing. In addition, the processing may be performed under different conditions.

Next, heat treatment may be performed. The heat treatment may be performed at 250°C or more and 650°C or less, preferably 300°C or more and 500°C or less, and more preferably 320°C or more and 450°C or less. In addition, the heat treatment is performed in a nitrogen gas atmosphere or an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be used at about 20%. In addition, the heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the released oxygen after the heat treatment is performed in a nitrogen gas atmosphere or an inert gas atmosphere. By performing the heat treatment as described above, impurities such as water included in the insulator (280), etc., can be reduced before the deposition of the oxide semiconductor film (230A) described later.

In addition, it is preferable that the gas used in the above heat treatment be highly purified. For example, it is preferable that the moisture content contained in the gas used in the above heat treatment be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture, etc. can be prevented from entering the insulator (280) or the like as much as possible.

Next, an oxide semiconductor film (230A) is formed in contact with the bottom surface and inner wall of the opening (290) (see (A) to (C) of FIG. 5). For the oxide semiconductor film (230A), it is preferable to use an appropriate metal oxide that can be used for the oxide semiconductor (230) described above. For the formation of the oxide semiconductor film (230A), a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like is preferably used. Here, it is preferable that the oxide semiconductor film (230A) is formed in contact with the bottom surface and inner wall of the opening (290) having a large aspect ratio. Therefore, for the formation of the oxide semiconductor film (230A), it is preferable to use a formation method having good coverage, and it is more preferable to use a CVD method or an ALD method. For example, as the oxide semiconductor film (230A), it is preferable to form an In-Ga-Zn oxide film using an ALD method. In addition, details of a method for forming a metal oxide film using an ALD method will be described in a later embodiment.

Here, the oxide semiconductor film (230A) is preferably formed in contact with the upper surface of the conductor (120), the side surface of the insulator (280), the side surface of the conductor (240), the side surface of the insulator (285), and the upper surface of the insulator (285). By forming the oxide semiconductor film (230A) in contact with the conductor (120), the conductor (120) functions as one of the source electrode and the drain electrode of the transistor (200). In addition, by forming the oxide semiconductor film (230A) in contact with the conductor (240), the conductor (240) functions as the other of the source electrode and the drain electrode of the transistor (200).

Next, an insulating film (250A) is formed in contact with the upper surface of the oxide semiconductor film (230A) (see (A) to (C) of FIG. 5). It is preferable to use the insulating material described above for the insulating film (250A). It is preferable to use a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like for the formation of the insulating film (250A). Here, it is preferable that the insulating film (250A) is formed in contact with the oxide semiconductor film (230A) provided on the inside of the opening (290) having a large aspect ratio. Therefore, it is preferable to use a film formation method having good covering properties for the formation of the insulating film (250A), and it is more preferable to use a CVD method or an ALD method. For example, it is preferable to form a silicon oxide film using an ALD method as the insulating film (250A).

Here, it is preferable that the formation of the insulating film (250A) is performed continuously without exposing it to the atmosphere after the formation of the oxide semiconductor film (230A). For example, a multi-chamber type deposition device may be used. As a result, the inclusion of impurities such as hydrogen into the film between each deposition process for the oxide semiconductor film (230A) and the insulating film (250A) can be reduced.

Next, it is preferable to perform a heat treatment. The heat treatment is preferably performed in a temperature range in which the oxide semiconductor film (230A) does not polycrystallize, and is preferably performed at a temperature of 250° C. or more and 650° C. or less, preferably 400° C. or more and 600° C. or less. In addition, the heat treatment is performed in a nitrogen gas atmosphere or an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to use about 20% of oxygen gas. In addition, the heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to supplement the released oxygen after performing the heat treatment in a nitrogen gas atmosphere or an inert gas atmosphere.

In addition, it is preferable that the gas used in the above heat treatment be highly purified. For example, it is preferable that the moisture content contained in the gas used in the above heat treatment be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture, etc. can be prevented from entering the oxide semiconductor film (230A) or the like as much as possible.

Here, it is preferable to perform the heat treatment in a state where the insulator (280) containing excess oxygen is provided in contact with the oxide semiconductor film (230A). By performing the heat treatment in this manner, oxygen can be supplied from the insulator (280) to the channel formation region of the oxide semiconductor (230), thereby reducing oxygen vacancies and VoH.

In addition, although the heat treatment was performed after the formation of the insulating film (250A) in the above, the present invention is not limited to this. It may be configured to perform the heat treatment in a subsequent process.

Next, the oxide semiconductor film (230A) and the insulating film (250A) are processed using a lithography method to form the oxide semiconductor (230) and the insulator (250) (see (A) to (C) of FIG. 6). As a result, a part of the oxide semiconductor (230) is formed over the opening (290) and comes into contact with a part of the upper surface of the insulator (285). In addition, a part of the insulator (250) is formed over the opening (290). In this way, by forming the oxide semiconductor (230) and the insulator (250) in one piece, as shown in (A) of FIG. 6, the side edge of the oxide semiconductor (230) and the side edge of the insulator (250) substantially coincide when viewed from the plane. By forming it in this configuration, the oxide semiconductor (230) and the insulator (250) can be formed using the same mask, which simplifies the manufacturing process of the memory device.

In addition, although the configuration in which the oxide semiconductor (230) and the insulator (250) are formed simultaneously after the oxide semiconductor film (230A) and the insulating film (250A) are formed in the foregoing has been shown, the present invention is not limited thereto. For example, a configuration in which the insulating film (250A) is formed after the oxide semiconductor (230) is formed may be used. In this case, since the side end of the oxide semiconductor (230) is covered with the insulating film (250A), short-circuiting between the oxide semiconductor (230) and the conductor (260) can be prevented.

Next, a conductive film to become a conductor (260) is formed to fill the concave portion of the insulator (250). The conductive material described above may be used appropriately for the conductive film to become the conductor (260). The sputtering method, the CVD method, the MBE method, the PLD method, the ALD method, or the like may be used appropriately for the formation of the conductive film to become the conductor (260). Here, it is preferable that the conductive film to become the conductor (260) be formed in contact with the insulator (250) provided on the inside of the opening (290) having a large aspect ratio. Therefore, it is preferable to use a film formation method having good covering or filling properties for the formation of the conductive film to become the conductor (260), and it is more preferable to use the CVD method or the ALD method. For example, it is preferable to form a titanium nitride film using the CVD method or the ALD method as the conductive film to become the conductor (260).

In addition, when a conductive film to be a conductor (260) is formed using a CVD method, there are cases where the average surface roughness of the upper surface of the conductive film to be a conductor (260) increases. In this case, it is preferable to flatten the conductive film to be a conductor (260) using a CMP method. At this time, before performing the CMP treatment, a silicon oxide film or a silicon oxynitride film may be formed on the conductive film to be a conductor (260), and the CMP treatment may be performed until the silicon oxide film or the silicon oxynitride film is removed.

In addition, in the above, the conductive film that becomes the conductor (260) is provided to fill the opening (290), but the present invention is not limited thereto. For example, there is a case where a concave portion reflecting the shape of the opening (290) is formed in the central portion of the conductive film that becomes the conductor (260). In addition, the concave portion may be filled with an inorganic insulating material, etc.

Next, the conductive film that becomes the conductor (260) is processed to form the conductor (260) (see (A) to (C) of FIG. 7). The formation of the conductor (260) can be performed by a lithography method. A dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for micro-processing.

Here, as shown in (A) of Fig. 7, it is preferable that the side end of the conductor (260) is positioned closer to the side end of the oxide semiconductor (230) and the side end of the insulator (250) when viewed from the plane. As a result, the conductor (260) and the oxide semiconductor (230) can be prevented from being short-circuited.

In this manner, a transistor (200) having a conductor (120), a conductor (240), an oxide semiconductor (230), an insulator (250), and a conductor (260) can be formed.

In addition, in the above, the configuration in which the oxide semiconductor film (230A) and the insulating film (250A) are formed, and then the oxide semiconductor (230) and the insulator (250) are formed, and then the conductive film to become the conductor (260) is formed, is shown, but the present invention is not limited thereto. For example, the configuration in which the oxide semiconductor film (230A), the insulating film (250A), and the conductive film to become the conductor (260) are continuously formed and the oxide semiconductor (230), the insulator (250), and the conductor (260) are pattern-formed may be used. In this case, after the oxide semiconductor (230), the insulator (250), and the conductor (260) are formed by photolithography, it is preferable to process the conductor (260) by performing the photolithography process once again so that the side edge of the conductor (260) is positioned on the inner side of the oxide semiconductor (230) and the insulator (250).

Next, an insulating film to become an insulator (287) is formed by covering the conductor (260), the insulator (250), the oxide semiconductor (230), and the insulator (285). For the insulating film to become the insulator (287), the insulating material described above may be used appropriately, similarly to the insulator (280). For the formation of the insulating film to become the insulator (287), a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used appropriately. For example, a silicon oxide film may be formed using a sputtering method as the insulating film to become the insulator (287).

Next, CMP treatment is performed on the insulating film to become the insulator (287) to form the insulator (287) (see (A) to (C) of FIG. 8). It is preferable that the CMP treatment is performed until the upper surface of the conductor (260) is exposed. At this time, it is preferable that the height of the upper surface of the conductor (260) and the height of the upper surface of the insulator (287) are identical or substantially identical.

Next, an insulator (289) is formed on the insulator (287) and the conductor (260). As with the insulator (280), the insulating material described above may be suitably used for the insulator (289). For the film formation of the insulator (289), a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like may be suitably used. For example, as the insulator (289), a silicon oxide film may be formed using a sputtering method. In addition, after the film formation of the insulator (289), it is preferable to perform CMP treatment to flatten the upper surface.

Next, a groove-shaped opening is formed in the insulator (289) to reach the conductor (260) and the insulator (287) (see (A) to (C) of FIG. 1). Since a conductor (265) functioning as a wiring is formed in the opening, it is preferable that the opening be provided to extend in the Y direction. It is preferable that the formation of the opening be performed using a lithography method. In addition, a dry etching method or a wet etching method can be used for the etching of the opening. Processing by the dry etching method is suitable for microprocessing.

Next, a conductive film to be a conductor (265) is formed to fill the opening of the insulator (289). The conductive material described above may be used appropriately for the conductive film to be the conductor (265). The sputtering method, the CVD method, the MBE method, the PLD method, the ALD method, etc. may be used appropriately for the formation of the conductive film to be the conductor (265). For example, it may be preferable to form a laminated film in which titanium nitride and tungsten are formed in this order using the CVD method as the conductive film to be the conductor (265).

Next, a part of the conductive film that becomes the conductor (265) on the insulator (289) is removed to form the conductor (265) within the opening of the insulator (289) (see (A) to (C) of FIG. 1). For the formation of the conductor (265), it is preferable to perform CMP treatment on the conductive film that becomes the conductor (265) until the upper surface of the insulator (289) is exposed.

In this way, a memory device having a transistor (200) and a capacitor element (100) as shown in (A) to (D) of FIG. 1 can be manufactured.

<Variations of memory devices>

Below, an example of a memory device, which is one form of the present invention, is described using FIG. 9.

The memory devices shown in (A) to (C) of Fig. 9 are modifications of the memory devices shown in (A) to (D) of Fig. 1. (A) to (C) of Fig. 9 correspond to (B) to (D) of Fig. 1, and in the memory device shown in Fig. 9, structures having the same function as the structures constituting the memory device shown in Fig. 1 are given the same reference numerals. In addition, in this item, as the constituent materials of the memory device, the materials described in detail in <Configuration Examples of Memory Devices> can be used.

The memory device shown in (A) to (C) of FIG. 9 differs from the memory device shown in (A) to (D) of FIG. 1 in that it has an insulator (254). The insulator (254) functions as a gate insulator together with the insulator (250).

An insulator (254) is provided between the insulator (250) and the conductor (260). In addition, it is preferable that the insulator (254) be provided to cover the side end of the oxide semiconductor (230) and the side end of the insulator (250). In this case, it is preferable that the insulator (254) be in contact with the upper surface and the side surface of the insulator (250), the side surface of the oxide semiconductor (230), the upper surface of the insulator (285), the lower surface of the conductor (260), and the lower surface of the insulator (287).

It is preferable that the insulator (254) have a barrier property against oxygen. It is more preferable that the insulator (254) have a barrier property against hydrogen. As such an insulator, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a laminated form. Specifically, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, indium gallium zinc oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and silicon (hafnium silicate), and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

In addition, in this specification and elsewhere, barrier property refers to a function of inhibiting the diffusion of a corresponding substance (also called low permeability) or a function of capturing and fixing a corresponding substance (also called gettering).

Since the insulator (254) has a barrier property against oxygen, it is possible to suppress oxygen included in the channel formation region of the insulator (250) and the oxide semiconductor (230) from diffusing into the conductor (260) and forming oxygen vacancies in the channel formation region of the oxide semiconductor (230). In addition, it is possible to suppress oxygen included in the channel formation region of the insulator (250) and the oxide semiconductor (230) from diffusing into the conductor (260) and oxidizing the conductor (260). Here, it is preferable that the insulator (254) be at least less permeable to oxygen than the insulator (280). For example, it is preferable to use silicon nitride formed by the PEALD method as the insulator (254).

In addition, since the insulator (254) has a barrier property against hydrogen, diffusion of impurities such as hydrogen from a layer above the insulator (254) into the channel formation region of the oxide semiconductor (230) can be reduced. Accordingly, oxygen vacancies and V _O H in the channel formation region of the oxide semiconductor (230) can be reduced. As a result, the electrical characteristics of the transistor (200) can be stabilized and the reliability can be improved.

In addition, as described above, an insulator having a barrier property against at least one of oxygen and hydrogen (hereinafter, sometimes referred to as a barrier insulating film) may be provided by laminating one or more of the insulators (140), (280), (281), (285), (287), and (289) that function as an interlayer film. For example, it may be provided on the lower surface of the insulator (280), and in this case, the barrier insulating film is provided in contact with the upper surface of the insulator (130), the upper surface of the conductor (120), and the side surface of the conductor (120). In addition, for example, it may be provided on the upper surface of the insulator (140), and in this case, the barrier insulating film is provided in contact with the lower surface of the conductor (110). By providing the barrier insulating film in this way, it is possible to reduce diffusion of impurities such as hydrogen from a layer lower than the insulator (140) into the channel formation region of the oxide semiconductor (230).

According to one embodiment of the present invention, a novel transistor, a novel semiconductor device, and a novel memory device can be provided. Or, a memory device capable of miniaturization or high integration can be provided. Or, a memory device having good frequency characteristics can be provided. Or, a memory device having a high operating speed can be provided. Or, a memory device having good reliability can be provided. Or, a memory device having low power consumption can be provided. Or, a memory device having a transistor with high on-state current can be provided. Or, a memory device having little variation in transistor characteristics can be provided. Or, a memory device having good electrical characteristics can be provided.

The memory cell (150) having the transistor (200) and the capacitor element (100) described in this embodiment can be used as a memory cell of a memory device. The transistor (200) is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor (200) has a low off-state current, by using it in a memory device, memory contents can be maintained for a long period of time. That is, since a refresh operation is unnecessary or the frequency of the refresh operation is very low, the power consumption of the memory device can be sufficiently reduced. In addition, since the frequency characteristic of the transistor (200) is high, reading and writing of the memory device can be performed at high speed.

Also, an example of a memory device that connects two memory cells (150) (hereinafter, referred to as memory cell (150a) and memory cell (150b)) to a common wiring will be described using Figs. 10(A) and (B). Fig. 10(A) is a plan view of the memory device. Also, Fig. 10(B) is a cross-sectional view of a portion indicated by a dashed-dotted line A1-A2 in Fig. 10(A). Also, in the plan view of Fig. 10(A), some elements are omitted for clarity of the drawing.

Here, the memory cell (150a) and the memory cell (150b) shown in (A) and (B) of Fig. 10 have the same configuration as the memory cell (150). The memory cell (150a) has a capacitive element (100a) and a transistor (200a), and the memory cell (150b) has a capacitive element (100b) and a transistor (200b). Therefore, in the memory devices shown in (A) and (B) of Fig. 10, the same reference numerals are given to structures having the same function as the structure constituting the memory device shown in Fig. 1. In addition, in this item, as the constituent material of the memory device, the materials described in detail in <Configuration Example of Memory Device> can be used.

As shown in (A) and (B) of Fig. 10, a conductor (265) functioning as a wiring (WL) is provided to each of the memory cell (150a) and the memory cell (150b). In addition, a conductor (240) functioning as a part of the wiring (BL) is provided in common to the memory cell (150a) and the memory cell (150b). That is, the conductor (240) is in contact with the oxide semiconductor (230) of the memory cell (150a) and the oxide semiconductor (230) of the memory cell (150b).

Here, the memory device shown in (A) and (B) of FIG. 10 has a conductor (245) and a conductor (246) that are electrically connected to the memory cell (150a) and the memory cell (150b) and function as a plug (which may also be called a connection electrode). The conductor (245) is arranged in an opening formed in the insulator (280) and the insulator (140) and is in contact with the lower surface of the conductor (240). In addition, the conductor (246) is arranged in an opening formed in the insulator (289), the insulator (287), and the insulator (285) and is in contact with the upper surface of the conductor (240). In addition, a conductive material that can be used for the conductor (240) can be used for the conductor (245) and the conductor (246).

Here, the conductor (245) and the conductor (246) function as a plug or a wire for electrically connecting circuit elements, wiring, electrodes, or terminals such as switches, transistors, capacitive elements, inductors, resistor elements, and diodes, and the memory cells (150a) and the memory cells (150b). For example, the conductor (245) may be electrically connected to a sense amplifier provided below the memory device shown in Fig. 10, and the conductor (246) may be electrically connected to a memory device such as the above provided above the memory device shown in Fig. 10. In this case, the conductor (245) and the conductor (246) function as a part of the wiring (BL). By providing a memory device or the like above or below the memory device shown in Fig. 10 in this way, the memory capacity per unit area can be increased.

In addition, the memory cell (150a) and the memory cell (150b) are configured to be line-symmetrical with the vertical bisector of the dashed-dotted line A1-A2 as the axis of symmetry. Accordingly, the transistor (200a) and the transistor (200b) are also arranged at line-symmetrical positions with the conductor (245) and the conductor (246) therebetween. Here, the configuration is such that one of the source electrode and the drain electrode of the transistor (200a) and one of the source electrode and the drain electrode of the transistor (200b) are also served by the conductor (240). In addition, the transistor (200a) and the transistor (200b) are configured to share the conductor (245) and the conductor (246) that function as a plug. In this way, by applying the above-described configuration to the connection of two transistors and a plug, it is possible to provide a memory device capable of miniaturization or high integration.

In addition, the conductor (110) functioning as a wiring (PL) may be provided to each of the memory cell (150a) and the memory cell (150b), or may be provided commonly to the memory cell (150a) and the memory cell (150b). However, as shown in (B) of Fig. 10, the conductor (110) is provided apart from the conductor (245), and the conductor (110) and the conductor (245) are prevented from being short-circuited.

In addition, a memory cell array can be configured by arranging memory cells (150) in a three-dimensional matrix. As an example of a memory cell array, a memory device in which 4×2×2 memory cells (150) are arranged in the X direction, the Y direction, and the Z direction is shown in (A) and (B) of Figs. (A) of Fig. 11 is a plan view of the memory device. In addition, (B) of Fig. 11 is a cross-sectional view of a portion indicated by the dashed-dotted line A1-A2 in (A) of Fig. 11. In addition, some elements are omitted in the plan view of (A) of Fig. 11 for clarity of the drawing.

Here, the memory cells (150a) to (150d) shown in (A) and (B) of Fig. 11 have the same configuration as the memory cell (150). The memory cell (150a) has a capacitive element (100a) and a transistor (200a), the memory cell (150b) has a capacitive element (100b) and a transistor (200b), the memory cell (150c) has a capacitive element (100c) and a transistor (200c), and the memory cell (150d) has a capacitive element (100d) and a transistor (200d). Therefore, in the memory devices shown in (A) and (B) of Fig. 11, structures having the same function as the structure constituting the memory device shown in Fig. 1 are given the same reference numerals. In addition, in this item, as the constituent materials of the memory device, the materials described in detail in <Configuration Example of Memory Device> can be used.

Hereinafter, a memory device composed of memory cells (150a) to memory cells (150d) is called a memory unit. The memory device shown in (A) and (B) of Fig. 11 has a memory unit (160a) to a memory unit (160d). Also, hereafter, the memory unit (160a) to the memory unit (160d) may be collectively called a memory unit (160). The memory unit (160b) is provided above the memory unit (160a). The memory unit (160c) is provided adjacent to the memory unit (160a) in the y-axis direction. The memory unit (160d) is provided above the memory unit (160c).

As shown in (B) of Fig. 11, the memory unit (160) has memory cells (150c) arranged on the outside of memory cells (150a) centered around conductors (245), and memory cells (150d) arranged on the outside of memory cells (150b). That is, in the memory device shown in Fig. 10, it can also be said to be a memory device in which memory cells (150c) are provided adjacent to memory cells (150a), and memory cells (150d) are provided adjacent to memory cells (150b).

As shown in (A) and (B) of FIG. 11, a conductor (265) functioning as a wiring (WL) is shared between adjacent memory cells (150) in the Y direction. In addition, a conductor (240) functioning as a part of a wiring (BL) is shared within the same memory unit. The conductor (240) is commonly provided to the memory cells (150a) to (150d). That is, the conductor (240) contacts the oxide semiconductor (230) of each of the memory cells (150a) to (150d).

A conductor (245) is provided between conductors (240) of adjacent memory units in the Z-axis direction. For example, as shown in (B) of FIG. 11, the conductor (245) is provided in contact with the upper surface of the conductor (240) of the memory unit (160a) and the lower surface of the conductor (240) of the memory unit (160b). In this way, a wiring (BL) is formed by the conductor (240) and the conductor (245) provided in each memory unit (160). The conductor (245) is electrically connected to a sense amplifier provided below the memory device shown in FIG. 11. In this way, by stacking a plurality of memory units in the memory device shown in FIG. 11, the memory capacity per unit area can be increased.

In addition, the memory cell (150a) and the memory cell (150c), and the memory cell (150b) and the memory cell (150d) are configured to be line-symmetrical with the vertical bisector of the dashed-dotted line A1-A2 as the axis of symmetry. Accordingly, the transistor (200a) and the transistor (200c), and the transistor (200b) and the transistor (200d) are also arranged at line-symmetrical positions with the conductor (245) therebetween. Here, the configuration is such that one of the source electrode and the drain electrode of the transistor (200a) to the transistor (200d) is also performed by the conductor (240). In addition, the transistor (200a) to the transistor (200d) are configured to share the conductor (245) that functions as a plug. In this way, by applying the above-described configuration to the connection of four transistors and the plug, it is possible to provide a memory device capable of miniaturization or high integration.

As shown in Fig. 11, by stacking a plurality of memory cells, cells can be integrated and arranged without increasing the occupied area of the memory cell array. In other words, a 3D memory cell array can be configured.

A memory device having a 3D memory cell array will be described in detail in a later embodiment.

The configurations, methods, etc. shown in this embodiment can be implemented by appropriately combining at least some of them with other embodiments described in this specification.

(Embodiment 2)

In this embodiment, a metal oxide (hereinafter, sometimes referred to as oxide semiconductor or oxide) that can be applied to a semiconductor layer of a transistor of a memory device shown in the preceding embodiment and a film formation method thereof are described using FIGS. 12 to 15.

In one embodiment of the semiconductor device of the present invention, it is preferable to use a metal oxide having high crystallinity as the metal oxide including the channel forming region. In addition, it is preferable that the crystal has a crystal structure in which a plurality of layers (for example, a first layer, a second layer, and a third layer) are laminated. That is, the crystal has a layered crystal structure (also called a layered crystal or a layered structure). At this time, the direction of the c-axis of the crystal becomes the direction in which the plurality of layers are laminated.

In order to form a metal oxide having the above layered crystal structure, it is desirable to deposit atoms one layer at a time. For example, an ALD (Atomic Layer Deposition) method can be used as a method for forming a metal oxide.

Since the ALD method can deposit atoms one layer at a time by utilizing the self-controlling property of precursor molecules or atoms included in the precursor, it has the effects of being able to form a very thin film, forming a film on a structure with a high aspect ratio, forming a film with fewer defects such as pinholes, forming a film with excellent coverage, and forming a film at low temperatures, etc. In addition, the ALD method also includes the thermal ALD method, which is a film forming method using heat, and the plasma ALD (PEALD: Plasma Enhanced ALD) method, which is a film forming method using plasma. By using plasma, a film can be formed at a lower temperature, which is sometimes preferable. In addition, the precursor used in the ALD method sometimes contains elements such as carbon or chlorine. Therefore, a film provided by the ALD method sometimes contains more elements such as carbon or chlorine than a film provided by another film forming method. Additionally, quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry.

Unlike other film-forming methods in which particles emitted from a target are deposited, the ALD method is a film-forming method in which a film is formed by a reaction on the surface of a target. Therefore, it is a film-forming method that is difficult to be affected by the shape of a target and has good step coverage. In particular, the ALD method has excellent step coverage and thickness uniformity, so it is suitable for covering the surface of an opening with a high aspect ratio.

<Method for forming a metal oxide film using ALD method>

Here, a method for forming a metal oxide film using the ALD method that can be used in one embodiment of the present invention is described.

Here, an example of a method for forming a film of a metal oxide having a three-layered crystal structure using the ALD method is described using Figs. 12(A) to (E). First, a precursor (611a) is introduced into a chamber, and the precursor (611a) is adsorbed onto the surface of a substrate (610) (see Fig. 12(A) . Hereinafter, the above process may be referred to as the first step). Here, as shown in Fig. 12(A), since the precursor (611a) is adsorbed onto the surface of the substrate (610), a self-stopping mechanism of the surface chemical reaction operates, so that the precursor (611a) is not further adsorbed onto the layer of the precursor (611a) on the substrate (610). In addition, an appropriate range of the substrate temperature in which the self-stopping mechanism of the surface chemical reaction operates is also called the ALD Window. The ALD Window is determined by the temperature characteristics of the precursor, vapor pressure, decomposition temperature, etc., but is, for example, in the range of 100°C to 600°C, preferably 200°C to 400°C.

Next, an inert gas (such as argon, helium, or nitrogen) is introduced into the chamber, and excess precursor (611a) and reaction products are discharged from the chamber (hereinafter, the above process may be referred to as the second step). In addition, instead of introducing an inert gas into the chamber, excess precursor and reaction products may be discharged from the chamber by vacuum exhaust. The second step is also referred to as a purge.

Next, a reactant (612a) (e.g., an oxidizing agent (ozone (O ₃ ), oxygen (O ₂ ), water (H ₂ O), and plasma, radicals, ions, etc. thereof)) is introduced into the chamber to react with the precursor (611a) adsorbed on the surface of the substrate (610), thereby causing some of the components included in the precursor (611a) to be removed while leaving the constituent molecules of the precursor (611a) adsorbed on the substrate (610) (see (B) of FIG. 12; the above process may be referred to as the third step hereinafter). As a result, a layer of an oxide (613a) formed by oxidizing a part of the precursor (611a) is formed on the surface of the substrate (610).

Next, by introducing an inert gas or by vacuum exhaust, excess reactant (612a) or reaction products, etc. are discharged from the chamber (hereinafter, the above process is sometimes referred to as the fourth step).

Next, a precursor (611b) having a different metal element from the precursor (611a) is introduced, and the same process as the first step is performed, and the precursor (611b) is adsorbed onto the surface of the layer of oxide (613a) (see (C) of FIG. 12). Here, as shown in (C) of FIG. 12, since the precursor (611b) is adsorbed onto the layer of oxide (613a), a self-stopping mechanism of the surface chemical reaction operates, so that the precursor (611b) is not further adsorbed onto the layer of the precursor (611b) on the substrate (610).

Next, as in the second step, excess precursor (611b) and reaction products, etc. are discharged from the chamber by introduction of an inert gas or vacuum exhaust.

Next, similar to the third step, a reactant (612b) is introduced into the chamber. Here, the reactant (612b) may be the same as the reactant (612a), or may be a different one (see (D) of Fig. 12). As a result, a layer of an oxide (613b) formed by oxidizing a portion of the precursor (611b) is formed on the layer of the oxide (613a).

Next, as in the fourth step, excess reactant (612b) and reaction products, etc. are discharged from the chamber by introduction of an inert gas or vacuum exhaust.

Also, similarly, steps 1 to 4 can be performed, and a layer of oxide (613c) can be formed on a layer of oxide (613b). In this way, by repeatedly performing the process of forming oxides (613a) to oxides (613c), a metal oxide having a layered crystal structure in which the stacked structure of oxides (613a) to oxides (613c) is repeated can be formed (see (E) of FIG. 12). That is, steps 1 to 4 can be performed as a set to form layers of oxides, and by repeating the set, a layered crystal structure in which a plurality of oxide layers are stacked can be formed.

In addition, the thickness of the metal oxide of the layered crystal structure is preferably 1 nm or more and less than 100 nm, and preferably 3 nm or more and less than 20 nm.

In addition, in forming a metal oxide having a layered crystal structure, it is preferable to perform the process shown in Fig. 12 while heating the substrate. For example, it is preferable to set the substrate temperature to 200°C or higher and 600°C or lower, preferably 300°C or higher and lower than the decomposition temperature of the precursor. In addition, when performing film formation by the ALD method using a plurality of different precursors, it is preferable to set the substrate temperature to a temperature lower than the lowest decomposition temperature among the decomposition temperatures of the plurality of precursors. Thereby, the plurality of precursors used in the film formation by the ALD method can be adsorbed onto the target object (e.g., substrate, etc.) without being decomposed individually.

By performing the film formation while heating the substrate in this temperature range, impurities such as hydrogen or carbon contained in the precursor and the reactant can be removed from the metal oxide in each process of steps 1 to 4. For example, carbon in the metal oxide can be released as CO ₂ and CO, and hydrogen in the metal oxide can be released as H ₂ O. In addition, at the same time as the removal of the impurities, rearrangement of metal atoms and oxygen atoms is performed, and each oxide layer can be arranged with a high degree of order. Therefore, a metal oxide having a layered crystal structure with high crystallinity can be formed.

In order to perform film formation while heating the substrate in the above temperature range, it is preferable that the precursor used for the film formation has a high decomposition temperature. For example, it is preferable that the decomposition temperature of the precursor is 200°C or more and 700°C or less, and it is more preferable that it is 300°C or more and 600°C or less. As the precursor having such a high decomposition temperature, it is preferable to use a precursor formed of an inorganic substance (hereinafter referred to as an inorganic precursor). In general, inorganic precursors tend to have a higher decomposition temperature than precursors formed of an organic substance (hereinafter referred to as an organic precursor), and therefore there are cases where the ALD Window is provided in the above temperature range. In addition, since the inorganic precursor does not contain impurities such as hydrogen or carbon, it is possible to prevent the concentration of impurities such as hydrogen or carbon in the metal oxide to be filmed from increasing.

In addition, it is preferable to perform heat treatment after the film formation of the metal oxide. In particular, it is preferable to continuously perform heat treatment without exposure to the outside after film formation by the ALD method. The heat treatment may be performed at 100°C or more and 1200°C or less, preferably 200°C or more and 1000°C or less, more preferably 250°C or more and 650°C or less, more preferably 300°C or more and 600°C or less, more preferably 400°C or more and 550°C or less, and more preferably 420°C or more and 480°C or less. In addition, the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. In addition, the heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the lost oxygen after performing the heat treatment in a nitrogen gas atmosphere or an inert gas atmosphere.

By performing heat treatment in this manner, impurities such as hydrogen or carbon contained in the metal oxide can be removed. For example, carbon in the metal oxide can be released as CO ₂ and CO, and hydrogen in the metal oxide can be released as H ₂ O. In addition, at the same time as the removal of the impurities, rearrangement of metal atoms and oxygen atoms is performed, and crystallinity can be improved. Therefore, a metal oxide having a layered crystal structure with high crystallinity can be formed.

In addition, after the deposition of the metal oxide, it is preferable to perform a treatment to reduce the concentration of impurities in the metal oxide by performing microwave treatment in an atmosphere containing oxygen. In addition, the impurities may particularly include hydrogen and carbon. Here, microwave treatment refers to a treatment using a device having a power source that generates high-density plasma using microwaves, for example.

By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be converted into plasma using high frequency such as microwave or RF, and the oxygen plasma can be acted on. In addition, the oxygen acting on the metal oxide has various forms such as an oxygen atom, an oxygen molecule, an oxygen ion, and an oxygen radical (also called an O radical, an atom or molecule having an unpaired electron, or an ion). In addition, the oxygen acting on the metal oxide preferably has one or more of the above-described forms, and an oxygen radical is particularly suitable.

In addition, it is preferable that the concentration of impurities in the metal oxide be further reduced by heating the substrate when performing microwave treatment in an atmosphere containing the oxygen described above. The heating of the substrate described above is preferably performed at a temperature of 100°C or higher and 650°C or lower, preferably 200°C or higher and 600°C or lower, and more preferably 300°C or higher and 450°C or lower.

By heating the substrate when performing microwave treatment in an atmosphere containing the above-described oxygen, the carbon concentration in the metal oxide obtained by SIMS can be reduced to less than 1×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ .

In addition, although the configuration for performing microwave treatment in an oxygen-containing atmosphere on a metal oxide has been exemplified above, it is not limited thereto. For example, microwave treatment may be performed on an insulating film located near a metal oxide, more specifically, a silicon oxide film, in an oxygen-containing atmosphere. For example, in the process shown in FIG. 5 according to the above embodiment, microwave treatment may be performed after forming an insulating film (250A). By performing microwave treatment on a silicon oxide film in an oxygen-containing atmosphere, hydrogen contained in the silicon oxide film can be released to the outside as H ₂ O. By releasing hydrogen from a silicon oxide film located near a metal oxide, a highly reliable semiconductor device can be provided.

In addition, although Fig. 12 describes a structure in which a laminated structure of oxides (613a) to (613c) is repeated, the present invention is not limited thereto. For example, a metal oxide in which a single layer, two layers, or four or more layers of oxides are repeatedly formed may be used.

In addition, unless specifically described in this specification or elsewhere, when ozone, oxygen, or water are used as a reactant or oxidizing agent, they are not limited to gaseous or molecular states, and include those in plasma states, radical states, and ionic states. When film formation is performed using an oxidizing agent in a plasma state, radical state, or ionic state, it is preferable to use a radical ALD device or plasma ALD device described below.

In order to remove impurities such as carbon or hydrogen contained in the precursor, it is preferable to sufficiently react the precursor with an oxidizing agent. For example, it is preferable to lengthen the pulse time for introducing the oxidizing agent. Or, it is preferable to introduce the oxidizing agent multiple times. When introducing the oxidizing agent multiple times, the same type of oxidizing agent may be introduced, or different types of oxidizing agents may be introduced. For example, after introducing water as the first oxidizing agent into the chamber, vacuum exhaust may be performed, and after introducing ozone or oxygen that does not contain hydrogen as the second oxidizing agent into the chamber, vacuum exhaust may be performed.

In this way, by repeating the introduction of an oxidizing agent and the introduction (or vacuum exhaust) of an inert gas several times in a short period of time within the chamber, unnecessary hydrogen atoms, carbon atoms, chlorine atoms, etc., can be more reliably removed from the precursor adsorbed on the substrate surface and excluded outside the chamber. In addition, by increasing the types of oxidizing agents to two, more unnecessary hydrogen atoms, etc., can be removed from the precursor adsorbed on the substrate surface. In this way, by preventing hydrogen atoms from entering the film during film formation, it is possible to reduce water, hydrogen, etc., contained in the formed film.

ALD is a film forming method that uses thermal energy to react a precursor and a reactant. The temperature required for the reaction of the precursor and the reactant is determined by their temperature characteristics, vapor pressure, decomposition temperature, etc., but is 100°C or more and 600°C or less, preferably 200°C or more and 600°C or less, and more preferably 300°C or more and 600°C or less.

In addition to the above-mentioned precursor and reactant reactions, there are cases where an ALD method that performs processing by introducing a plasma-excited reactant as a third raw material gas into the chamber is called a plasma ALD method. In this case, a plasma generation device is provided at the introduction section of the third raw material gas. Inductively coupled plasma can be used to generate plasma. In addition, on the other hand, there are cases where an ALD method that performs the precursor and reactant reactions with thermal energy is called a thermal ALD method.

In the plasma ALD method, film formation is performed by introducing a plasma excited reactant in the third stage. Or, film formation is performed by repeatedly performing the first to fourth stages and simultaneously introducing a plasma excited reactant (second reactant). In this case, the reactant introduced in the third stage is called the first reactant. The second reactant used as the third raw material gas in the plasma ALD method can use the same material as the oxidizing agent. That is, plasma excited ozone, oxygen, and water can be used as the second reactant. In addition to the oxidizing agent, a nitriding agent may be used as the second reactant. Nitrogen (N ₂ ) or ammonia (NH ₃ ) can be used as the nitriding agent. In addition, a mixed gas of nitrogen (N ₂ ) and hydrogen (H ₂ ) can be used as the nitriding agent. For example, a mixed gas of 5% nitrogen (N ₂ ) and 95% hydrogen (H ₂ ) can be used as a nitriding agent. By performing film formation while introducing plasma-excited nitrogen or ammonia, a nitride film such as a metal nitride film can be formed.

Also, as a carrier gas of the second reactant, argon (Ar), helium (He), or nitrogen (N ₂ ) may be used. By using a carrier gas such as argon, helium, or nitrogen, plasma discharge becomes easy, and the plasma-excited second reactant is easily generated, which is preferable. Also, when forming an oxide film such as a metal oxide film using the plasma ALD method, if nitrogen is used as a carrier gas, nitrogen may be mixed into the film, and the desired film quality may not be obtained. In this case, it is preferable to use argon or helium as a carrier gas.

The ALD method can form very thin films with uniform film thickness. It also has a high surface coverage even on uneven surfaces.

Here, the arrangement of atoms in the crystal when the metal oxide having the layered crystal structure is In-M-Zn oxide is explained using Figs. 13(A) to (D). In addition, in Figs. 13(B) and (D), atoms are represented as spheres (circles), and bonds between metal atoms and oxygen atoms are represented as lines. In Figs. 13(B) and (D), the c-axis direction in the crystal structure of In-M-Zn oxide is indicated by an arrow in the drawing. In addition, the a-b plane direction in the crystal structure of In-M-Zn oxide is a direction perpendicular to the c-axis direction indicated by the arrow in Figs. 13(B) and (D).

Fig. 13(A) is a drawing showing an oxide (660) having an In-M-Zn oxide formed in a structure (650). Here, the structure refers to an element constituting a semiconductor device such as a transistor. The structure (650) includes conductors such as a substrate, a gate electrode, a source electrode, and a drain electrode, insulators such as a gate insulating film, an interlayer insulating film, and a base insulating film, and semiconductors such as a metal oxide or silicon. Fig. 13(A) shows a case where the film-forming surface of the structure (650) is arranged parallel to the substrate (or substrate, not shown).

Fig. 13(B) is an enlarged view showing the atomic arrangement within the crystal in a region (653) which is a part of the oxide (660) in Fig. 13(A). Here, the composition of the oxide (660) shown in Figs. 13(A) and (B) is In:M:Zn=1:1:1 [atomic ratio], and the crystal structure is a YbFe ₂ O ₄ type structure. In addition, the element M is a +3 valent metal element.

As shown in (B) of FIG. 13, the crystal of the oxide (660) is formed by sequentially and repeatedly stacking a layer (621) having indium (In) and oxygen, a layer (631) having element M and oxygen, and a layer (641) having zinc (Zn) and oxygen. The layers (621), (631), and (641) are arranged substantially parallel to the film-forming surface of the structure (650). That is, the a-b plane of the oxide (660) is substantially parallel to the film-forming surface of the structure (650), and the c-axis of the oxide (660) is substantially parallel to the normal direction of the film-forming surface of the structure (650).

As shown in (B) of Fig. 13, each of the layers (621), (631), and (641) of the crystal is composed of one metal element and oxygen, thereby arranging them with good crystallinity and increasing the mobility of the metal oxide.

In addition, the In-M-Zn oxide of In:M:Zn=1:1:1 [atomic ratio] is not limited to the structure shown in (B) of Fig. 13. The stacking order of the layer (621), the layer (631), and the layer (641) may be changed. For example, the layers may be repeatedly stacked in the order of the layer (621), the layer (641), and the layer (631). Or, the layers may be repeatedly stacked in the order of the layer (621), the layer (631), the layer (641), the layer (621), the layer (641), and the layer (631). In addition, a part of the element M of the layer (631) may be replaced with zinc, and a part of the zinc of the layer (641) may be replaced with the element M.

The above shows an example of forming an In-M-Zn oxide having a composition of In:M:Zn=1:1:1 [atomic ratio], but a crystalline In-M-Zn oxide having a composition formula of In _(1+α) M _(1-α) O ₃ (ZnO) _m (α is a real number greater than 0 and less than 1, and m is a positive number) can likewise have a layered crystal structure. As an example, In-M-Zn oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] will be described using (C) and (D) of FIG. 13.

Fig. 13(C) is a drawing showing an oxide (662) having an In-M-Zn oxide formed in a structure (650). Fig. 13(D) is an enlarged view showing the atomic arrangement within a crystal in a region (654) that is part of the oxide (662) in Fig. 13(C).

As shown in (D) of FIG. 13, the crystal of the oxide (662) has a layer (622) having indium (In) and element M and oxygen, a layer (641) having zinc (Zn) and oxygen, and a layer (631) having element M and oxygen. In the oxide (662), a plurality of layers are repeatedly laminated in the order of layer (622), layer (641), layer (631), and layer (641). The layers (622), layer (631), and layer (641) are arranged substantially parallel to the film-forming surface of the structure (650). That is, the a-b plane of the oxide (662) is substantially parallel to the film-forming surface of the structure (650), and the c-axis of the oxide (662) is substantially parallel to the normal direction of the film-forming surface of the structure (650).

In addition, the In-M-Zn oxide of In:M:Zn=1:3:4 [atomic ratio] is not limited to the structure shown in (D) of Fig. 13, and the structure may be changed within the range of In:M:Zn=1:3:4 [atomic ratio]. For example, the stacking order of the layer (622), the layer (631), and the layer (641) may be changed. In addition, a part of the element M of the layer (631) may be replaced with zinc, and a part of the zinc of the layer (641) may be replaced with the element M. In addition, the layer (621) or the layer (631) may be formed instead of the layer (622).

Next, a detailed formation method of the oxide (660) having the In-M-Zn oxide shown in (A) and (B) of Fig. 13 is explained using (A) of Fig. 14 to (C) of Fig. 15.

First, a raw material gas containing a precursor including indium is introduced into the chamber to adsorb the precursor on the surface of the structure (650) (see (A) of FIG. 14). Here, in addition to the precursor, the raw material gas includes a carrier gas such as argon, helium, or nitrogen. As a precursor having indium, trimethylindium, triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedioic acid)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, etc. can be used.

In addition, an inorganic precursor that does not have a hydrocarbon may be used as a precursor having indium. Halogen-based indium compounds such as indium trichloride, indium tribromide, and indium triiodide may be used as an inorganic precursor having indium. Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

Next, the introduction of the raw material gas is stopped and the inside of the chamber is purged to discharge excess precursor and reaction products, etc., from the chamber.

Then, an oxidizing agent as a reactant is introduced into the chamber, reacted with the adsorbed precursor, and a layer (621) in which indium and oxygen are combined is formed by removing components other than indium while leaving indium adsorbed on the substrate (see (B) of Fig. 14). Ozone, oxygen, water, etc. can be used as the oxidizing agent. Next, the introduction of the oxidizing agent is stopped, the inside of the chamber is purged, and excess reactant and reaction products, etc. are discharged from the chamber.

Next, a raw material gas containing a precursor having element M is introduced into the chamber to adsorb the precursor on the layer (621) (see (C) of FIG. 14). In addition to the precursor, the raw material gas contains a carrier gas such as argon, helium, or nitrogen. When gallium is used as the element M, trimethylgallium, triethylgallium, tris(dimethylamide)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedioic acid)gallium, dimethylchlorogallium, diethylchlorogallium, dimethylgallium isopropoxide, or the like can be used as a precursor having gallium.

In addition, an inorganic precursor that does not have a hydrocarbon may be used as a precursor having gallium. Halogen-based gallium compounds such as gallium trichloride, gallium tribromide, and gallium triiodide can be used as inorganic precursors having gallium. Gallium trichloride has a decomposition temperature of approximately 550°C to 700°C. Therefore, by using gallium trichloride, a film can be formed by the ALD method while heating the substrate at approximately 450°C to 650°C, for example, at 550°C.

Next, the introduction of the raw material gas is stopped and the inside of the chamber is purged to discharge excess precursor and reaction products, etc., from the chamber.

Next, an oxidizing agent as a reactant is introduced into the chamber and reacted with the adsorbed precursor to form a layer (631) in which element M and oxygen are combined by adsorbing element M onto the substrate and removing components other than element M (see (D) of FIG. 14). At this time, some of the oxygen constituting the layer (641) may be adsorbed onto the layer (631). Next, the introduction of the oxidizing agent is stopped, the inside of the chamber is purged, and excess reactant and reaction products, etc. are discharged from the chamber.

Next, a raw material gas containing a precursor having zinc is introduced into the chamber, and the precursor is adsorbed on the layer (631) (see (A) of FIG. 15). At this time, there are cases where a part of a layer (641) in which zinc and oxygen are combined is formed. In addition to the precursor, the raw material gas contains a carrier gas such as argon, helium, or nitrogen. As a precursor containing zinc, dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptanedioic acid)zinc, zinc acetate, etc. can be used.

In addition, an inorganic precursor that does not have a hydrocarbon may be used as a precursor having zinc. As an inorganic precursor having zinc, a halogen-based zinc compound such as zinc dichloride, zinc dibromide, or zinc diiodide may be used. Zinc dichloride has a decomposition temperature of approximately 450°C to 700°C. Therefore, by using zinc dichloride, a film can be formed by the ALD method while heating the substrate at approximately 350°C to 550°C, for example, at 450°C.

Next, the introduction of the raw material gas is stopped and the inside of the chamber is purged to discharge excess precursor and reaction products, etc., from the chamber.

Next, an oxidizing agent as a reactant is introduced into the chamber and reacted with the adsorbed precursor to form a layer (641) in which zinc and oxygen are combined by removing components other than zinc while adsorbing zinc to the substrate (see (B) of FIG. 15). Next, the introduction of the oxidizing agent is stopped, the inside of the chamber is purged, and excess reactant and reaction products, etc. are discharged from the chamber.

Next, a layer (621) is formed again on the layer (641) using the method described above (see (C) of FIG. 15). By repeating the above method, an oxide (660) can be formed on the substrate or structure.

In addition, among the above precursors, there are some that contain, in addition to metal elements, one or both of carbon and chlorine. In some cases, a film formed using a precursor containing carbon contains carbon. In some cases, a film formed using a precursor containing a halogen such as chlorine contains a halogen such as chlorine.

As described above, by forming the oxide (660) using the ALD method, it is possible to form a metal oxide whose c-axis is oriented substantially parallel to the normal direction of the film-forming surface. For example, in the oxide semiconductor (230) shown in FIG. 1 (B) and (C) according to the above embodiment, it is possible to form a layered crystal substantially parallel to the sidewall of the opening (290), particularly, the side surface of the insulator (280). By forming it in this configuration, since the layered crystal of the oxide semiconductor (230) is formed substantially parallel to the channel length direction of the transistor (200), the on-state current of the transistor can be increased.

It is preferable to perform the processes shown in Fig. 14(A) to Fig. 15(C) while heating the substrate. For example, it is preferable to set the substrate temperature to 200°C or higher and 600°C or lower, preferably 300°C or higher and lower than the decomposition temperature of the precursor.

In order to perform film formation while heating the substrate in the above temperature range, it is preferable that the precursor used for the film formation has a high decomposition temperature. For example, it is preferable that the decomposition temperature of the precursor is 200°C or higher and 700°C or lower, and more preferably 300°C or higher and 600°C or lower. As the precursor having such a high decomposition temperature, it is preferable to use an inorganic precursor. Since inorganic precursors generally tend to have a higher decomposition temperature than organic precursors, even if film formation is performed while heating the substrate as described above, it is difficult for the precursor to decompose.

As the inorganic precursor, for example, indium trichloride, gallium trichloride, and zinc dichloride can be used. As described above, these precursors have a decomposition temperature of about 350°C or more and 700°C or less, which is considerably higher than the decomposition temperatures of general organic precursors. However, as described above, the decomposition temperatures of indium trichloride, gallium trichloride, and zinc dichloride are different from each other. In this way, when performing film formation by the ALD method using a plurality of different precursors, it is preferable to set the substrate temperature to a temperature lower than the lowest among the decomposition temperatures of the plurality of precursors. In the above example, it is preferable to set the substrate temperature in a range where zinc dichloride, which has the lowest decomposition temperature of the precursor, is not decomposed. Thereby, other indium trichlorides and gallium trichlorides can be adsorbed onto a target object (e.g., a substrate, etc.) without being decomposed.

In addition, in Fig. 14(A) to Fig. 15(C), an example is shown in which a layer (621) is formed as a layer including indium, a layer (631) is formed as a layer including element M thereon, and a layer (641) is formed as a layer including zinc thereon, but the present embodiment is not limited thereto. One of the layer (631) and the layer (641) may be formed, the layer (621) may be formed thereon, and the other of the layer (631) and the layer (641) may be further formed thereon. Alternatively, one of the layer (631) and the layer (641) may be formed, the other of the layer (631) and the layer (641) may be formed thereon, and the layer (621) may be further formed thereon.

Also, in the case of forming a metal oxide having an atomic ratio different from In:M:Zn=1:1:1 [atomic ratio], it is good to appropriately form the layer (621), layer (631), and layer (641) according to the atomic ratio. For example, by repeating the formation of layer (641) several times before and after the formation of layer (631) as shown in (A) of Fig. 15, it is good to form a stack of layers (631) and (641) having a desired atomic number, layer number, and thickness between the two layers (621).

(Embodiment 3)

In this embodiment, an example of a configuration of a memory device using the memory cells described in the preceding embodiments is described. In this embodiment, an example of a configuration of a memory device is described in which a layer having a functional circuit having a function of amplifying and outputting a data potential maintained in a memory cell is provided between layers having stacked memory cells.

[Example of memory device configuration]

Fig. 16 is a block diagram showing an example of a configuration of a memory device (300) according to one embodiment of the present invention. The memory device (300) shown in Fig. 16 has a driving circuit (21) and a memory array (20). The memory array (20) has a functional layer (50) having a plurality of memory cells (10) and a plurality of functional circuits (51).

Fig. 16 shows an example in which a memory array (20) has a plurality of memory cells (10) arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 2). In addition, a functional circuit (51) is provided for each wire (BL) that functions as a bit line, as an example. Fig. 16 shows an example in which a plurality of functional circuits (51) are provided corresponding to n wires (BL).

In Fig. 16, the memory cell (10) of the first row, first column is represented as memory cell (10[1,1]), and the memory cell (10) of the m-th row, n-th column is represented as memory cell (10[m,n]). In addition, in the present embodiment, etc., when indicating an arbitrary row, there are cases where it is described as row i. In addition, when indicating an arbitrary column, there are cases where it is described as column j. Accordingly, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n. In addition, in the present embodiment, etc., the memory cell (10) of the i-th row, j-th column is represented as memory cell (10[i,j]). In addition, in the present embodiment, etc., when indicating as "i+α" (α is a positive or negative integer), "i+α" does not fall below 1 and does not exceed m. Similarly, when indicating as "j+α", "j+α" does not fall below 1 and does not exceed n.

In addition, the memory array (20) has m wirings (WL) extending in the row direction, m wirings (PL) extending in the row direction, and n wirings (BL) extending in the column direction. In the present embodiment, the wiring (WL) provided in the first (first row) is represented as wiring (WL[1]), and the wiring (WL) provided in the mth (mth row) is represented as wiring (WL[m]). Similarly, the wiring (PL) provided in the first (first row) is represented as wiring (PL[1]), and the wiring (PL) provided in the mth (mth row) is represented as wiring (PL[m]). Similarly, the wiring (BL) provided in the first (first column) is represented as wiring (BL[1]), and the wiring (BL) provided in the nth (nth column) is represented as wiring (BL[n]).

A plurality of memory cells (10) provided in the ith row are electrically connected to the wiring (WL) of the ith row (wiring (WL[i])) and the wiring (PL) of the ith row (wiring (PL[i])). A plurality of memory cells (10) provided in the jth column are electrically connected to the wiring (BL) of the jth column (wiring (BL[j])).

The memory array (20) can be applied with DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM having a 1T (transistor) 1C (capacitor) type memory cell, and refers to a memory in which the access transistor is an OS transistor. The OS transistor has a very small leakage current, that is, a current that flows between the source and the drain in the off state. DOSRAM can maintain a charge according to data maintained in the capacitance element (capacitor) for a long time by turning the access transistor off (non-conductive state). Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAM composed of a transistor having silicon in a channel formation region (hereinafter, also called "Si transistor"). As a result, low power consumption can be achieved.

In addition, as described in Embodiment 1, etc., by stacking and arranging OS transistors, the memory cells (10) can be stacked and provided. For example, in the memory array (20) shown in Fig. 16, a plurality of memory arrays (20 [1] to 20 [m]) can be stacked and provided. By arranging the memory arrays (20 [1] to 20 [m]) of the memory array (20) in the vertical direction of the substrate surface on which the driving circuit (21) is provided, the memory density of the memory cell (10) can be improved. In addition, the memory array (20) can be manufactured in the vertical direction by repeatedly using the same manufacturing process. In the memory device (300), the manufacturing cost of the memory array (20) can be reduced.

The wiring (BL) functions as a bit line for writing and reading data. The wiring (WL) functions as a word line for controlling the on or off (conductive or non-conductive state) of the access transistor that functions as a switch. The wiring (PL) functions as a positive potential line connected to the capacitive element.

The memory cells (10) of each of the memory arrays (20[1] to 20[m]) are connected to the functional circuit (51) via the wiring (BL). The wiring (BL) can be arranged in the vertical direction of the substrate surface on which the driving circuit (21) is provided. By providing the wiring (BL) that is extended from the memory cells (10) of the memory arrays (20[1] to 20[m]) in the vertical direction of the substrate surface, the length of the wiring between the memory array (20) and the functional circuit (51) can be shortened. Therefore, the signal transmission distance between two circuits connected to the bit line can be shortened, and since the resistance and parasitic capacitance of the bit line are greatly reduced, power consumption and signal delay can be reduced. In addition, operation is possible even if the capacity of the capacitance element of the memory cell (10) is reduced.

The function circuit (51) has a function of amplifying the data potential maintained in the memory cell (10) and outputting it to the sense amplifier (46) of the driving circuit (21) through the wiring (GBL) (not shown) described later. By having the above configuration, the minute potential difference of the wiring (BL) can be amplified when reading data. The wiring (GBL), like the wiring (BL), can be arranged in the vertical direction of the substrate surface on which the driving circuit (21) is provided. By providing the wiring (BL) and the wiring (GBL) that are extended from the memory cell (10) of the memory array (20 [1] to 20 [m]) in the vertical direction of the substrate surface, the length of the wiring between the function circuit (51) and the sense amplifier (46) can be shortened. Therefore, the signal transmission distance between the two circuits connected to the wiring (GBL) can be shortened, and since the resistance and parasitic capacitance of the wiring (GBL) are greatly reduced, power consumption and signal delay can be reduced.

In addition, the wiring (BL) is provided in contact with the semiconductor layer of the transistor of the memory cell (10). Or, the wiring (BL) is provided in contact with an area functioning as a source or drain of the semiconductor layer of the transistor of the memory cell (10). Or, the wiring (BL) is provided in contact with a conductor provided in contact with an area functioning as a source or drain of the semiconductor layer of the transistor of the memory cell (10). In other words, the wiring (BL) can be said to be a wiring for electrically connecting, in a vertical direction, one of the source and drain of the transistor of the memory cell (10) in each layer of the memory array (20) and the functional circuit (51).

The memory array (20) can be provided by overlapping the driving circuit (21). By overlapping the driving circuit (21) and the memory array (20), the signal transmission distance between the driving circuit (21) and the memory array (20) can be shortened. Accordingly, the resistance and parasitic capacitance between the driving circuit (21) and the memory array (20) can be reduced, thereby reducing power consumption and signal delay. In addition, miniaturization of the memory device (300) can be realized.

By configuring the functional circuit (51) with OS transistors, similar to the transistors of the memory cell (10) of DOSRAM, it can be freely arranged on a circuit using Si transistors, such as a memory array (20 [1] to 20 [m]), thereby facilitating integration. By configuring the functional circuit (51) to amplify a signal, the circuits of the subsequent circuits, such as the sense amplifier (46), can be miniaturized, thereby facilitating miniaturization of the memory device (300).

The driving circuit (21) has a PSW (22) (power switch), a PSW (23), and a peripheral circuit (31). The peripheral circuit (31) has a peripheral circuit (41), a control circuit (32), and a voltage generation circuit (33).

In the memory device (300), each circuit, each signal, and each voltage can be appropriately selected as needed. Or, other circuits or other signals may be added. Signal (BW), signal (CE), signal (GW), signal (CLK), signal (WAKE), signal (ADDR), signal (WDA), signal (PON1), and signal (PON2) are input signals from the outside, and signal (RDA) is an output signal to the outside. Signal (CLK) is a clock signal.

In addition, signals (BW), (CE), and (GW) are control signals. Signal (CE) is a chip enable signal, signal (GW) is a global write enable signal, and signal (BW) is a byte write enable signal. Signal (ADDR) is an address signal. Signal (WDA) is write data, and signal (RDA) is read data. Signal (PON1) and signal (PON2) are signals for power gating control. In addition, signal (PON1) and signal (PON2) may be generated in the control circuit (32).

The control circuit (32) is a logic circuit that has a function of controlling the overall operation of the memory device (300). For example, the control circuit performs a logic operation on the signal (CE), the signal (GW), and the signal (BW) and determines the operation mode (e.g., write operation, read operation) of the memory device (300). Or, the control circuit (32) generates a control signal of the peripheral circuit (41) so that this operation mode is executed.

The voltage generation circuit (33) has a function of generating a negative voltage. The signal (WAKE) has a function of controlling the input of the signal (CLK) to the voltage generation circuit (33). For example, when a signal of H level is supplied as the signal (WAKE), the signal (CLK) is input to the voltage generation circuit (33), and the voltage generation circuit (33) generates a negative voltage.

The peripheral circuit (41) is a circuit for performing recording and reading of data for the memory cell (10). In addition, the peripheral circuit (41) is a circuit for outputting various signals for controlling the functional circuit (51). The peripheral circuit (41) has a row decoder (42), a column decoder (44), a row driver (43), a column driver (45), an input circuit (47), an output circuit (48), and a sense amplifier (46).

The row decoder (42) and the column decoder (44) have a function of decoding a signal (ADDR). The row decoder (42) is a circuit for specifying a row to be accessed, and the column decoder (44) is a circuit for specifying a column to be accessed. The row driver (43) has a function of selecting a wiring (WL) specified by the row decoder (42). The column driver (45) has a function of writing data to a memory cell (10), a function of reading data from a memory cell (10), a function of maintaining the read data, etc.

The input circuit (47) has a function of maintaining a signal (WDA). The data maintained by the input circuit (47) is output to the column driver (45). The output data of the input circuit (47) is data (Din) written to the memory cell (10). The data (Dout) read by the column driver (45) from the memory cell (10) is output to the output circuit (48). The output circuit (48) has a function of maintaining Dout. In addition, the output circuit (48) has a function of outputting Dout to the outside of the memory device (300). The data output from the output circuit (48) is a signal (RDA).

PSW (22) has a function of controlling the supply of VDD to the peripheral circuit (31). PSW (23) has a function of controlling the supply of VHM to the row driver (43). Here, the high power voltage of the memory device (300) is VDD, and the low power voltage is GND (ground potential). Also, VHM is a high power voltage used to make the word line high level, and is higher than VDD. The on/off of PSW (22) is controlled by signal (PON1), and the on/off of PSW (23) is controlled by signal (PON2). In Fig. 16, the number of power domains to which VDD is supplied from the peripheral circuit (31) is set to one, but may be set to multiple. In this case, it is good to provide a power switch for each power domain.

In a memory array (20) having a memory array (20[1] to 20[m]) (m is an integer of 2 or greater) and a functional layer (50), a plurality of layers of memory arrays (20) can be provided by overlapping them on a driving circuit (21). By overlapping and providing a plurality of layers of memory arrays (20), the memory density of the memory cell (10) can be increased. Fig. 17 (A) is a perspective view of a memory device (300) provided by overlapping a functional layer (50) and a five-layer (m=5) memory array (20[1] to 20[5]) on a driving circuit (21).

In (A) of Fig. 17, the memory array (20) provided in the first layer is represented as a memory array (20[1]), the memory array (20) provided in the second layer is represented as a memory array (20[2]), and the memory array (20) provided in the fifth layer is represented as a memory array (20[5]). In addition, in (A) of Fig. 17, the wiring (WL) and the wiring (PL) provided to extend in the X direction and the wiring (BL) provided to extend in the Z direction (the direction perpendicular to the substrate surface on which the driving circuit is provided) are illustrated. In addition, in order to make the drawing easier to read, some of the descriptions of the wiring (WL) and the wiring (PL) of each memory array (20) are omitted. In addition, although (A) of Fig. 17 illustrates a configuration in which the wiring (PL) is provided to extend in the X direction, the present invention is not limited thereto. For example, it may be configured to provide wiring (PL) extended in the Y direction, or it may be configured to provide wiring (PL) extended in the X and Y directions, for example, it may be configured to provide wiring (PL) in a plane.

Fig. 17(B) is a schematic diagram explaining an example of a configuration of a memory cell (10) having a functional circuit (51) connected to a wiring (BL) shown in Fig. 17(A) and a memory array (20[1] to 20[5]) connected to the wiring (BL). In addition, Fig. 17(B) shows a wiring (GBL) provided between a functional circuit (51) and a driving circuit (21). In addition, a configuration in which a plurality of memory cells (memory cells (10)) are electrically connected to a single wiring (BL) is also called a "memory string." In addition, in the drawing, the wiring (GBL) is sometimes shown as a thick line to improve visibility.

Fig. 17 (B) shows an example of a circuit configuration of a memory cell (10) connected to a wiring (BL). The memory cell (10) has a transistor (11) and a capacitor (12). For the transistor (11), the capacitor (12), and each wiring (BL and WL, etc.), for example, the wiring (BL[1]) and the wiring (WL[1]) are sometimes referred to as the wiring (BL) and the wiring (WL, etc.).

In the memory cell (10), one of the source and drain of the transistor (11) is connected to the wiring (BL). The other of the source and drain of the transistor (11) is connected to one electrode of the capacitor element (12). The other electrode of the capacitor element (12) is connected to the wiring (PL). The gate of the transistor (11) is connected to the wiring (WL).

For example, two memory cells (10) connected to a common wiring (BL) on the same layer can have a structure as shown in Fig. 10 according to embodiment 1.

In addition, although Fig. 17 (B) shows a configuration in which two memory cells (10) are connected to a common wiring (BL) in the same layer, the present invention is not limited thereto. For example, a configuration in which four memory cells (10) are connected to a common wiring (BL) in the same layer may be used, or a configuration in which eight memory cells (10) are connected to a common wiring (BL) in the same layer may be used. For example, in the case of providing four memory cells (10) connected to a common wiring (BL) in the same layer, the structure shown in Fig. 11 according to Embodiment 1 may be used.

The wiring (PL) is a wiring that supplies a constant potential to maintain the potential of the capacitive element (12).

The wiring (GBL) shown in (B) of Fig. 17 is provided to electrically connect the driving circuit (21) and the functional layer (50). Fig. 18 (A) shows a schematic diagram of a memory device (300) having a functional circuit (51) and a memory array (20 [1] to 20 [m]) as repeating units (70). In addition, although Fig. 18 (A) shows one wiring (GBL), the wiring (GBL) may be provided appropriately according to the number of functional circuits (51) provided to the functional layer (50).

In addition, the wiring (GBL) is provided in contact with the semiconductor layer of the transistor of the functional circuit (51). Or, the wiring (GBL) is provided in contact with an area functioning as a source or drain of the semiconductor layer of the transistor of the functional circuit (51). Or, the wiring (GBL) is provided in contact with a conductor provided in contact with an area functioning as a source or drain of the semiconductor layer of the transistor of the functional circuit (51). In other words, the wiring (GBL) can be said to be a wiring for electrically connecting one of the source and drain of the transistor of the functional circuit (51) in the functional layer (50) and the driving circuit (21) in the vertical direction.

In addition, a configuration may be adopted in which repeating units (70) having functional circuits (51) and memory arrays (20[1] to 20[m]) are further stacked. One form of a memory device (300A) of the present invention may have repeating units (70[1] to 70[p]) (p is an integer of 2 or more) as shown in (B) of Fig. 18. The wiring (GBL) is connected to the functional layer (50) of the repeating unit (70). The wiring (GBL) may be provided appropriately according to the number of functional circuits (51).

In one embodiment of the present invention, while providing OS transistors by stacking them, wirings functioning as bit lines are arranged in a vertical direction of a substrate surface on which a driving circuit (21) is provided. By providing wirings functioning as bit lines that are extended from a memory array (20) in a vertical direction of the substrate surface, the length of the wiring between the memory array (20) and the driving circuit (21) can be shortened. Therefore, the parasitic capacitance of the bit lines can be greatly reduced.

In addition, in one embodiment of the present invention, a functional layer (50) having a functional circuit (51) having a function of amplifying and outputting a data potential maintained in a memory cell (10) is included in a layer in which a memory array (20) is provided. By forming the above configuration, a minute potential difference of a wiring (BL) functioning as a bit line can be amplified when data is read, thereby driving a sense amplifier (46) of a driving circuit (21). Since circuits such as a sense amplifier can be miniaturized, the memory device (300) can be miniaturized. In addition, operation is possible even when the capacity of a capacitance element (12) of a memory cell (10) is reduced.

[Configuration example of memory array (20) and functional circuit (51)]

A configuration example of the functional circuit (51) described in FIGS. 16 to 18 and a configuration example of the sense amplifier (46) of the memory array (20) and the driver circuit (21) will be described using FIG. 19. FIG. 19 shows a driver circuit (21) connected to a wiring (GBL) (GBL_A, GBL_B) connected to a functional circuit (51) (51_A, 51_B) connected to a memory cell (10) (memory cell (10_A), memory cell (10_B)) connected to different wirings (BL) (BL_A, BL_B). The driver circuit (21) shown in FIG. 19 includes, in addition to the sense amplifier (46), a precharge circuit (71_A), a precharge circuit (71_B), a switch circuit (72_A), a switch circuit (72_B), and a write/read circuit (73).

Transistors (52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, 55_b) are illustrated in the functional circuits (51_A, 51_B). The transistors (52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, 55_b) illustrated in Fig. 19 are OS transistors, similar to the transistor (11) of the memory cell (10). The functional layer (50) having the functional circuit (51) can be provided by stacking, similar to the memory array (20[1] to 20[m]).

The wirings (BL_A and BL_B) are connected to the gates of the transistors (52_a, 52_b). The wirings (GBL_A and GBL_B) are connected to one of the sources and drains of the transistors (53_a, 53_b, 54_a, 54_b). The wirings (GBL_A and GBL_B) are provided in the vertical direction like the wirings (BL_A and BL_B) and are connected to the transistors of the driving circuit (21). As shown in Fig. 19, the gates of the transistors (53_a, 53_b, 54_a, 54_b, 55_a, 55_b) are supplied with control signals (WE, RE, MUX).

The transistors (81_1 to 81_6) and the transistors (82_1 to 82_4) constituting the sense amplifier (46), the precharge circuit (71_A), and the precharge circuit (71_B) shown in Fig. 19 are composed of Si transistors. The switches (83_A to 83_D) constituting the switch circuit (72_A) and the switch circuit (72_B) may also be composed of Si transistors. One of the sources and drains of the transistors (53_a, 53_b, 54_a, 54_b) is connected to a transistor or switch constituting the precharge circuit (71_A), the precharge circuit (71_B), the sense amplifier (46), and the switch circuit (72_A).

The precharge circuit (71_A) has n-channel transistors (81_1 to 81_3). The precharge circuit (71_A) is a circuit for precharging the wiring (BL_A) and the wiring (BL_B) to an intermediate potential (VPC) corresponding to a potential (VDD/2) between VDD and VSS according to a precharge signal supplied to the precharge line (PCL1).

The precharge circuit (71_B) has n-channel transistors (81_4 to 81_6). The precharge circuit (71_B) is a circuit for precharging the wiring (GBL_A) and the wiring (GBL_B) to an intermediate potential (VPC) corresponding to a potential (VDD/2) between VDD and VSS according to a precharge signal supplied to the precharge line (PCL2).

The sense amplifier (46) has p-channel transistors (82_1, 82_2) and n-channel transistors (82_3, 82_4) connected to wiring (VHH) or wiring (VLL). The wiring (VHH) or wiring (VLL) is a wiring having a function of supplying VDD or VSS. The transistors (82_1 to 82_4) are transistors constituting an inverter loop. By selecting the memory cells (10_A, 10_B), the potentials of the precharged wiring (BL_A) and wiring (BL_B) are changed, and according to the change, the potentials of the wiring (GBL_A) and wiring (GBL_B) are set to the high power potential VDD or the low power potential VSS. The potentials of the wiring (GBL_A) and wiring (GBL_B) can be output to the outside through the switch (83_C), the switch (83_D), and the write/read circuit (73). Wiring (BL_A) and wiring (BL_B) and wiring (GBL_A) and wiring (GBL_B) correspond to bit line pairs. The write/read circuit (73) controls the writing of data signals according to the signal (EN_data).

The switch circuit (72_A) is a circuit for controlling the conduction state between the sense amplifier (46) and the wiring (GBL_A) and the wiring (GBL_B). The switch circuit (72_A) is switched on or off under the control of the switching signal (CSEL1). When the switches (83_A and 83_B) are n-channel transistors, they are turned on when the switching signal (CSEL1) is at a high level and are turned off when it is at a low level. The switch circuit (72_B) is a circuit for controlling the conduction state between the write/read circuit (73) and the bit line pair connected to the sense amplifier (46). The switch circuit (72_B) is switched on or off under the control of the switching signal (CSEL2). The switches (83_C and 83_D) may be configured in the same manner as the switches (83_A and 83_B).

As shown in Fig. 19, the memory device (300) can be configured such that the memory cell (10), the functional circuit (51), and the sense amplifier (46) are connected via the wiring (BL) and the wiring (GBL) provided in the vertical direction, which is the shortest distance. Although the functional layer (50) having the transistors constituting the functional circuit (51) increases, the load on the wiring (BL) is reduced, so the recording time is shortened and data reading becomes easier.

In addition, as shown in Fig. 19, each transistor of the functional circuit (51_A, 51_B) is controlled according to a control signal (WE, RE) and a selection signal (MUX). Each transistor can output the potential of the wiring (BL) to the driving circuit (21) through the wiring (GBL) according to the control signal and the selection signal. The functional circuit (51_A, 51_B) can function as a sense amplifier composed of an OS transistor. By using the above configuration, the minute potential difference of the wiring (BL) can be amplified at the time of reading, and the sense amplifier (46) using a Si transistor can be driven.

As described above, by stacking multiple memory cell arrays and driving circuits, high integration and large capacity of the memory device are possible.

This embodiment can be appropriately combined with other embodiments described in this specification.

(Embodiment 4)

In this embodiment, an example of a chip (1200) in which the memory device of the present invention is mounted is described using (A) and (B) of FIG. 20. A plurality of circuits (systems) are mounted on the chip (1200). In this way, a technology for integrating a plurality of circuits (systems) into a single chip is sometimes called a system on chip (SoC).

As shown in (A) of Fig. 20, the chip (1200) has a CPU (1211), a GPU (1212), one or more analog operation units (1213), one or more memory controllers (1214), one or more interfaces (1215), one or more network circuits (1216), etc.

The chip (1200) is provided with bumps (not shown) and is connected to a first surface of a package substrate (1201), as shown in (B) of Fig. 20. In addition, a plurality of bumps (1202) are provided on the back surface of the first surface of the package substrate (1201) and are connected to a motherboard (1203).

The motherboard (1203) may be provided with a memory device such as DRAM (1221) or flash memory (1222). For example, the DOSRAM described in the preceding embodiment may be used as the DRAM (1221). This makes it possible to reduce power consumption, increase speed, and increase capacity of the DRAM (1221).

It is preferable that the CPU (1211) has multiple CPU cores. In addition, the GPU (1212) preferably has multiple GPU cores. In addition, the CPU (1211) and the GPU (1212) may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU (1211) and the GPU (1212) may be provided in the chip (1200). The above-described DOSRAM can be used as the memory. In addition, the GPU (1212) is suitable for parallel calculation of a large number of data, and can be used for image processing or a product-sum operation. By providing the GPU (1212) with an image processing circuit or a product-sum operation circuit using the oxide semiconductor of the present invention, image processing and a product-sum operation can be executed with low power consumption.

In addition, if the CPU (1211) and the GPU (1212) are provided on the same chip, the wiring between the CPU (1211) and the GPU (1212) can be shortened, so that data transfer from the CPU (1211) to the GPU (1212), data transfer between the memories of the CPU (1211) and the GPU (1212), and transfer of the operation result from the GPU (1212) to the CPU (1211) after the operation in the GPU (1212) can be performed at high speed.

The analog operation unit (1213) has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. In addition, the analog operation unit (1213) may be provided with the above-described integration operation circuit.

The memory controller (1214) has a circuit that functions as a controller of DRAM (1221) and a circuit that functions as an interface of flash memory (1222).

The interface (1215) has an interface circuit with external connection devices such as a display device, speaker, microphone, camera, and controller. The controller includes a mouse, a keyboard, and a game controller. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

The network circuit (1216) has a network circuit such as a LAN (Local Area Network). It may also have a circuit for network security.

The chip (1200) can form the above circuit (system) using the same manufacturing process. Therefore, even if the number of circuits required for the chip (1200) increases, there is no need to increase the manufacturing process, so the chip (1200) can be manufactured at a low cost.

A package substrate (1201) provided with a chip (1200) having a GPU (1212), a motherboard (1203) provided with DRAM (1221), and flash memory (1222) may be referred to as a GPU module (1204).

Since the GPU module (1204) has a chip (1200) using SoC technology, its size can be reduced. In addition, since it has high image processing capability, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (carry-on) game consoles. In addition, since it is possible to execute methods such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), and a deep belief neural network (DBN) by means of an integrated circuit using the GPU (1212), the chip (1200) can be used as an AI chip, or the GPU module (1204) can be used as an AI system module.

The configurations, methods, etc. described in this embodiment can be implemented by appropriately combining at least some of them with other embodiments, etc. described in this specification.

(Embodiment 5)

In this embodiment, an example of an electronic component and an electronic device provided with a memory device, etc., described in the preceding embodiment is described. By using the memory device described in the preceding embodiment in the following electronic components and electronic devices, it is possible to reduce power consumption and increase speed of the electronic components and electronic devices.

<Electronic components>

First, an example of an electronic component provided with a memory device (720) is described using (A) and (B) of Fig. 21.

Fig. 21(A) shows a perspective view of an electronic component (700) and a substrate (mounting substrate (704)) on which the electronic component (700) is mounted. The electronic component (700) shown in Fig. 21(A) has a memory device (720) inside a mold (711). Part of Fig. 21(A) is omitted to show the inside of the electronic component (700). The electronic component (700) has a land (712) on the outside of the mold (711). The land (712) is electrically connected to an electrode pad (713), and the electrode pad (713) is electrically connected to the memory device (720) by a wire (714). The electronic component (700) is mounted on, for example, a printed circuit board (702). A plurality of such electronic components are combined and each is electrically connected on a printed circuit board (702) to complete a mounting circuit board (704).

The memory device (720) has a driving circuit layer (721) and a memory circuit layer (722).

A perspective view of an electronic component (730) is shown in (B) of Fig. 21. The electronic component (730) is an example of a SiP (System in package) or an MCM (Multi Chip Module). The electronic component (730) is provided with an interposer (731) on a package substrate (732) (printed substrate), and a semiconductor device (735) and a plurality of memory devices (720) are provided on the interposer (731). By using the memory device shown in the above embodiment for the memory device (720), low power consumption and high speed can be achieved.

As a semiconductor device (735), an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA can be used.

As the package substrate (732), a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. can be used. As the interposer (731), a silicon interposer, a resin interposer, etc. can be used.

The interposer (731) has a plurality of wires and has a function of electrically connecting a plurality of integrated circuits having different terminal pitches. The plurality of wires are provided in a single layer or multiple layers. In addition, the interposer (731) has a function of electrically connecting an integrated circuit provided on the interposer (731) with an electrode provided on a package substrate (732). Therefore, the interposer is sometimes called a “rewiring substrate” or an “intermediate substrate.” In addition, a through electrode is provided on the interposer (731), and the integrated circuit and the package substrate (732) are electrically connected using the through electrode. In addition, in a silicon interposer, a TSV (Through Silicon Via) may be used as the through electrode.

It is preferable to use a silicon interposer as the interposer (731). Since a silicon interposer does not need to provide active components, it can be manufactured at a lower cost than an integrated circuit. In addition, since the wiring of a silicon interposer can be formed through a semiconductor process, it is easy to form fine wiring that is difficult with a resin interposer.

In addition, in SiP, MCM, etc. using silicon interposers, it is difficult for reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer to occur. In addition, since the silicon interposer has a high surface flatness, it is difficult for a connection failure to occur between the integrated circuit provided on the silicon interposer and the silicon interposer. In particular, it is desirable to use a silicon interposer in a 2.5D package (2.5-dimensional mounting) in which multiple integrated circuits are placed side by side on an interposer.

It is also possible to provide a heat sink (heat dissipation plate) by overlapping the electronic component (730). When providing a heat sink, it is preferable to match the height of the integrated circuit provided on the interposer (731). For example, in the electronic component (730) described in this embodiment, it is preferable to match the height of the memory device (720) and the semiconductor device (735).

In order to mount the electronic component (730) on another substrate, an electrode (733) may be provided on the bottom of the package substrate (732). In Fig. 21 (B), an example in which the electrode (733) is formed as a solder ball is shown. By providing the solder balls as a matrix on the bottom of the package substrate (732), BGA (Ball Grid Array) mounting can be realized. In addition, the electrode (733) may be formed as a conductive pin. By providing the conductive pins as a matrix on the bottom of the package substrate (732), PGA (Pin Grid Array) mounting can be realized.

The electronic component (730) is not limited to BGA and PGA, and can be mounted on other substrates using various mounting methods. For example, a mounting method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with other configurations, methods, etc. shown in this embodiment, and configurations, methods, etc. shown in other embodiments.

(Embodiment 6)

In this embodiment, an application example of a memory device using the memory device described in the preceding embodiment is described. The memory device described in the preceding embodiment can be applied to, for example, a memory device of various electronic devices (for example, an information terminal, a computer, a smart phone, an e-book terminal, a digital camera (including a video camera), a recording and playback device, a navigation system, etc.). In addition, the computer herein includes not only a tablet computer, a notebook computer, a desktop computer, but also a large computer such as a server system. Alternatively, the memory device described in the preceding embodiment is applied to various removable memory devices such as a memory card (for example, an SD card), a USB memory, and an SSD (Solid State Drive). Several configuration examples of a removable memory device are schematically shown in Fig. 22 (A) to (E). For example, the memory device described in the preceding embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

Fig. 22 (A) is a schematic diagram of a USB memory. The USB memory (1100) has a housing (1101), a cap (1102), a USB connector (1103), and a substrate (1104). The substrate (1104) is housed in the housing (1101). For example, a memory chip (1105) and a controller chip (1106) are mounted on the substrate (1104). The memory device described in the preceding embodiment can be provided to the memory chip (1105), etc.

Fig. 22 (B) is a schematic diagram of the appearance of the SD card, and Fig. 22 (C) is a schematic diagram of the internal structure of the SD card. The SD card (1110) has a housing (1111), a connector (1112), and a substrate (1113). The substrate (1113) is housed in the housing (1111). For example, a memory chip (1114) and a controller chip (1115) are mounted on the substrate (1113). By providing a memory chip (1114) on the back side of the substrate (1113), the capacity of the SD card (1110) can be increased. In addition, a wireless chip having a wireless communication function may be provided on the substrate (1113). This enables reading and writing of data of the memory chip (1114) by wireless communication between the host device and the SD card (1110). The memory device described in the preceding embodiment can be provided on the memory chip (1114), etc.

Fig. 22 (D) is a schematic diagram of the appearance of the SSD, and Fig. 22 (E) is a schematic diagram of the internal structure of the SSD. The SSD (1150) has a housing (1151), a connector (1152), and a substrate (1153). The substrate (1153) is housed in the housing (1151). For example, a memory chip (1154), a memory chip (1155), and a controller chip (1156) are mounted on the substrate (1153). The memory chip (1155) is a working memory of the controller chip (1156), and, for example, a DOSRAM chip may be used. By also providing the memory chip (1154) on the back side of the substrate (1153), the capacity of the SSD (1150) can be increased. The memory device described in the preceding embodiment can be provided on the memory chip (1154), etc.

The configurations, methods, etc. described in this embodiment can be implemented by appropriately combining at least some of them with other embodiments, etc. described in this specification.

(Embodiment 7)

A memory device according to one embodiment of the present invention can be used in a processor or chip such as a CPU or GPU. By using such a processor or chip such as a CPU or GPU in an electronic device, power consumption and speed of the electronic device can be reduced. Specific examples of electronic devices having a processor or chip such as a CPU or GPU using the memory device are shown in (A) to (H) of Figs. 23.

<Electronic devices/systems>

A GPU or chip according to one embodiment of the present invention can be mounted on various electronic devices. Examples of the electronic devices include, in addition to electronic devices having relatively large screens, such as television devices, monitors for desktop or notebook-type information terminals, digital signage, and large game machines such as pachinko machines, digital cameras, digital video cameras, digital picture frames, e-book terminals, mobile phones, portable game machines, portable information terminals, and audio reproduction devices. In addition, by providing a GPU or chip according to one embodiment of the present invention to an electronic device, artificial intelligence can be mounted on the electronic device.

An electronic device of one embodiment of the present invention may have an antenna. By receiving a signal through the antenna, an image, information, etc. can be displayed on the display section. In addition, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

An electronic device of one embodiment of the present invention may have a sensor (having a function of detecting, sensing, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared ray).

An electronic device of one embodiment of the present invention may have various functions. For example, it may have a function for displaying various information (still images, moving images, text images, etc.) on a display unit, a touch panel function, a function for displaying a calendar, date, or time, a function for executing various software (programs), a wireless communication function, a function for reading a program or data recorded on a recording medium, etc. Examples of electronic devices are shown in (A) to (H) of FIG. 23.

[Information Terminal]

Fig. 23 (A) illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal (5100) has a housing (5101) and a display portion (5102), and a touch panel is provided on the display portion (5102) as an input interface, and a button is provided on the housing (5101).

By applying a type of chip of the present invention to an information terminal (5100), low power consumption and high speed are possible.

Fig. 23 (B) shows a notebook-type information terminal (5200). The notebook-type information terminal (5200) has a main body (5201), a display portion (5202), and a keyboard (5203).

As with the information terminal (5100) described above, by applying one type of chip of the present invention to a notebook-type information terminal (5200), low power consumption and high speed are possible.

In addition, although the above-described electronic devices, such as smartphones and laptop-type information terminals, were used as examples in Figures 23 (A) and (B), respectively, information terminals other than smartphones and laptop-type information terminals can be applied. Information terminals other than smartphones and laptop-type information terminals include, for example, PDAs (Personal Digital Assistants), desktop-type information terminals, and workstations.

[Game console]

Fig. 23 (C) illustrates a portable game machine (5300) which is an example of a game machine. The portable game machine (5300) has a housing (5301), a housing (5302), a housing (5303), a display portion (5304), a connection portion (5305), operation keys (5306), etc. The housing (5302) and the housing (5303) can be removed from the housing (5301). By attaching the connection portion (5305) provided on the housing (5301) to another housing (not shown), an image output to the display portion (5304) can be output to another image device (not shown). At this time, the housing (5302) and the housing (5303) can each function as an operation portion. Thereby, multiple players can play the game simultaneously. The chips described in the preceding embodiments can be provided on the substrates of the housing (5301), the housing (5302), and the housing (5303).

Also, Fig. 23 (D) shows a stationary game machine (5400), which is an example of a game machine. A controller (5402) is connected wirelessly or by wire to the stationary game machine (5400).

By applying a GPU or chip of one form of the present invention to a game machine such as a portable game machine (5300) or a home game machine (5400), a game machine with low power consumption can be realized. In addition, since low power consumption can reduce heat generation from a circuit, the impact of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

In addition, by applying a GPU or chip of one form of the present invention to a portable game device (5300), low power consumption and high speed are possible.

In Figs. 23(C) and (D), a portable game machine and a home game machine are shown as examples of game machines, but game machines applying a GPU or chip of one embodiment of the present invention are not limited to these. Examples of game machines applying a GPU or chip of one embodiment of the present invention include arcade game machines installed in entertainment facilities (game rooms, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[large computer]

A GPU or chip of one form of the present invention can be applied to large computers.

Fig. 23 (E) is a drawing showing a supercomputer (5500), which is an example of a large computer. Fig. 23 (F) is a drawing showing a rack-mounted calculator (5502) included in the supercomputer (5500).

A supercomputer (5500) has a rack (5501) and a plurality of rack-mounted calculators (5502). In addition, a plurality of calculators (5502) are stored in the rack (5501). In addition, a plurality of substrates (5504) are provided in the calculator (5502), and a GPU or chip described in the preceding embodiment can be mounted on the substrate.

The supercomputer (5500) is a large computer mainly used for scientific and technological calculations. Since scientific and technological calculations require high-speed processing of massive calculations, power consumption is high and chip heat generation is large. By applying a GPU or chip of one form of the present invention to the supercomputer (5500), a supercomputer with low power consumption can be realized. In addition, since low power consumption can reduce heat generation from a circuit, the impact on the circuit itself, peripheral circuits, and modules due to heat generation can be reduced.

In Figs. 23(E) and (F), a supercomputer is shown as an example of a large computer, but a large computer to which a GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of large computers to which a GPU or chip of one embodiment of the present invention is applied include a computer providing a service (server), a large general-purpose computer (mainframe), etc.

[Moving Object]

A GPU or chip of one form of the present invention can be applied to a mobile vehicle, and to the area around the driver's seat of the vehicle.

Fig. 23 (G) shows the area around the windshield in the interior of an automobile, which is an example of a mobile body. Fig. 23 (G) shows, in addition to the display panel (5701), display panel (5702), and display panel (5703) mounted on the dashboard, a display panel (5704) mounted on a pillar.

The display panel (5701) to the display panel (5703) can provide various information by displaying a speedometer, a tachometer, a driving distance, a fuel gauge, gear status, air conditioner settings, etc. In addition, since the display items, layout, etc. displayed on the display panel can be appropriately changed according to the user's preference, the design can be improved. The display panel (5701) to the display panel (5703) can also be used as a lighting device.

The display panel (5704) can compensate for blind spots (blind spots) covered by fillers by displaying images from an imaging device (not shown) provided in the car. That is, by displaying images from an imaging device provided on the outside of the car, blind spots can be compensated for and safety can be improved. In addition, by displaying images that compensate for invisible parts, safety can be confirmed more naturally and without discomfort. The display panel (5704) can also be used as a lighting device.

Since the GPU or chip of one form of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used in an autonomous driving system of an automobile. In addition, the chip can be used in a system for providing road guidance, risk prediction, etc. A configuration for displaying information such as road guidance, risk prediction, etc. may be applied to the display panel (5701) to the display panel (5704).

In addition, although an automobile was described above as an example of a mobile body, the mobile body is not limited to an automobile. For example, there are also trains, monorails, ships, and aircraft (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), etc. as mobile bodies, and by applying a type of chip of the present invention to these mobile bodies, a system utilizing artificial intelligence can be provided.

[Electronics]

Fig. 23 (H) illustrates an electric refrigerator-freezer (5800), which is an example of an electronic product. The electric refrigerator-freezer (5800) has a housing (5801), a refrigerator door (5802), a freezer door (5803), etc.

By applying one type of chip of the present invention to an electric refrigerator-freezer (5800), an electric refrigerator-freezer (5800) having artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer (5800) can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer (5800), the expiration date of the ingredients, etc., a function of automatically adjusting the temperature to an appropriate temperature for ingredients stored in the electric refrigerator-freezer (5800), etc.

As an example of an electronic product, an electric refrigerator was described, but other electronic products include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water purifiers, air conditioners, and other heating and cooling appliances, washing machines, dryers, and audio visual appliances.

The electronic device described in this embodiment, the functions of the electronic device, the application examples of artificial intelligence, the effects thereof, etc. can be appropriately combined with descriptions of other electronic devices.

The configurations, methods, etc. described in this embodiment can be implemented by appropriately combining at least some of them with other embodiments, etc. described in this specification.

(Embodiment 8)

One form of a memory device of the present invention includes an OS transistor. The OS transistor has a small fluctuation in electrical characteristics due to radiation exposure. That is, since it has high resistance to radiation, it can be suitably used in an environment where radiation may be incident. For example, the OS transistor is suitable for use in space. In this embodiment, a specific example of applying one form of a memory device of the present invention to a space device will be described using FIG. 24.

Fig. 24 shows an artificial satellite (6800) as an example of a space device. The artificial satellite (6800) has a body (6801), a solar panel (6802), an antenna (6803), a secondary battery (6805), and a control device (6807). Also, Fig. 24 shows a planet (6804) in space as an example. In addition, space refers to, for example, an altitude of 100 km or higher, but the space described in this specification may include the thermosphere, the mesosphere, and the stratosphere.

Also, space is an environment where radiation is 100 times higher than on the ground. In addition, as radiation, there are electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

The power required for the operation of the satellite (6800) is generated when sunlight is irradiated on the solar panel (6802). However, for example, in a situation where sunlight is not irradiated on the solar panel, or in a situation where the amount of sunlight irradiated on the solar panel is small, the generated power is low. Therefore, there is a possibility that the power required for the operation of the satellite (6800) is not generated. In order to operate the satellite (6800) even in a situation where the generated power is low, it is preferable to provide a secondary battery (6805) to the satellite (6800). In addition, the solar panel is sometimes called a solar cell module.

The satellite (6800) can generate a signal. The signal is transmitted through the antenna (6803), and, for example, a receiver provided on the ground or another satellite can receive the signal. By receiving the signal transmitted by the satellite (6800), the position of the receiver that received the signal can be measured. As a result, the satellite (6800) can constitute a satellite positioning system.

In addition, the control device (6807) has a function of controlling the artificial satellite (6800). The control device (6807) is configured by using, for example, one or more selected from a CPU, a GPU, and a memory device. In addition, it is suitable for the control device (6807) to use a memory device including an OS transistor, which is one embodiment of the present invention. The OS transistor has a smaller fluctuation in electrical characteristics due to radiation exposure than a Si transistor. In other words, it can be suitably used because it has high reliability even in an environment where radiation may be incident.

In addition, the satellite (6800) may be configured to have a sensor. For example, by having a visible light sensor, the satellite (6800) may have a function of detecting sunlight reflected by an object provided on the ground. Or, by having a thermal infrared sensor, the satellite (6800) may have a function of detecting thermal infrared emitted from the ground. As a result, the satellite (6800) may have a function as an earth observation satellite, for example.

In addition, although an artificial satellite is shown as an example of a space device in this embodiment, it is not limited thereto. For example, a memory device of one form of the present invention can be suitably used in space devices such as a spacecraft, a space capsule, or a space probe.

ADDR: signal, BL[1]: wiring, BL[j]: wiring, BL[n]: wiring, BL_A: wiring, BL_B: wiring, BL: wiring, BW: signal, CE: signal, CLK: signal, EN_data: signal, GBL_A: wiring, GBL_B: wiring, GBL: wiring, GW: signal, MUX: select signal, PL[1]: wiring, PL[i]: wiring, PL[m]: wiring, PL: wiring, RDA: signal, RE: control signal, Tr: transistor, VDD: high power potential, VHH: wiring, VLL: wiring, VPC: middle power potential, VSS: low power potential, WAKE: signal, WDA: signal, WE: control signal, WL[1]: wiring, WL[i]: wiring, WL[m]: wiring, WL: wiring, 10_A: memory cell, 10_B: memory cell, 10: memory cell, 11: transistor, 12: capacitive element, 20: memory array, 21: driver circuit, 22: PSW, 23: PSW, 31: peripheral circuit, 32: control circuit, 33: voltage generation circuit, 41: peripheral circuit, 42: row decoder, 43: row driver, 44: column decoder, 45: column driver, 46: sense amplifier, 47: input circuit, 48: output circuit, 50: functional layer, 51_A: functional circuit, 51_B: functional circuit, 51: functional circuit, 52_a: transistor, 52_b: transistor, 53_a: transistor, 53_b: transistor, 54_a: transistor, 54_b: transistor, 55_a: transistor, 55_b: transistor, 70: repeating unit, 71_A: precharge circuit, 71_B: precharge circuit, 72_A: switch circuit, 72_B: switch circuit, 73: read-write circuit, 81_1: transistor, 81_3: transistor, 81_4: transistor, 81_6: transistor, 82_1: transistor, 82_2: transistor, 82_3: transistor, 82_4: transistor, 83_A: switch, 83_B: switch, 83_C: switch, 83_D: switch, 100a: capacitive element, 100b: capacitive element, 100c: capacitive element, 100d: capacitive element, 100: capacitive element, 110: conductor, 120: conductor, 130: insulator, 140: insulator, 150a: memory cell, 150b: memory cell, 150c: memory cell, 150d: memory cell, 150: memory cell, 160a: memory unit, 160b: memory unit, 160c: memory unit, 160d: memory unit, 160: memory unit, 200a: transistor, 200b: transistor, 200c: transistor, 200d: transistor, 200: transistor, 230A: oxide semiconductor film, 230: oxide semiconductor, 240: conductor, 245: conductor, 246: conductor, 250A: insulating film, 250: insulator, 254: insulator, 260: conductor, 265: conductor, 280: insulator, 281: insulator, 285: insulator, 287: insulator, 289: insulator, 290: opening, 300A: memory device, 300: memory device, 610: substrate, 611a: precursor, 611b: precursor, 612a: reactant, 612b: reactant, 613a: oxide, 613b: oxide, 613c: oxide, 621: layer, 622: layer, 631: layer, 641: layer, 650: structure, 653: region, 654: region, 660: oxide, 662: oxide, 700: electronic component, 702: printed circuit board, 704: mounting board, 711: mold, 712: land, 713: electrode pad, 714: wire, 720: memory device, 721: drive circuit layer, 722: memory circuit layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 1100: USB memory, 1101: housing, 1102: cap, 1103: USB connector, 1104: board, 1105: memory chip, 1106: controller chip, 1110: SD card, 1111: housing, 1112: connector, 1113: board, 1114: memory chip, 1115: controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: board, 1154: memory chip, 1155: memory chip, 1156: controller chip, 1200: chip, 1201: package board, 1202: bump, 1203: motherboard, 1204: GPU module, 1211: CPU, 1212: GPU, 1213: analog operation unit, 1214: memory controller, 1215: interface, 1216: network circuit, 1221: DRAM, 1222: flash memory, 5100: information terminal, 5101: housing, 5102: display unit, 5200: notebook type information terminal, 5201: main body, 5202: display unit, 5203: keyboard, 5300: portable game machine, 5301: housing, 5302: housing, 5303: housing, 5304: display unit, 5305: connection unit, 5306: operation key, 5400: stationary game machine, 5402: controller, 5500: supercomputer, 5501: rack, 5502: calculator, 5504: substrate, 5701: display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5800: Electric refrigerator, 5801: Housing, 5802: Door for refrigerator, 5803: Door for freezer, 6800: Satellite, 6801: Airframe, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device

Claims (13)

As a memory device,
Having a capacitive element, a transistor on the capacitive element, a first insulator on the capacitive element, and a second insulator on the first insulator,
The above transistor
A first conductor under the first insulator, and
An oxide semiconductor arranged in contact with the upper surface of the first conductor,
A second conductor disposed between the first insulator and the second insulator and in contact with the oxide semiconductor,
A third insulator on the above oxide semiconductor, and
Having a third conductor on the third insulator,
The first insulator, the second conductor, and a first opening reaching the first conductor are formed in the second insulator,
At least a portion of the oxide semiconductor, at least a portion of the third insulator, and at least a portion of the third conductor are disposed within the first opening,
The above capacitive element
The 4th challenger,
A fourth insulator on the fourth conductor, and
A memory device having a first conductor on the fourth insulator. As a memory device,
Having a first layer and a second layer, each including a capacitor, a transistor over the capacitor, a first insulator over the capacitor, and a second insulator over the first insulator,
The second layer is laminated on the first layer,
The above transistor
A first conductor under the first insulator, and
An oxide semiconductor arranged in contact with the upper surface of the first conductor,
A second conductor disposed between the first insulator and the second insulator and in contact with the oxide semiconductor,
A third insulator on the above oxide semiconductor, and
Having a third conductor on the third insulator,
In the first insulator, the second conductor, and the second insulator, a first opening reaching the first conductor is formed,
At least a portion of the oxide semiconductor, at least a portion of the third insulator, and at least a portion of the third conductor are disposed within the first opening,
The above capacitive element
The 4th challenger,
A fourth insulator on the fourth conductor, and
Having the first conductor on the fourth insulator,
A second opening is formed in the second insulator of the first layer and in the first insulator of the second layer,
Having a fifth conductor within the second opening,
A memory device, wherein the fifth conductor is in contact with the upper surface of the second conductor of the first layer and also in contact with the lower surface of the second conductor of the second layer. In claim 1 or 2,
Having a sixth conductor in contact with the upper surface of the third conductor,
The second conductor is formed by extending in the first direction,
The above sixth conductor is formed by extending in the second direction,
A memory device wherein the first direction and the second direction intersect each other. In any one of claims 1 to 3,
The above first conductor functions as one of the source electrode and the drain electrode,
The second conductor functions as the other of the source electrode and the drain electrode,
A memory device, wherein the third conductor functions as a gate electrode. In any one of claims 1 to 4,
A memory device, wherein a portion of the oxide semiconductor, a portion of the third insulator, and a portion of the third conductor are positioned on the second insulator. In any one of claims 1 to 5,
A memory device, wherein when viewed from a plane, the side edge of the oxide semiconductor and the side edge of the third insulator substantially coincide. In any one of claims 1 to 6,
A memory device, wherein, when viewed from a plane, the side edge of the third conductor is positioned inside the side edge of the oxide semiconductor and the side edge of the third insulator. In any one of claims 1 to 7,
A memory device, wherein the first opening is circular or approximately circular when viewed from a plane. In any one of claims 1 to 8,
Having a fifth insulator between the third insulator and the third conductor,
A memory device, wherein the fifth insulator covers the side edge of the oxide semiconductor and the side edge of the third insulator. In Article 9,
A memory device, wherein the fifth insulator is silicon nitride. In any one of claims 1 to 10,
A memory device wherein the oxide semiconductor has one or more selected from In, Ga, and Zn. In any one of claims 1 to 11,
A memory device, wherein the oxide semiconductor has a layered crystal substantially parallel to the sidewall of the first opening. In any one of claims 1 to 12,
The above oxide semiconductor is a memory device having a carbon concentration of less than 1×10 ²⁰ atoms/cm ³ .