KR20240163511A - Method for memory id allocation, memory, memory module and memory system - Google Patents

Abstract

The memory module comprises a management bus; a plurality of memories connected to the management bus, each of which includes an ID input terminal and an ID output terminal and which are connected to each other in series, and among the plurality of memories, a memory whose signal of its own ID input terminal is activated can set its own ID in response to ID setting information transmitted through the management bus.

Description

METHOD FOR MEMORY ID ALLOCATION, MEMORY, MEMORY MODULE AND MEMORY SYSTEM

This patent document relates to a memory and a memory system including the same.

Memory systems may include various types of memory modules. A memory module may consist of a single memory, but is usually composed of multiple memories for high capacity and high-speed processing.

Each memory in a memory module mainly performs the same operation. For example, if one memory module contains eight memories, read and write operations can be performed simultaneously on these eight memories. However, since each memory in a memory module has differences in location, wiring length, etc., sometimes it is necessary to distinguish them and operate them independently or make specific settings.

Embodiments of the present invention can provide a configuration and method for assigning an ID to distinguish memories.

A memory module according to one embodiment of the present invention comprises: a management bus; a plurality of memories connected to the management bus, each memory including an ID input terminal and an ID output terminal, the plurality of memories being connected in series with each other, wherein a memory among the plurality of memories, the signal of its own ID input terminal being activated, can set its own ID in response to ID setting information transmitted through the management bus.

A method for assigning an ID to a memory according to one embodiment of the present invention may include: a step in which first to fourth memories receive information to set an ID to a first value through a management bus; a step in which a first memory among the first to fourth memories, to which an activated signal is input into an ID input terminal, sets its own ID to the first value; a step in which the first memory outputs an activated signal to its own ID output terminal that is electrically connected to the ID input terminal of the second memory; a step in which the first to fourth memories receive information to set the ID to a second value through the management bus; a step in which a second memory among the first to fourth memories, to which an activated signal is input into an ID input terminal and whose ID has not yet been set, sets its own ID to the second value; and a step in which the second memory outputs an activated signal to its own ID output terminal that is electrically connected to the ID input terminal of the third memory.

According to one embodiment of the present invention, a memory system comprises: a command address bus; a plurality of data buses; a management bus; a plurality of memories, each of which is commonly connected to the management bus, each of which is commonly connected to the command address bus and connected to a data bus corresponding to itself among the plurality of data buses, each of which includes an ID input terminal and an ID output terminal and which are serially connected to each other; a memory controller connected to the plurality of memories through the command address bus and the plurality of data buses; and a baseboard management controller (BMC) connected to the plurality of memories through the management bus, wherein a memory of which a signal of its own ID input terminal is activated among the plurality of memories can set its own ID in response to ID setting information transmitted from the baseboard management controller through the management bus.

A memory module according to one embodiment of the present invention includes a plurality of memories, each of the plurality of memories including a plurality of ID input terminals; a plurality of ID output terminals; and an arithmetic circuit that uses values input to the plurality of ID input terminals to generate values to be output to the plurality of ID output terminals, and can set the values input to the plurality of ID input terminals as its own ID.

A memory according to one embodiment of the present invention may include: a plurality of ID input terminals; a plurality of ID output terminals; an ID setting circuit for setting a value input to the ID input terminals as an ID; and an operation circuit for generating a value to be output to the ID output terminals using the input value.

According to one embodiment of the present invention, a memory may include: a plurality of first ID terminals; a plurality of second ID terminals; an ID setting circuit which sets a value input to the first ID terminals as an ID in a forward mode and sets a value input to the second ID terminals as the ID in a reverse mode; and an arithmetic circuit which generates a value to be output to the second ID terminals using the value input to the first ID terminals in the forward mode and generates a value to be output to the first ID terminals using the value input to the second ID terminals in the reverse mode.

A method for assigning an ID to a memory according to one embodiment of the present invention may include: a step in which a first memory sets a value input to its own ID input terminal as its own ID; a step in which the first memory generates a value to be output to its own ID output terminal using the value input to its own ID input terminal; a step in which a second memory sets a value input to its own ID input terminal electrically connected to the ID output terminal of the first memory as its own ID; and a step in which the second memory generates a value to be output to its own ID output terminal using the value input to its own ID input terminal.

According to embodiments of the present invention, different IDs can be assigned to memories.

Figure 1 is a configuration diagram of a memory system (100) according to one embodiment of the present invention.
Figure 2 is a configuration diagram of one embodiment of the memory module (120) of Figure 1.
Figure 3 is a configuration diagram of one embodiment of the memory (210_1) of Figure 2.
Figure 4 is a configuration diagram of another embodiment of the memory (210_1) of Figure 2.
Figure 5 is a configuration diagram of another embodiment of the memory module (120) of Figure 1.
Figure 6 is a configuration diagram of another embodiment of the memory module (120) of Figure 1.
Figure 7 is a configuration diagram of another embodiment of the memory module (120) of Figure 1.
Figure 8 is a configuration diagram of one embodiment of the memory (710_0) of Figure 7.
FIG. 9 is a diagram illustrating a process of setting the IDs of memories (710_0 to 710_7) of the memory module (120) of FIG. 7.

Hereinafter, embodiments according to the technical idea of the present invention will be described with reference to the attached drawings.

Figure 1 is a configuration diagram of a memory system (100) according to one embodiment of the present invention.

Referring to FIG. 1, a memory system (100) may include a memory controller (110), a memory module (120), and a baseboard management controller (130).

The memory controller (110) can control the operation of the memory module (120). The memory controller (110) can be included in a processor such as a CPU (Central Processing Unit), a GPU (Graphic Processing Unit), or an AP (Application Processor). The memory controller transmits commands and addresses to the memory module (120) through a command address bus (CA_BUS), and can transmit and receive data with the memory module (120) through a data bus (DATA_BUS).

The memory module (120) can perform read operations, write operations, etc. under the control of the memory controller (110). The memory module (120) can perform operations indicated by commands and addresses transmitted through the command address bus (CA_BUS), and during a read operation, it can transmit data to the memory controller (110) through the data bus (DATA_BUS), and during a write operation, it can receive data transmitted from the memory controller (110) through the data bus (DATA_BUS).

The baseboard management controller (BMC) (130) may be a device that performs management and monitoring functions mounted on a basic board of a device such as a server or a PC. The baseboard management controller (130) communicates with a memory module (120) and can manage memories in the memory module (120), and also communicates with a memory controller (110) to check the status of the system and manage the system or diagnose problems. Communication between the baseboard management controller (130) and the memory controller (110) may mainly use an interface (131) called IPMI (Intelligent Platform Management Interface). In addition, communication between the baseboard management controller (130) and the memory module (120) may be performed through a management bus (Manage_BUS). The management bus (Manage_BUS) may use an M3C (Memory Module Management Control) interface similar to an I2C (Inter-Integrated Circuit) interface.

The command address bus (CA_BUS) and the data bus (DATA_BUS) between the memory controller (110) and the memory module (120) are buses used to perform the main function of the memory module (120), and thus this interface is called an in-band interface. In addition, the management bus (Manage_BUS) between the base board management controller (130) and the memory module (120) is a bus used for additional control or management of the memory module (120), and thus this interface is called a side-band interface.

Figure 2 is a configuration diagram of one embodiment of the memory module (120) of Figure 1.

Referring to FIG. 2, the memory module (120) may include a plurality of memories (210_0 to 210_7).

The command address bus (CA_BUS) can be commonly connected to the memories (210_0 to 210_8). Therefore, the memories (210_0 to 210_7) can receive the same command and address from the memory controller (110).

The data bus (DATA_BUS) can be distributed and connected to the memories (210_0 to 210_7). If the data bus (DATA_BUS) between the memory controller (110) and the memory module (120) is 64 bits, the data bus (DATA_BUS) can be distributed and connected to the memories (210_0 to 210_7) in 8-bit increments. Accordingly, the memories (210_0 to 210_7) can transmit and receive different data with the memory controller (110).

The management bus (Manage_BUS) can be commonly connected to the memories (210_0 to 210_7). One of the reasons for using the management bus (Manage_BUS), which is a side-band interface, is to set up the memories (210_0 to 210_7) through the management bus (Manage_BUS) before the memory system (100) is powered up and the command address bus (CA_BUS) and data bus (DATA_BUS), which are in-band interfaces, become available.

Since the locations and wiring lengths of the memories (210_0 to 210_7) within the memory module (120) are different, independent settings may be required for each memory (210_0 to 10_7). To this end, an ID that allows the memories (210_0 to 210_7) to be distinguished from each other is required.

PDA Enumerate ID Programming supported in PDA (Per DRAM Addressability) mode can be used as a method for assigning different IDs to memories (210_0 to 210_7). However, since the PDA mode is a mode that uses a command address bus (CA_BUS) and a data bus (DATA_BUS), which are in-band interfaces, it may not be suitable for the purpose of independently setting the memories (210_0 to 210_7) through the management bus (Manage_BUS) before power-up to enable normal operation of the memory controller (110).

In order to assign different IDs to the memories (210_0 to 210_7) without using an in-band interface, ID input terminals (IDi) and ID output terminals (IDo) are provided in the memories (210_0 to 210_7), and these can be connected to each other in series. For example, the ID output terminals (IDo) of the memory (210_1) can be connected to the ID input terminals (IDi) of the memory (210_2), and the ID output terminals of the memory (210_2) can be connected to the ID input terminals (IDi) of the memory (210_3). <0:3> in the drawing indicates that the number of ID input terminals (IDi) and ID output terminals (IDo) is 4. It should be understood that the number may be different from the example. A fixed voltage can be connected to the ID input terminals (IDi) of the first memory (210_0) among the memories (210_0 to 210_7) connected in series. For example, a ground voltage can be connected to all four ID input terminals (IDi) of the memory (210_0).

The memory module (120) may be of the DIMM (Dual In Line Memory Module) type, and may also be one of other types of form factors such as AIC (Add-in Card) and EDSFF (Enterprise and Data Center SSD Form Factor).

Fig. 3 is a configuration diagram of one embodiment of the memory (210_1) of Fig. 2. Fig. 3 shows only the configuration related to the assignment of IDs in the memory (210_1). The remaining memories (210_0, 210_2, 210_3) may also be configured in the same manner as the memory (210_1).

Referring to FIG. 3, the memory (210_1) may include ID receivers (310), ID transmitters (320), ID setting circuits (330), and operation circuits (340).

The ID receivers (310) can receive signals from the ID input terminals (IDi<0:3>). Since the number of ID input terminals (IDi<0:3>) is exemplified as four, the number of ID receivers (310) can also be four.

The ID setting circuit (330) can set the signals of the ID input terminals (IDi<0:3>) received through the ID receivers (310) to the ID (ID<0:3>) of the memory (210_1). Depending on the design, the ID (ID<0:3>) setting of the ID setting circuit (330) can be performed in synchronization with a signal input from outside the memory (210_1). For example, the ID setting circuit (330) can be designed to set the input signals to the ID (ID<0:3>) at the time when a reset signal input from outside the memory (210_1) transitions from low to high. In addition, the ID receivers (310) can be designed to be inactive after the ID (ID<0:3>) is set by the ID setting circuit (330).

The operation circuit (340) can generate signals to be transmitted to the ID output terminals (IDi<0:3>) via the ID transmitters (320) using the signals of the ID input terminals (IDi<0:3>) received via the ID receivers (310). The operation circuit (340) is an adder and can generate a value to be output by adding a specific value (e.g., 1) to an input value.

The ID transmitters (320) can output values generated by the operation circuit (340) to the ID output terminals (IDo<0:3>).

Through configurations such as those in Fig. 3, the memory (210_1) can set the value input to the ID input terminals (IDi<0:3>) as its own ID (ID<0:3>) and output the value with +1 added to it through the ID output terminals (IDo<0:3>).

Referring back to FIGS. 2 and 3, the memory (210_0) can set the value '0' inputted into its ID input terminals (IDi) as its ID and output '1' through its ID output terminals (IDo). In addition, the memory (210_1) can set the value '1' inputted into its ID input terminals (IDi) as its ID and output '2' through its ID output terminals (IDo). In this manner, the ID of the memory (210_2) can be set to '2', the ID of the memory (210_3) can be set to '3', the ID of the memory (210_4) can be set to '4', the ID of the memory (210_5) can be set to '5', the ID of the memory (210_6) can be set to '6', and the ID of the memory (210_7) can be set to '7'.

FIG. 4 is a configuration diagram of another embodiment of the memory (210_1) of FIG. 2. FIG. 4 shows only the configuration related to the assignment of IDs in the memory (210_1). The remaining memories (210_0, 210_2, 210_3) may also be configured in the same manner as the memory (210_1). The memory (210_1) of FIG. 4 may further have a function added to enable the ID input terminals (IDi) and ID output terminals (IDo) to be interchanged with each other, compared to the memory (210_1) of FIG. 3.

Referring to FIG. 4, the memory (210) may include first ID receivers (410), second ID receivers (415), first ID transmitters (420), second ID transmitters (425), a mirroring signal receiver (417), an inverter (419), a selection circuit (450), an ID setting circuit (430), and an operation circuit (440).

The mirroring signal receiver (417) can receive a mirroring signal (MIR) input from outside the memory (210_1). The mirroring signal (MIR) may be a signal transmitted from another device on the memory module (120) or a device outside the memory module (120), or may be a signal generated in such a way that an input terminal of the mirroring signal receiver (417) is connected to a ground voltage or a power voltage on a substrate of the memory module (120). The inverter (419) can invert the positive mirroring signal (MIRT) received by the mirroring signal receiver (417) to generate a negative mirroring signal (MIRB). When the positive mirroring signal (MIRT) is activated and the negative mirroring signal (MIRB) is deactivated, the memory (210) can operate in a reverse mode, and when the positive mirroring signal (MIRT) is deactivated and the negative mirroring signal (MIRB) is activated, the memory (210) can operate in a forward mode.

The first ID receivers (410) can receive signals of the first ID terminals (IDi<0:3>). The first ID receivers (410) can be activated in a forward mode in which the mirroring signal (MIRB) is activated. Since the number of the first ID terminals (IDi<0:3>) is exemplified as four, the number of the first ID receivers (410) can also be four.

The second ID receivers (415) can receive signals of the second ID terminals (IDo<0:3>). The second ID receivers (415) can be activated in a reverse mode in which a positive mirroring signal (MIRT) is activated. Since the number of the second ID terminals (IDo<0:3>) is exemplified as four, the number of the second ID receivers (415) can also be four. Here, the terminals (IDi<0:3>) are not named ID input terminals but first ID terminals, and the terminals (IDo<0:3>) are not named ID output terminals but second ID terminals, because in the embodiment of FIG. 4, the input terminal and the output terminal are not fixed but can be changed depending on the mode.

The selection circuit (450) can select and output signals (IDin0<0:3>) received through the first ID receivers (410) in the forward mode in which the positive mirroring signal (MIRT) is deactivated, and can select and output signals (IDin1<0:3>) received through the second ID receivers (415) in the reverse mode in which the positive mirroring signal (MIRT) is activated.

The ID setting circuit (430) can set the signals selected by the selection circuit (450) to the ID (ID<0:3>) of the memory (210_1). Accordingly, in the forward mode, the signals (IDin0<0:3>) input to the first ID terminals (IDi<0:3>) can be set to the ID (ID<0:3>), and in the reverse mode, the signals (IDin1<0:3>) input to the second ID terminals (IDo<0:3>) can be set to the ID (ID<0:3>). Depending on the design, the ID (ID<0:3>) setting of the ID setting circuit (430) can be performed in synchronization with a signal input from outside the memory (210_1). For example, the ID setting circuit (430) can be designed to set the input signals to ID (ID<0:3>) at the time when the reset signal input from outside the memory (210_1) transitions from low to high.

The operation circuit (440) can generate output signals (IDout<0:3>) using signals selected by the selection circuit (450). The operation circuit (440) is an adder and can generate a value to be output by adding a specific value (e.g., 1) to an input value.

The first ID transmitters (420) can transmit output signals (IDout<0:3>) of the operation circuit (450) to the first ID terminals (IDi<0:3>). The first ID transmitters (420) can be activated in a reverse mode in which the mirroring signal (MIRT) is activated.

The second ID transmitters (425) can transmit the output signals (IDout<0:3>) of the operation circuit (450) to the second ID terminals (IDo<0:3>). The second ID transmitters (425) can be activated in the forward mode in which the mirroring signal (MIRB) is activated.

Through configurations such as those in FIG. 4, the memory (210_1) can set the value input to the first ID terminals (IDi<0:3>) as its own ID (ID<0:3>) in the forward mode, and output the value obtained by adding +1 to the value through the second ID terminals (IDo<0:3>). In addition, the memory (210_1) can set the value input to the second ID terminals (IDo<0:3>) as its own ID (ID<0:3>) in the reverse mode, and output the value obtained by adding +1 to the value through the first ID terminals (IDi<0:3>).

Referring again to FIGS. 2 and 4, when the memories (210_0 to 210_7) of the memory module (120) operate in the forward mode, a fixed voltage may be connected to the terminals (IDi) of the memory (210_0), as shown in FIG. 2. However, when the memories (210_0 to 210_7) operate in the reverse mode, a fixed voltage may be connected to the terminals (IDo) of the memory (210_7).

Figure 5 is a configuration diagram of another embodiment of the memory module (120) of Figure 1.

In the embodiment of Fig. 5, we will look into an example in which the connection of the ID input terminals (IDi) and the ID output terminals (IDi) of the memories (210_0 to 210_7) is different from the embodiment of Fig. 2. In Fig. 5, the illustration of the buses (CA_BUS, DATA_BUS, Manage_BUS) is omitted.

Referring to FIG. 5, it can be confirmed that the ID input terminals (IDi) and ID output terminals (IDo) of the memories (210_0 to 210_3) are connected in series with each other, and the ID input terminals (IDi) and ID output terminals (IDo) of the memories (210_4 to 210_7) are connected in series with each other.

The ID input terminals (IDi) of the first memory (210_0) among the memories (210_0 to 210_3) are all connected to a ground voltage (VSS), so that the ID of the memory (210_0) can be set to '0', and the input terminals (IDi<0:3>) of the first memory (210_4) among the memories (210_4 to 210_7) are connected to a ground voltage (VSS) and a power supply voltage (VDD) so that they are (0, 1, 0, 0), so that the ID of the memory (210_4) can be set to '4'.

Since the ID of the memory (210_0) is set to '0', the IDs of the memories (210_1 to 210_3) can be set to '1' to '3'. In addition, since the ID of the memory (210_4) is set to '4', the IDs of the memories (210_5 to 210_7) can be set to '5' to '7'.

Figure 6 is a configuration diagram of another embodiment of the memory module (120) of Figure 1.

In the embodiment of Fig. 6, we will look into an example in which the connection of the ID input terminals (IDi) and the ID output terminals (IDi) of the memories (210_0 to 210_7) is different from the embodiments of Figs. 2 and 5. In Fig. 6, the illustration of the buses (CA_BUS, DATA_BUS, Manage_BUS) is omitted.

Referring to FIG. 6, the ID input terminals (IDi) of the memories (210_0 to 210_7) may be respectively connected to a ground voltage (VSS) and a power voltage (VDD) so that the memories (210_0 to 210_7) can be set to different IDs. For example, the ID input terminals (IDi<0:3>) of the memory (210_2) may be connected to a ground voltage (VSS) and a power voltage (VDD) as (0, 0, 1, 0), so that the ID of the memory (210_2) may be set to '2', and the ID input terminals (IDi<0:3>) of the memory (210_5) may be connected to a ground voltage (VSS) and a power voltage (VDD) as (0, 1, 0, 1), so that the ID of the memory (210_5) may be set to '5'.

Fig. 7 is a configuration diagram of another embodiment of the memory module (120) of Fig. 1. The memory module of Fig. 7 can use a method of assigning different IDs to memories (710_0 to 710_7) in a different way from the memory modules of Figs. 2, 5, and 6.

Referring to FIG. 7, the memory module (120) may include a plurality of memories (710_0 to 710_7).

The command address bus (CA_BUS) can be commonly connected to the memories (710_0 to 710_7). Therefore, the memories (710_0 to 710_7) can receive the same command and address from the memory controller (110).

The data bus (DATA_BUS) can be distributed and connected to the memories (710_0 to 710_7). If the data bus (DATA_BUS) between the memory controller (110) and the memory module (120) is 64 bits, the data bus (DATA_BUS) can be distributed and connected to the memories (710_0 to 710_7) in 8-bit increments. Accordingly, the memories (710_0 to 710_7) can transmit and receive different data with the memory controller (110).

The management bus (Manage_BUS) can be commonly connected to the memories (710_0 to 710_7). One of the reasons for using the management bus (Manage_BUS), which is a side-band interface, is to set up the memories (710_0 to 710_7) through the management bus (Manage_BUS) before the memory system (100) is powered up and the command address bus (CA_BUS) and data bus (DATA_BUS), which are in-band interfaces, become available.

In order to assign different IDs to the memories (710_0 to 710_7), an ID input terminal (IDi) and an ID output terminal (IDo) are provided in the memories (710_0 to 710_7), and these can be connected in series with each other. In each of the memories (710_0 to 710_7), one ID input terminal (IDi) and one ID output terminal (IDo) can be used. A fixed voltage can be connected to the ID input terminal (IDi) of the first memory (710_0) among the memories (710_0 to 710_7) connected in series. For example, a ground voltage can be connected to the ID input terminal (IDi) of the memory (710_0).

The memory module (120) may be of the DIMM (Dual In Line Memory Module) type, and may also be one of other types of form factors such as AIC (Add-in Card) and EDSFF (Enterprise and Data Center SSD Form Factor).

Fig. 8 is a configuration diagram of one embodiment of the memory (710_0) of Fig. 7. Fig. 8 shows only the configuration related to the assignment of IDs in the memory (710_0). The remaining memories (710_1 to 710_7) may also be configured in the same manner as the memory (710_0).

Referring to FIG. 8, the memory (710_0) may include an ID receiver (810), an ID transmitter (820), a management bus receiving circuit (830), a decoding circuit (840), and an ID setting circuit (850).

The ID receiver (810) can receive a signal from the ID input terminal (IDi).

The management bus receiving circuit (830) can receive signals of the management bus (Manage_BUS). The management bus (Manage_BUS) can include lines such as a serial clock (SCL) line and a serial data (SDA) line, and the management bus receiving circuit (830) can be configured to receive signals of the lines included in the management bus (Manage_BUS).

The decoding circuit (840) can decode signals transmitted through the management bus (Manage_BUS) to perform an ID setting operation. The decoding circuit (840) can decode signals transmitted through the management bus (Manage_BUS) to set an ID when the voltage level of the signal of the ID input terminal (IDi) received through the ID receiver (810) is an activation level (e.g., ground voltage level) and the ID of the memory (710_0) has not yet been set. The ID setting circuit (850) can store the set ID according to the decoding result of the decoding circuit (840). ID<0:3> in the drawing can represent an ID set by the ID setting circuit (850) according to the instructions of the decoding circuit (840).

The decoding circuit (840) can transmit a signal of an activation level (low level) to the ID transmitter (820) so that a signal of an activation level (ground voltage level) can be output to the ID output terminal (IDo) through the ID transmitter (820) after the ID of the memory (710_0) is set.

FIG. 9 is a diagram illustrating a process of setting the IDs of memories (710_0 to 710_7) of the memory module (120) of FIG. 7. With reference to FIGS. 7 to 9, the process of setting the IDs of memories (710_0 to 710_7) will be described.

Referring to FIG. 9, memories (710_0 to 710_7) can receive a command to set an ID transmitted through the management bus (Manage_BUS) to '0' (901). This command may be transmitted from the baseboard management controller (130) to the management bus (Manage_BUS).

Among the memories (710_0 to 710_7), only the memory (710_0) has a signal of an activation level input to the ID input terminal (IDi), so the decoding circuit (840) of the memory (710_0) decodes the signals transmitted to the management bus (Manage_BUS), and as a result, the ID setting circuit (850) of the memory (710_0) can set the ID (ID<0:3>) of the memory (710_0) to '0' (903). Since the ID of the memory (710_0) has been set, a signal of an activation level can now be output from the ID output terminal (IDo) of the memory (710_0).

Memories (710_0 to 710_7) can receive a command to set the ID to '1' transmitted through the management bus (Manage_BUS) (905). This command may be transmitted from the baseboard management controller (130) to the management bus (Manage_BUS).

Among the memories (710_0 to 710_7), memories (710_0, 710_1) input a signal of an activation level to an ID input terminal (IDi), and since the ID of the memory (710_0) has already been set, the decoding circuit (840) of the memory (710_1) decodes the signals transmitted to the management bus (Manage_BUS), and as a result, the ID setting circuit (850) of the memory (710_1) can set the ID (ID<0:3>) of the memory (710_1) to '1' (907). Since the ID of the memory (710_1) has been set, a signal of an activation level can now be output from the ID output terminal (IDo) of the memory (710_1).

Memories (710_0 to 710_7) can receive a command to set the ID to '2' transmitted through the Manage_BUS (909). This command may be transmitted from the baseboard management controller (130) to the Manage_BUS.

Among the memories (710_0 to 710_7), memories (710_0, 710_1, 710_2) input a signal of an activation level to the ID input terminal (IDi), and since the IDs of the memories (710_0, 710_1) have already been set, the decoding circuit (840) of the memory (710_2) decodes the signals transmitted to the management bus (Manage_BUS), and as a result, the ID setting circuit (850) of the memory (710_2) can set the ID (ID<0:3>) of the memory (710_2) to '2' (911). Since the ID of the memory (710_2) has been set, a signal of an activation level can now be output from the ID output terminal (IDo) of the memory (710_2).

Through the same processes (913, 915, 917, 919, 921, 923, 925, 927, 929, 931), the ID of the memory (710_3) can be set to '3', the ID of the memory (710_4) can be set to '4', the ID of the memory (710_5) can be set to '5', the ID of the memory (710_6) can be set to '6', and the ID of the memory (710_7) can be set to '7'.

The memories (710_0 to 710_7) of the memory module (120) of Fig. 7 receive the same commands from the management bus (Manage_BUS), but by using a method in which only the memories for which an ID has not yet been set decode the commands of the management bus (Manage_BUS) by inputting an activation level signal to the ID input terminal (IDi), it is possible for the memories (710_0 to 710_7) to be set to IDs of different values.

Although the embodiments according to the technical idea of the present invention have been described with reference to the attached drawings, this is only for explaining the embodiments according to the concept of the present invention, and the present invention is not limited to the embodiments. Various forms of substitution, modification, and change of the embodiments may be made by those skilled in the art without departing from the technical idea of the present invention described in the claims, and this will also be considered to fall within the scope of the present invention.

120: Memory Module
210_0~210_7: Memories

Claims (28)

management bus;
A plurality of memories connected to the above management bus, each of which includes an ID input terminal and an ID output terminal and which are connected in series to each other,
Among the above multiple memories, a memory whose ID input terminal signal is activated sets its own ID in response to the ID setting information transmitted through the management bus.
Memory modules.
In paragraph 1,
A fixed activation voltage is input to the ID input terminal of the first memory among the plurality of memories connected in series, and the plurality of memories activate the signal of their ID output terminals after setting their IDs.
Memory modules.
In the second paragraph,
The above multiple memories ignore the ID setting information after their IDs are set.
Memory modules.
In the third paragraph,
The above management bus is connected to the baseboard management controller (BMC) outside the memory module.
Memory modules.
In the third paragraph,
The above management bus uses the Memory Module Management Control (M3C) interface.
Memory modules.
A step of receiving information to set the ID to the first value through the management bus from the first to fourth memories;
A step of setting the ID of the first memory, to which an activated signal is input into the ID input terminal among the first to fourth memories, to the first value;
A step of the first memory outputting an activated signal to its own ID output terminal which is electrically connected to the ID input terminal of the second memory;
A step of receiving information to set the ID to a second value through the management bus by the first to fourth memories;
A step in which an activated signal is input to an ID input terminal among the first to fourth memories and the second memory, whose ID has not yet been set, sets its ID to the second value; and
A step in which the second memory outputs an activated signal to its own ID output terminal, which is electrically connected to the ID input terminal of the third memory.
How to allocate IDs for memory containing .
In paragraph 6,
A step of receiving information to set the ID to a third value through the management bus from the first to fourth memories;
A step in which an activated signal is input to an ID input terminal among the first to fourth memories and a third memory whose ID has not yet been set sets its ID to the third value;
A step of the third memory outputting an activated signal to its own ID output terminal which is electrically connected to the ID input terminal of the fourth memory;
A step of receiving information to set the ID to a fourth value through the management bus from the first to fourth memories;
A step in which an activated signal is input to an ID input terminal among the first to fourth memories and the fourth memory, whose ID has not yet been set, sets its ID to the fourth value; and
The step of the above fourth memory outputting an activated signal to its ID output terminal
A method of allocating an ID for memory that includes more.
In paragraph 6,
The above management bus uses the Memory Module Management Control (M3C) interface.
How to allocate IDs to memory.
In Article 8,
A baseboard management controller (BMC) is connected to the above management bus.
The above baseboard management controller transmits information to set the ID to the first to fourth memories through the management bus.
How to allocate IDs to memory.
command address bus;
Multiple data buses;
management bus;
A plurality of memories, each of which is commonly connected to the management bus, commonly connected to the command address bus, and connected to a data bus corresponding to itself among the plurality of data buses, each of which includes an ID input terminal and an ID output terminal and which are connected to each other in series;
A memory controller connected to the plurality of memories through the command address bus and the plurality of data buses; and
Includes a baseboard management controller (BMC) connected to the plurality of memories through the management bus,
Among the above multiple memories, a memory whose ID input terminal signal is activated sets its own ID in response to ID setting information transmitted from the baseboard management controller through the management bus.
Memory system.
In Article 10,
A fixed activation voltage is input to the ID input terminal of the first memory among the plurality of memories connected in series, and the plurality of memories activate the signal of their ID output terminals after setting their IDs.
Memory system.
In Article 11,
The above multiple memories ignore the ID setting information after their IDs are set.
Memory system.
In Article 12,
The above management bus uses the Memory Module Management Control (M3C) interface.
Memory system.
Contains multiple memories,
Each of the above multiple memories
Multiple ID input terminals;
Multiple ID output terminals; and
It includes an operation circuit that generates a value to be output from the plurality of ID output terminals by using the values input to the plurality of ID input terminals, and sets the value input to the plurality of ID input terminals as its own ID.
Memory modules.
In Article 14,
The above operation circuit is an adder, and the above operation circuit adds a specific value to the input value to generate the output value.
Memory modules.
In Article 14,
The ID input terminals and ID output terminals of the above multiple memories are connected in series.
Memory modules.
In Article 16,
Fixed voltage values are input to the ID input terminals of the first memory among the above multiple memories.
Memory modules.
In Article 14,
The above multiple memories are connected to a baseboard management controller outside the memory module through a management bus.
Memory modules.
In Article 14,
The above multiple memories include memories of the first group and memories of the second group,
The ID input terminals and ID output terminals of the memories of the first group are connected in series,
The ID input terminals and ID output terminals of the memories of the second group are connected in series.
Memory modules.
In Article 20,
Fixed voltage values are input to the ID input terminals of the first memory among the memories of the first group above,
Fixed voltage values of different values from the fixed voltage values input to the ID input terminals of the first memory among the memories of the second group are input to the ID input terminals of the first memory among the memories of the first group.
Memory modules.
Multiple ID input terminals;
Multiple ID output terminals;
An ID setting circuit for setting the values input through the above ID input terminals as IDs; and
An arithmetic circuit that generates values to be output to the ID output terminals using the input values above.
Memory containing .
In Article 21,
The above operation circuit is an adder, and the above operation circuit adds a specific value to the input value to generate the output value.
Memory.
In Article 21,
The above operation circuit operates in synchronization with the reset signal.
Memory.
A number of first ID terminals;
Multiple second ID terminals;
An ID setting circuit that sets the value input to the first ID terminals as the ID in the forward mode and sets the value input to the second ID terminals as the ID in the reverse mode; and
An arithmetic circuit that generates values to be output to the second ID terminals using the values input to the first ID terminals in the forward mode, and generates values to be output to the first ID terminals using the values input to the second ID terminals in the reverse mode.
Memory containing .
In Article 24,
The above operation circuit is an adder, and the above operation circuit generates its output value by adding a specific value to its input value.
Memory.
A step in which the first memory sets the value entered into its own ID input terminal as its own ID;
A step in which the first memory generates a value to be output through its own ID output terminal using the value input through its own ID input terminal;
A step for the second memory to set the value input into its own ID input terminal, which is electrically connected to the ID output terminal of the first memory, as its own ID; and
The step of the above second memory generating a value to be output through its own ID output terminal using the value input through its own ID input terminal
How to allocate IDs for memory containing .
In Article 26,
A step for the third memory to set the value input into its own ID input terminal, which is electrically connected to the ID output terminal of the second memory, as its own ID;
A step in which the third memory generates a value to be output through its own ID output terminal using the value input through its own ID input terminal;
A step in which the fourth memory sets the value input into its own ID input terminal, which is electrically connected to the ID output terminal of the third memory, as its own ID; and
The step of generating a value to be output from the ID output terminal by using the value input to the ID input terminal of the fourth memory above
A method of allocating an ID for memory that includes more.
In Article 26,
In each of the above generating steps, a specific value is added to the input value to generate the output value.
How to allocate IDs to memory.

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