KR20250028906A - Semiconductor Package And Manufacturing Methods Thereof - Google Patents

Abstract

The technical idea of the present invention provides a method for manufacturing a semiconductor package, comprising: a step of dotting water on a package substrate; a step of attaching one or more semiconductor chips on the package substrate to form a chip stack structure; a step of forming a bonding wire electrically connecting the chip stack structure and the package substrate; a step of performing a baking process; and a step of forming a molding layer covering an upper surface of the package substrate, the chip stack structure, and the bonding wire.

Description

Semiconductor package and manufacturing method thereof {Semiconductor Package And Manufacturing Methods Thereof}

The technical field of the present invention relates to a semiconductor package and a method for manufacturing the same.

Recently, the demand for portable devices has been rapidly increasing in the electronic product market, and as a result, the electronic components mounted on these electronic products are continuously required to be miniaturized and lightweight. In order to miniaturize and lightweight the electronic components, the semiconductor packages mounted on them are required to be smaller in size while processing a large amount of data.

The problem that the technical idea of the present invention seeks to solve is to provide a semiconductor package that bonds a semiconductor chip and a package substrate using water.

The problem that the technical idea of the present invention seeks to solve is to provide a method for manufacturing a semiconductor package by bonding a semiconductor chip and a package substrate using water.

The problems to be solved by the technical idea of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

In order to solve the above-described problem, the technical idea of the present invention provides a method for manufacturing a semiconductor package, characterized by including the steps of: dotting water on a package substrate; attaching one or more semiconductor chips on the package substrate to form a chip stack structure; forming bonding wires electrically connecting the chip stack structure and the package substrate; performing a baking process; and forming a molding layer covering the upper surface of the package substrate, the chip stack structure, and the bonding wires.

In addition, the technical idea of the present invention provides a semiconductor package including a package substrate; a chip stack structure including a plurality of semiconductor chips sequentially stacked on an upper surface of the package substrate; bonding wires electrically connecting the chip stack structure and the package substrate; and a molding layer covering the upper surface of the package substrate, the chip stack structure, and the bonding wires, wherein the molding layer fills a first gap between the package substrate and the semiconductor chips and a second gap between two adjacent semiconductor chips among the plurality of semiconductor chips.

According to exemplary embodiments of the present disclosure, by bonding a semiconductor chip and a package substrate using water, a die attach film is not used, thereby reducing the production cost of a semiconductor package.

According to exemplary embodiments of the present disclosure, by bonding a semiconductor chip and a package substrate using water, there is an effect of improving the productivity of a semiconductor package without using a die attach film.

FIG. 1 is a flowchart illustrating a method for manufacturing a semiconductor package according to one embodiment of the present disclosure.
FIG. 2 is a schematic drawing of a semiconductor package according to one embodiment of the present disclosure.
Figure 3 is an enlarged drawing of the EX1 portion of Figure 2.
FIGS. 4 to 10 are drawings schematically illustrating a method for manufacturing a semiconductor package according to one embodiment of the present disclosure.

Hereinafter, embodiments of the technical idea of the present invention will be described in detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof are omitted.

FIG. 1 is a schematic drawing of a semiconductor package according to one embodiment of the present disclosure.

Figure 2 is an enlarged drawing of the EX1 portion of Figure 1.

Referring to FIGS. 1 and 2, a semiconductor package (100) according to one embodiment of the present disclosure may include a chip stack structure (110), a bonding wire (121), a package substrate (130), a molding layer (140), and a connecting bump (150).

In exemplary embodiments, the package substrate (130) may be a Printed Circuit Board (PCB). For example, the package substrate (130) may be a double-sided Printed circuit Board. For example, the package substrate (130) may be a multi-layer Printed circuit Board. When the package substrate (130) is a multi-layer Printed circuit Board, wiring layers may be arranged on the lower surface, upper surface, and interior of the package substrate (130), respectively. However, the present invention is not limited thereto, and for example, the package substrate (130) may be a flexible substrate or a tape substrate.

The package substrate (130) may include an upper substrate pad (131) disposed on an upper surface of the package substrate (130). The upper substrate pad (131) may be embedded in the package substrate (130). An upper surface of the upper substrate pad (131) may be coplanar with an upper surface of the package substrate (130). The package substrate (130) may include a lower substrate pad (132) disposed on a lower surface of the package substrate (130). The lower substrate pad (132) may be embedded in the package substrate (130). An lower surface of the lower substrate pad (132) may be coplanar with an upper surface of the package substrate (130). However, the present invention is not limited thereto, and the upper substrate pad (131) and the lower substrate pad (132) may be disposed to protrude from an upper surface and a lower surface of the package substrate (130), respectively.

A connection bump (150) configured to electrically connect an external device and a semiconductor package (100) may be arranged on the lower substrate pad (132). At this time, the connection bump (150) may be a solder ball. However, the present invention is not limited thereto, and the connection bump (150) may have a structure including a pillar and solder. At this time, the connection bump (150) may include at least one of copper (Cu), silver (Ag), gold (Au), and tin (Sb).

In exemplary embodiments, the package substrate (130) may be formed of at least one material selected from a phenol resin, an epoxy resin, and a polyimide. For example, the package substrate (130) may include at least one material selected from a flame retardant 4 (FR4), a tetrafunctional epoxy, a polyphenylene ether, an epoxy/polyphenylene oxide, a bismaleimide triazine (BT), a thermount, a cyanate ester, a polyimide, and a liquid crystal polymer.

A conductive layer (not shown) may be placed within the package substrate (130). The conductive layer may electrically connect the upper substrate pad (131) and the lower substrate pad (132). In addition, the conductive layer, the lower substrate pad (132), and the connection bump (150) may be electrically connected. At this time, the upper substrate pad (131), the lower substrate pad (132), and the conductive layer may include a metal such as copper or nickel.

The chip stack structure (110) may include one or more semiconductor chips (111) that are vertically stacked on a package substrate (130). Although the chip stack structure (110) is illustrated in this specification as including four semiconductor chips (111) that are vertically stacked, it is not limited thereto. For example, the chip stack structure (110) may include one to three semiconductor chips, or may include five or more semiconductor chips.

The chip stack structure (110) may include a first semiconductor chip (111a), a second semiconductor chip (111b), a third semiconductor chip (111c), and a fourth semiconductor chip (111d). The plurality of semiconductor chips (111) included in the chip stack structure (110) may be sequentially offset and stacked in a horizontal direction. That is, the plurality of semiconductor chips (111) may be stacked in a stepwise manner.

For example, a first semiconductor chip (111a) may be stacked on a package substrate (130), and a second semiconductor chip (111b) may be stacked on the first semiconductor chip (111a) such that a portion thereof protrudes horizontally from the first semiconductor chip (111a). In addition, a third semiconductor chip (111c) may be stacked on the second semiconductor chip (111b) such that a portion thereof protrudes horizontally from the second semiconductor chip (111b). However, the present invention is not limited thereto, and a plurality of semiconductor chips (111) may be stacked such that they overlap in a vertical direction. In addition, a plurality of semiconductor chips (111) may be arranged in a zigzag shape.

The semiconductor chip (111) may include a semiconductor substrate. The semiconductor substrate may include, for example, silicon (Si). Alternatively, the semiconductor substrate may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Alternatively, the semiconductor substrate may have a silicon on insulator (SOI) structure. For example, the semiconductor substrate may include a buried oxide layer (BOX layer). The semiconductor substrate may include a conductive region, for example, a well doped with impurities. The semiconductor substrate may have various device isolation structures such as a shallow trench isolation (STI) structure. The semiconductor substrate may have an active surface and an inactive surface opposite to the active surface.

A plurality of semiconductor chips (111) may be formed with semiconductor devices including various types of a plurality of individual devices on the active surface. The plurality of individual devices may include various microelectronic devices, for example, a MOSFET (metal-oxide-semiconductor field effect transistor) such as a CMOS transistor (complementary metal-insulator-semiconductor transistor), a system LSI (large scale integration), an image sensor such as a CIS (CMOS imaging sensor), a MEMS (micro-electro-mechanical system), an active device, a passive device, etc. The plurality of individual devices may be electrically connected to the conductive region of the semiconductor substrate. The semiconductor device may further include a conductive wire or a conductive plug electrically connecting at least two of the plurality of individual devices, or the plurality of individual devices and the conductive region of the semiconductor substrate. In addition, the plurality of individual devices may be electrically separated from other neighboring individual devices by an insulating film, respectively.

In exemplary embodiments, the plurality of semiconductor chips (111) included in the chip stack structure (110) may be semiconductor chips of the same type. For example, the plurality of semiconductor chips (111) may be memory semiconductor chips. The memory chip may be a volatile memory semiconductor chip, such as, for example, a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory), or a nonvolatile memory semiconductor chip, such as a PRAM (Phase-change Random Access Memory), an MRAM (Magnetoresistive Random Access Memory), a FeRAM (Ferroelectric Random Access Memory), or an RRAM (Resistive Random Access Memory). In some exemplary embodiments, the plurality of semiconductor chips (111) may be a flash memory, for example, a NAND flash memory.

In other exemplary embodiments, the plurality of semiconductor chips (111) included in the chip stack structure (110) may include different types of semiconductor chips. For example, some of the semiconductor chips among the plurality of semiconductor chips (111) may be logic chips, and other some of the semiconductor chips among the plurality of semiconductor chips (111) may be memory chips. For example, the logic chip may be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

In exemplary embodiments, the plurality of semiconductor chips (111) may have the same dimensions. For example, the horizontal width, vertical width, and thickness of the plurality of semiconductor chips (111) may be the same.

In exemplary embodiments, the semiconductor package (100) of the present disclosure may include a bonding pad (123). The bonding pad (123) may be respectively arranged on an exposed area of a plurality of semiconductor chips (111). At this time, the exposed area of the plurality of semiconductor chips (111) may be defined as an area of the upper surface of the semiconductor chip (111) that is not covered by another semiconductor chip (111). For example, the bonding pad (123) may be arranged on an exposed area of the upper surface of a first semiconductor chip (111a) that is not covered by a second semiconductor chip (111b).

In exemplary embodiments, a bonding wire (121) may be formed on one side of the chip stack structure (110). The bonding wire (121) may electrically connect a plurality of bonding pads (123). In addition, the bonding wire (121) may electrically connect a package substrate (130) and the bonding pads (123). For example, the bonding wire (121) may electrically connect an upper substrate pad (131) and one of the plurality of bonding pads (123).

In exemplary embodiments, the semiconductor package (100) of the present disclosure may include a molding layer (140) covering a chip stack structure (110) provided on a package substrate (130). For example, the molding layer (140) may be formed to cover an upper surface of the package substrate (130). In addition, the molding layer (140) may be formed to cover side surfaces and upper surfaces of a plurality of semiconductor chips (111) included in the chip stack structure (110). In addition, the molding layer (140) may be formed to cover a plurality of bonding pads (123) and bonding wires (121). In this case, the molding layer (140) may include an insulating resin or an epoxy molding compound (EMC).

In exemplary embodiments, the molding layer (140) may be formed to fill a first gap (G ₁ ) and a second gap (G ₂ ). The first gap (G ₁ ) may be a space between the package substrate (130) and the first semiconductor chip (111a). At this time, the first semiconductor chip (111a) may mean a semiconductor chip positioned at the bottom among a plurality of semiconductor chips (111). The second gap (G ₂ ) may be a space between two adjacent semiconductor chips. For example, the second gap (G ₂ ) may be a space between the first semiconductor chip (111a) and a second semiconductor chip (111b) positioned on the first semiconductor chip (111a). At this time, the sizes of the first gap (G ₁ ) and the second gap (G ₂ ) may be the same, but are not limited thereto.

The first gap (G ₁ ) and the second gap (G ₂ ) may be spaces formed according to a method for manufacturing a semiconductor package (100) of the present disclosure. The method for manufacturing a semiconductor package (100) of the present disclosure may attach a semiconductor chip (111) onto a package substrate (130) using water. In addition, the method for manufacturing a semiconductor package (100) may attach a plurality of semiconductor chips (111) to each other using water to form a chip stack structure (110).

In the past, a package substrate and a plurality of semiconductor chips were bonded using an adhesive material such as a die attach film. The semiconductor package (100) of the present disclosure bonds the package substrate (130) and the plurality of semiconductor chips (111) using water without using a die attach film, thereby reducing the production cost of the semiconductor package (100). Since the die attach film, which accounts for a significant portion (for example, about 44%) of the material cost of the semiconductor package, is not used, the material cost can be saved. In addition, since the die attach film is not used, the cure process is omitted, thereby improving the productivity of the semiconductor package (100). A method for manufacturing the semiconductor package (100) of the present disclosure will be described in detail below.

FIG. 3 is a flowchart illustrating a method for manufacturing a semiconductor package according to one embodiment of the present disclosure.

FIGS. 4 to 10 are drawings schematically illustrating a method for manufacturing a semiconductor package according to one embodiment of the present disclosure.

Referring to FIGS. 3 and 4, a method for manufacturing a semiconductor package (100) according to an embodiment of the present disclosure may include a step of dotting water (W) on a package substrate (130) (S301). The water (W) may be supplied to a position where a chip stack structure (110, see FIG. 1) is to be formed on the package substrate (130) using a dotting device (200). For example, the water (W) may be supplied to a position where a first semiconductor chip (111a, see FIG. 5) is to be attached on the package substrate (130) using the dotting device (200).

Referring to FIGS. 3 and 5 to 7, a method for manufacturing a semiconductor package (100) according to one embodiment of the present disclosure may include a step of forming a chip stack structure (110) on a package substrate (130) (S302).

Specifically, referring to FIG. 5, a first semiconductor chip (111a) can be attached on a package substrate (130). The first semiconductor chip (111a) can be attached to a location where water (W) is dotted on the package substrate (130). At this time, the process of attaching the first semiconductor chip (111a) to the package substrate (130) can be performed at room temperature.

Referring to FIG. 6, water (W) dotted on a package substrate (130) can form an adhesive layer (112). The adhesive layer (112) can fix the first semiconductor chip (111a) on the package substrate (130). The adhesive layer (112) can fix the first semiconductor chip (111a) on the package substrate (130) by utilizing the adhesive force of water. Specifically, the adhesive layer (112) can fix the first semiconductor chip (111a) on the package substrate (130) by utilizing the force of water and other molecules attracting each other.

In exemplary embodiments, the method for manufacturing a semiconductor package (100) of the present disclosure uses water as an adhesive layer (112) to fix a first semiconductor chip (111a) on a package substrate (130), so that a cure process of a die attach film can be omitted. Accordingly, there is an effect of improving the productivity of the semiconductor package (100).

Referring to FIG. 7, a chip stack structure (110) can be formed on a package substrate (130). The step of dotting water and the step of attaching a semiconductor chip (111) can be repeatedly performed to form a chip stack structure (110) on the package substrate (130).

For example, water may be dotted onto a first semiconductor chip (111a), and a second semiconductor chip (111b) may be attached onto the first semiconductor chip (111a). The second semiconductor chip (111b) may be fixed onto the first semiconductor chip (111a) using the water as an adhesive layer (112). In addition, water may be dotted onto the second semiconductor chip (111b), and a third semiconductor chip (111c) may be attached onto the second semiconductor chip (111b). The third semiconductor chip (111c) may be fixed onto the second semiconductor chip (111b) using the water as an adhesive layer (112). In addition, water may be dotted onto the third semiconductor chip (111c), and a fourth semiconductor chip (111d) may be attached onto the third semiconductor chip (111c). The fourth semiconductor chip (111d) can be fixed on the third semiconductor chip (111c) using the water as an adhesive layer (112). The adhesive layer (112) can fix a plurality of semiconductor chips (111) by utilizing the adhesive force of water.

At this time, the plurality of semiconductor chips (111) may be stacked so as to be offset from each other in the horizontal direction. However, the present invention is not limited thereto, and the plurality of semiconductor chips (111) may be stacked so as to overlap in the vertical direction. In addition, the plurality of semiconductor chips (111) may be arranged in a zigzag shape.

Referring to FIGS. 3 and 8, a method for manufacturing a semiconductor package (100) according to one embodiment of the present disclosure may include a step of forming a bonding wire (121). The bonding wire (121) may electrically connect a chip stack structure (110) and a package substrate (130).

In exemplary embodiments, a plurality of bonding pads (123) are respectively arranged on the exposed areas of a plurality of semiconductor chips (111), and the bonding wires (121) can electrically connect the plurality of bonding pads (123). At this time, the exposed areas of the plurality of semiconductor chips (111) can be defined as areas of the upper surfaces of the semiconductor chips (111) that are not covered by other semiconductor chips (111).

The bonding wire (121) may be formed on one side of the chip stack structure (110). In addition, the bonding wire (121) may electrically connect the package substrate (130) and the bonding pad (123). For example, the bonding wire (121) may electrically connect the upper substrate pad (131) and one of the plurality of bonding pads (123).

In exemplary embodiments, the step of forming the bonding wire (121) may be performed inline with the step of forming the chip stack structure (110). Since the adhesive layer (112) is formed using water, the step of forming the bonding wire (121) and the step of forming the chip stack structure (110) may be connected in one line to prevent process defects.

Referring to FIG. 3 and FIG. 9, a method for manufacturing a semiconductor package (100) according to an embodiment of the present disclosure may include a bake process step (S304). The adhesive layer (112) may be removed by the bake process. The adhesive layer (112) may be completely evaporated by the bake process. At this time, the bake process may be performed at about 125° C., but is not limited thereto.

In exemplary embodiments, a first gap (G ₁ ) and a second gap (G ₂ ) may be formed as the adhesive layer (112) is removed. The first gap (G ₁ ) may be a space between the package substrate (130) and the first semiconductor chip (111a). In this case, the first semiconductor chip (111a) may mean a semiconductor chip positioned at the bottom among a plurality of semiconductor chips (111). The second gap (G ₂ ) may be a space between two adjacent semiconductor chips. For example, the second gap (G ₂ ) may be a space between the first semiconductor chip (111a) and a second semiconductor chip (111b) positioned on the first semiconductor chip (111a).

Since the bonding wire (121) connects a plurality of semiconductor chips (111) and a package substrate (130), and fills the first gap (G ₁ ) and the second gap (G ₂ ) in the step of forming a molding layer immediately thereafter, the chip stack structure (110) can be stably maintained.

Referring to FIG. 3 and FIG. 10, a method for manufacturing a semiconductor package (100) according to one embodiment of the present disclosure may include a step of forming a molding layer (S305).

The molding layer (140) may be formed to cover the package substrate (130) and the chip stack structure (110). For example, the molding layer (140) may be formed to cover the upper surface of the package substrate (130). The molding layer (140) may be formed to cover the side surfaces and upper surfaces of a plurality of semiconductor chips (111) included in the chip stack structure (110). In addition, the molding layer (140) may be formed to cover a plurality of bonding pads (123) and bonding wires (121). At this time, the molding layer (140) may include an insulating resin or an epoxy molding compound (EMC).

In exemplary embodiments, the molding layer (140) may be formed to fill the first gap (G ₁ ) and the second gap (G ₂ ). By filling the first gap (G ₁ ) and the second gap (G ₂ ), the structural stability of the semiconductor package (100) of the present disclosure may be increased. For example, the molding layer (140) may completely fill the first gap (G ₁ ) and the second gap (G ₂ ) so that no voids are generated in the first gap (G ₁ ) and the second gap (G ₂ ).

The method of forming the molding layer (140) can be performed while maintaining the shape of the chip stack structure (110). At this time, the method of forming the molding layer (140) can utilize compression molding, but is not limited thereto. For example, the molding layer (140) can be formed using transfer molding.

The method for manufacturing a semiconductor package (100) of the present disclosure can reduce the production cost of the semiconductor package (100) by bonding a package substrate (130) and a plurality of semiconductor chips (111) using water without using a die attach film. Since the die attach film, which accounts for a significant portion (for example, about 44%) of the material cost of the semiconductor package, is not used, the material cost can be saved. In addition, since the molding layer (140) fills the space of the adhesive layer (112) evaporated during the baking process, the structural stability of the semiconductor package (100) can be maintained.

Referring again to FIGS. 1 and 3, a method for manufacturing a semiconductor package (100) according to one embodiment of the present disclosure may include a step of forming a connecting bump (150) (S306).

A plurality of connection bumps (150) may be arranged on the lower surface of the package substrate (130). The connection bumps (150) may be arranged on the lower substrate pad (132) and configured to electrically connect an external device and the semiconductor package (100). At this time, the connection bumps (150) may be solder balls.

Above, the technical idea of the present invention has been described with reference to the attached drawings, but those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features thereof. Therefore, it should be understood that the above-described embodiments are exemplary in all respects and not restrictive.

100: Semiconductor Package
110: Chip stack structure
111: Semiconductor Chip
121: Bonding wire
130: Package substrate
140: Molding layer

Claims (10)

A step of dotting water onto a package substrate;
A step of forming a chip stack structure by attaching one or more semiconductor chips on the package substrate;
A step of forming a bonding wire electrically connecting the chip stack structure and the package substrate;
Step of performing the baking process;
A method for manufacturing a semiconductor package, comprising the step of forming a molding layer covering the upper surface of the package substrate, the chip stack structure, and the bonding wire. In the first paragraph,
The step of forming the above chip stack structure is:
The water dotted on the above package substrate forms an adhesive layer,
A method for manufacturing a semiconductor package, characterized in that the adhesive layer fixes a first semiconductor chip to the package substrate. In the second paragraph,
The step of forming the above chip stack structure is:
a step of dotting water onto the first semiconductor chip; and
A method for manufacturing a semiconductor package, characterized by comprising the step of fixing a second semiconductor chip on the first semiconductor chip using water dotted on the first semiconductor chip as an adhesive layer. In the third paragraph,
The step of forming the above chip stack structure is:
A method for manufacturing a semiconductor package, characterized by repeating the steps of dotting the water and fixing the semiconductor chip. In the first paragraph,
The step of forming the above chip stack structure is:
A method for manufacturing a semiconductor package, characterized in that the manufacturing process is performed at room temperature. In the first paragraph,
The step of forming the chip stack structure and the step of forming the bonding wire are,
A method for manufacturing a semiconductor package, characterized in that it is performed by connecting inline. In the first paragraph,
The step of performing the above baking process is:
a first gap between the package substrate and the semiconductor chip; and
A method for manufacturing a semiconductor package, characterized by forming a second gap between the semiconductor chips. In Article 7,
The step of forming the above molding layer is:
A method for manufacturing a semiconductor package, characterized by filling the first gap and the second gap. package substrate;
A chip stack structure including a plurality of semiconductor chips sequentially stacked on the upper surface of the package substrate;
Bonding wires electrically connecting the chip stack structure and the package substrate; and
Including a molding layer covering the upper surface of the package substrate, the chip stack structure, and the bonding wire,
A semiconductor package, characterized in that the molding layer fills a first gap between the package substrate and the semiconductor chip and a second gap between two adjacent semiconductor chips among the plurality of semiconductor chips. In Article 9,
The above chip stack structure is,
A semiconductor package comprising a plurality of semiconductor chips stacked in a horizontally offset manner.

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