KR20250095185A - SnO2 channel layer manufacturing method for field effect transistor - Google Patents

Abstract

A method for manufacturing a SnO ₂ channel layer for a field effect transistor is disclosed. The method for manufacturing a SnO ₂ channel layer for a field effect transistor may include annealing an amorphous tin oxide layer at a temperature of 400° C. or less in an air atmosphere.

Description

{SnO2 channel layer manufacturing method for field effect transistor}

The present invention relates to a method for manufacturing a SnO ₂ channel layer for a field effect transistor.

Tin oxide (SnO ₂ ) is one of the materials applicable to monolithic three-dimensional integration (M3D) technology, a new technology for improving integration density based on high mobility and large band gap.

In particular, tin oxide is a material that enables device fabrication at temperatures below 450℃, which is the BEOL compatible transistor process temperature, and enables CMOS formation within the device based on the p-type characteristics of SnO.

Although it has been reported that tin oxide devices are fabricated through sol-gel, sputtering, etc., most of the known tin oxide devices are depletion mode devices, and exhibit characteristics of a current extinction ratio lower than 10 ⁷ .

Accordingly, there is a need to develop a tin oxide-based transistor with high current extinction ratio and field mobility by lowering carrier concentration and controlling the channel.

One object of the present invention is to provide a method for manufacturing a SnO ₂ channel layer for a field effect transistor.

In one aspect, the present invention provides a method for manufacturing a SnO ₂ channel layer for a field effect transistor, comprising annealing an amorphous tin oxide layer at a temperature of 400° C. or less in an air atmosphere.

In one embodiment, the SnO ₂ channel layer is characterized by a thickness of less than 10 nm.

In one embodiment, the SnO ₂ channel layer is characterized by a thickness of 6 nm or less.

In one embodiment, the amorphous tin oxide layer is characterized by being deposited by a thermal atomic layer deposition method.

In one embodiment, the amorphous tin oxide layer is characterized by being deposited on a p-type Si layer and an aluminum oxide layer on the p-type Si layer.

In one embodiment, the SnO ₂ channel layer is characterized by exhibiting enhancement mode operation characteristics at a thickness of 6 nm or less.

In one embodiment, the SnO ₂ channel layer can have an I _on/off of 1.2 × 10 ¹¹ and a μFE (field-effect mobility) of 14.6 cm ² /Vs at a thickness of 6 nm.

According to the present invention, a field-effect transistor including a SnO ₂ channel layer annealed in an air atmosphere exhibits enhancement mode operation characteristics at a channel layer thickness of 6 nm or less, and can exhibit high current extinction ratio (I _on/off ) and field mobility (μFE) at a channel layer thickness of 6 nm.

In addition, the present invention can be applied to the M3D technology, which is a next-generation integrated device technology, because it manufactures devices at a temperature of 450°C or lower, which is a BEOL compatible process temperature, and mass production is possible because the SnO ₂ channel layer is deposited using a mass-producible thermal atomic layer deposition method.

FIG. 1 is a schematic diagram showing a method for manufacturing a SnO ₂ channel layer for a field effect transistor according to an embodiment of the present invention and a method for manufacturing a field effect transistor including the same.
Figures 2 to 5 are drawings showing experimental results according to experimental examples of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. The present invention can be modified in various ways and can have various forms, and specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, but should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention. In describing each drawing, similar reference numerals are used for similar components. In the attached drawings, the dimensions of structures are illustrated larger than actual dimensions in order to ensure clarity of the present invention.

The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprises" or "has" and the like are intended to specify the presence of a feature, number, step, operation, component or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms defined in commonly used dictionaries, such as those defined in common dictionaries, should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly defined in this application.

FIG. 1 is a schematic diagram showing a method for manufacturing a SnO ₂ channel layer for a field effect transistor according to an embodiment of the present invention and a method for manufacturing a field effect transistor including the same.

Referring to FIG. 1, a method for manufacturing a SnO ₂ channel layer for a field effect transistor according to an embodiment of the present invention may include annealing an amorphous tin oxide layer at a temperature of 400° C. or less in an air atmosphere.

In one embodiment, the amorphous tin oxide layer can be deposited by thermal atomic layer deposition. In one embodiment, the amorphous tin oxide layer can be deposited on a p-type Si layer and an aluminum oxide layer on the p-type Si layer. For example, after an aluminum oxide layer is deposited on a p-type Si layer by thermal atomic layer deposition, an amorphous tin oxide layer can be deposited on the aluminum oxide layer by thermal atomic layer deposition.

During the above deposition, the SnO ₂ channel layer can be adjusted to have a thickness of 10 nm or less. Preferably, the SnO ₂ channel layer can be adjusted to have a thickness of 6 nm or less. In the present invention, the operating characteristics can be controlled by adjusting the micro-thickness of the channel layer as described above.

Meanwhile, the present invention may include annealing the deposited amorphous tin oxide layer in an air atmosphere at a temperature of 400° C. or lower. When annealing a SnO ₂ channel layer having a thickness of 10 nm or less in an oxygen atmosphere, a SnO ₂ channel layer having too many background carriers is generated, making it difficult to completely deplete the channel, and when annealing in a nitrogen atmosphere, effective modulation is not possible despite having a relatively lower carrier concentration than when annealing in an oxygen atmosphere. In contrast, when annealing in an air atmosphere containing a mixture of nitrogen and oxygen at a temperature of 400° C. or lower, a high current extinction ratio (I _on/off ) and electric field mobility (μFE) can be exhibited.

In one embodiment, before the annealing, the amorphous tin oxide layer can be etched to control the width, length, etc. of the channel layer. In addition, after the annealing, a field effect transistor can be manufactured by forming source/drain electrodes on the SnO ₂ channel layer. Here, the formation of the source/drain electrodes can be formed using a known technique such as an electron beam deposition method, and is not particularly limited.

According to the present invention, the SnO ₂ channel layer annealed at a temperature of 400° C. or less in an air atmosphere can exhibit enhancement mode operation characteristics at a thickness of 6 nm or less. For example, the SnO ₂ channel layer can exhibit excellent device characteristics of I _on/off of 1.2 × 10 ¹¹ and μFE (field-effect mobility) of 14.6 cm ² /Vs at a thickness of 6 nm.

The present invention can be applied to the M3D technology, which is a next-generation integrated device technology, to manufacture devices at a temperature of 450°C or lower, which is a BEOL compatible process temperature, and secures device characteristics that enable channel control by lowering the carrier concentration through controlling the annealing atmosphere and micro-thickness of the channel layer, and can manufacture a field-effect transistor exhibiting incremental operating characteristics.

Hereinafter, embodiments of the present invention will be described in detail. However, the embodiments described below are only some embodiments of the present invention, and the scope of the present invention is not limited to the embodiments described below.

[Example]

_A 60 nm thick _Al2O3 gate oxide was deposited on heavily doped p-type Si gate oxide using T-ALD (NexusBe Mini™). The deposition was performed at 100°C. Trimethylaluminum (TMA) and deionized _H2O were used as a precursor and a reactant, respectively, for _{the Al2O3} deposition. The typical growth-per-cycle (GPC) rate _{of Al2O3} was measured to be 1.2Å/cycle.

After Al ₂ O ₃ deposition, the sample was taken out and the thermal atomic layer deposition (ALD) chamber was preconditioned for SnO ₂ channel deposition. The SnO ₂ channels were deposited at 200°C using a GPC rate of 0.42 Å/cycle. Tetrakisdimethylaminyl (TDMASn) was used as the precursor for SnO ₂ deposition.

Subsequently, wet etching was performed using a diluted HCl solution to form SnO ₂ mesas. A typical etching rate observed during this process was 0.26 nm/s.

In an embodiment of the present invention, SnO ₂ channels were formed with two channel sizes (width 15 μm, length 30 μm and width 8 μm, length 5 μm). After mesa etching, the SnO ₂ channels were annealed at 400° C. for 2 hours under various ambient conditions including air, O ₂ , and N ₂ . SnO ₂ was etched before annealing because the etching rate significantly decreases when SnO ₂ is recrystallized.

Thereafter, a Ti/Au layer was deposited using an electron beam evaporator for deposition of the source (S) and drain (D). The field effect transistor structure and process flow according to an embodiment of the present invention are illustrated in Fig. 1.

The electrical characteristics of the fabricated field-effect transistor devices were analyzed using a semiconductor parameter analyzer (KEYSIGHT HP4156-C).

[Experimental example]

Amorphous SnO ₂ thin films deposited by thermal atomic layer deposition (T-ALD) are not suitable as transistor channel layers due to their high insulating properties, and therefore require post-deposition annealing to increase conductivity.

Table 1 shows the Hall characteristics of 6.5 nm thick SnO ₂ thin films annealed at 400 °C for 2 h in different gas environments, i.e., air, O ₂ and N ₂ .

Referring to Table 1, when annealed in an O ₂ atmosphere, the SnO ₂ thin films became conductive and exhibited carrier concentration and hole mobility of 1.6 x 10 ²⁰ and 7.8 cm ² /V s, respectively. In contrast, the carrier concentrations of the SnO ₂ thin films annealed in air and N ₂ atmospheres were lower, 1.6 x 10 ¹⁹ and 5.7 x 10 ¹⁹ , respectively. The hole mobility of the N ₂ annealed SnO ₂ thin films was high. However, the conductivity of the SnO ₂ thin films annealed in N ₂ was significantly reduced without capping.

FIG. 2 shows the V _DS -I _DS characteristics of a field effect transistor (FET) including a SnO ₂ channel layer annealed under various conditions according to an embodiment of the present invention as in Table 1. Here, the channel width (W)/length (L) of the FET is 15/30 μm. The output current I _DS was measured with a gate voltage in the range of -10 to 10 V and a step size of 2 V. Referring to FIG. 2, all the FET devices of the present invention exhibited typical output characteristics of a depletion mode FET.

Among the various annealing conditions, the SnO ₂ channel annealed in an O ₂ atmosphere (Fig. 2(a)) showed a higher output current compared to the other devices, indicating higher channel conductivity. In contrast, the device annealed in an N ₂ atmosphere (Fig. 2(b)) showed an output current that was one order of magnitude lower. This lower output current is attributed to the decreased conductivity of the N ₂ annealed channel.

The devices annealed in the air atmosphere (Fig. 2(c)) showed lower I _DS than the devices annealed in the O ₂ atmosphere, but better pinch-off characteristics with clear saturation of I _DS . In addition, all the SnO ₂ FETs fabricated in the present invention showed gate control output characteristics regardless of the annealing environment.

Meanwhile, when the previously reported 20 nm thick SnO ₂ thin film was used, the SnO ₂ annealed in N ₂ atmosphere showed two differences from the SnO ₂ annealed in air atmosphere: the conductivity was more sensitive to the surface and the recrystallization was stronger. This suggests that the N ₂ annealing may generate more surface defect states than other gas environments, which may affect the device operation of the bottom-gate FET. To address this issue, the SnO 2 annealed in N ₂ atmosphere The surfaces of the annealed devices were passivated by depositing a 1.5 nm thick _{Al2O3 capping} layer. With the capping layer, the I _DS value increased by almost a factor of 5, as shown in Fig. 2(d). However, even with the application of the capping, the output current was still lower than that of the other devices. The lower output current of the _N2 annealed devices is attributed to the potential degradation of the film due to surface exposure during the device fabrication process steps between annealing and capping. In addition, enhanced recrystallization was consistently observed under _N2 atmosphere. Excessive oxygen during oxygen annealing inhibits the grain growth of _SnO2 (Han et al.). That is, oxygen-deficient annealing promotes the recrystallization of _SnO2 .

Likewise, in SnO ₂ field-effect transistors, annealing in N ₂ atmosphere results in deterioration of device performance, and as the SnO ₂ channel becomes thinner, the channel conductivity can be much more affected by surface and interface (between grain boundaries) conditions, and contamination such as OH and moisture.

Figure 3 shows the transfer curves (I _DS vs V _GS ) of the device at various V _DS values of 0.1, 0.5, and 1.0 V. Threshold voltage (V _th ), subthreshold swing (SS), and field mobility (μ _FE ) of the FET device (W, L = 15, 30 μm) according to the embodiment of the present invention and current extinction ratio (I _on/off ) The values are shown in Table 2.

As a result, the device with a 6.5 nm thick channel layer exhibited the expected operating characteristics of a depletion mode n-type FET with a negative threshold voltage (V _th ). In an O ₂ atmosphere. The annealed device exhibited higher I _DS than the other devices, as shown in Fig. 2(a). However, because of the higher background carrier concentration in the channel (see Table 1), it was difficult to completely deplete the channel before the gate leakage increased, as shown in Fig. 3(a). As a result, the O ₂ annealed device exhibited an I _on/off of 6.1×10 ⁵ . V _th and SS were -7.6 V and 2 V/dec, respectively.

Regardless of capping, N ₂ annealed devices cannot be effectively gated as shown in Figures 3(b) and (c). This lack of gate controllability is due to enhanced particle growth in the oxygen-poor environment.

Meanwhile, the devices annealed in the air atmosphere showed higher device performance than other annealed atmosphere devices, with I _on/off of 3.7×10 ⁷ , V _th of -4.7 V, and SS of 1.2 V/dec.

Additionally, the transfer curves in dual sweep mode for each device were measured to investigate the interface quality between the gate dielectric and the channel layer, as shown in the inset of Fig. 3.

As a result, all devices were observed to exhibit similar clockwise hysteresis, which is a result of similar levels of defects at or near the Al ₂ O ₃ /SnO ₂ interface, regardless of annealing conditions.

Meanwhile _, as shown in Fig. 4, which is the result of XPS analysis on the non-annealed and annealed SnO ₂ thin films, the O 1s spectrum of the non-annealed SnO ₂ thin film (Fig. 4(a)) can be separated into two binding energies centered at 529.8 ± 0.1 and 530.5 ± 0.1 eV for Sn ²⁺ -O and Sn ⁴⁺ -O, respectively.

For the unannealed SnO ₂ thin films, the XPS results indicate that the films are not conductive due to the lack of V _O as shallow donors. In addition, SnO exhibits p-type conductivity due to cation vacancies, indicating that the conducting electrons can be compensated by cation vacancies.

All three annealing conditions according to the present invention resulted in the formation of V _O as shown in Figs. 4(b)-(d). However, the relative amounts of Sn ⁴⁺ -O and Sn ²⁺ -O bonds varied among samples.

O ₂ -Annealed films (b) showed significant increases in both Sn ⁴⁺ -O and V _O . This is partly due to the lower formation energy of V _O in SnO ₂ compared to SnO . These XPS results are consistent with the Hall and device results, indicating a relatively higher carrier concentration.

The air-annealed film (c) exhibited XPS spectra similar to the O ₂ -annealed film. The difference is the higher fraction of Sn ²⁺ -O and lower amount of V _O observed in the air-annealed film.

Meanwhile, the N ₂ annealed thin film (d) showed suppressed Sn ⁴⁺ -O bond formation. This XPS result shows that the carriers in the N ₂ -annealed SnO ₂ have lower mobility due to the higher density of grain boundaries and trap sites.

Next, the performance of the SnO ₂ channels annealed in air atmosphere was further investigated with reference to Fig. 5.

The results show that I _DS increases as the channel length decreases at given V _GS and V _DS , which is mainly due to the decrease in channel resistance.

For the smallest device manufactured according to an embodiment of the present invention, the channel width and length were 8 μm and 5 μm, respectively (Fig. 5(a)), and the device exhibited I _{on/off of} 3×10 ⁹ , SS of 0.6 V/dec, V _th of -4.5 V, and μ _FE of 10.3 cm ² /Vs. Additionally, the channel thickness was fine-tuned after identifying the optimal annealing conditions to improve the device performance. As a result, the V _th value significantly shifted from -5.8 to 8 V as the channel thickness decreased from 7 nm to 5 nm (Fig. 5(b)).

Referring to Table 2 and FIGS. 5(c) and (d), the present invention exhibited the highest performance in a 6 nm thick channel with W and L of 15 μm and 30 μm, respectively. The device was operated in enhancement mode with V _th of 1.1 V and exhibited I _on/off of 1.2 × 10 ¹¹ , μ _FE of 14.6 cm ² /Vs, and SS of 0.4 V/dec. Further optimization of the gate oxide and metal contacts can lead to lower SS, higher mobility, and consequently higher output current in the SnO ₂ FET.

Table 3 compares the performance of metal oxide channel layer FET devices.

Channel Process/Annealing Channel W/L
(㎛) Gate/
thickness(nm) Channel thickness V _th
(V) I _on/off SS
(V/dec) μFE
(cm ² / V s) In ₂ O ₃ PE-ALD/O ₂ 350℃ 20/40 Al ₂ O ₃ /175 5 -1.18 ~10 ⁷ 0.27 39.2 SnO ₂ T-ALD/Air 400℃ 15/30 Al ₂ O ₃ /60 6 1.1 1.24x10 ¹¹ 0.4 14.6

Referring to Table 3, In ₂ O ₃ FETs with a field mobility (μ _FE ) of 39.2 cm ² /Vs were fabricated through process optimization such as plasma-enhanced ALD (PE-ALD) and annealing conditions ( H.-I. Yeom, J. B. Ko, G. Mun, S.-H. K. Park, High mobility polycrystalline indium oxide thin-film transistors by means of plasma-enhanced atomic layer deposition, J. Mater. Chem. C. 4 (2016) 6873-6880, ). However, devices with enhancement mode operation characteristics using In ₂ O ₃ are not fabricated because of the high background carrier density.

Compared with the amorphous In-containing oxide channel layer devices, the T-ALD SnO ₂ channels fabricated in the examples of the present invention exhibited lower carrier densities. The μ _FE of the SnO ₂ FET exhibited excellent ON/OFF controllability while operating in the augmented mode of operation, which is particularly promising for memory-on-logic applications.

Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims (7)

Comprising annealing an amorphous tin oxide layer at a temperature of 400°C or less in an air atmosphere.
Method for fabricating SnO ₂ channel layer for field effect transistor. In the first paragraph,
The SnO ₂ channel layer is characterized by a thickness of less than 10 nm.
Method for fabricating SnO ₂ channel layer for field effect transistor. In the first paragraph,
The SnO ₂ channel layer is characterized by a thickness of 6 nm or less.
Method for fabricating SnO ₂ channel layer for field effect transistor. In the second paragraph,
The above amorphous tin oxide layer is characterized by being deposited by a thermal atomic layer deposition method.
Method for fabricating SnO ₂ channel layer for field effect transistor. In paragraph 4,
The amorphous tin oxide layer is characterized in that it is deposited on a p-type Si layer and an aluminum oxide layer on the p-type Si layer.
Method for fabricating SnO ₂ channel layer for field effect transistor. In paragraph 5,
The SnO ₂ channel layer is characterized by exhibiting enhancement mode operation characteristics at a thickness of 6 nm or less.
Method for fabricating SnO ₂ channel layer for field effect transistor. In Article 6,
The SnO ₂ channel layer has a thickness of 6 nm, an I _on/off of 1.2 × 10 ¹¹ , and a μFE (field-effect mobility) of 14.6 cm ² /Vs.
Method for fabricating SnO ₂ channel layer for field effect transistor.