KR20250103114A - Self Feeding Oscillator and N stages Oscillator for Output Power Maximization by Transistor Phase Optimization - Google Patents

Abstract

A single-feeding oscillator for maximizing output power through transistor phase optimization may comprise an active network including a first transistor and a second transistor; and a passive network including a first capacitor connected between a gate of the first transistor and a ground, a first inductor connected between a drain of the first transistor and a gate of the second transistor, a second capacitor connected between the drain of the first transistor and the ground, a third capacitor connected between the gate of the second transistor and the ground, a second inductor connected between the drain of the second transistor and the gate of the first transistor, and a fourth capacitor connected between the drain of the second transistor and the ground.

Description

{Self Feeding Oscillator and N stages Oscillator for Output Power Maximization by Transistor Phase Optimization}

The present invention relates to single-feeding oscillator and N-stage oscillator technologies for maximizing output power through transistor phase optimization.

With the exponential growth of wireless data communications, the development of next-generation cellular technologies such as 5G and 6G has attracted significant attention. In order to serve a larger user base and achieve higher data rates, it has become essential to utilize a wider frequency spectrum, which has led to the adoption of mm-Wave/sub-THz (0.1-1 THz) frequencies. However, these frequencies can be difficult to achieve because the channel loss is quite high, requiring very high local oscillator (LO) output power.

The present invention aims to provide a single-feeding oscillator and an N-stage oscillator for maximizing output power through transistor phase optimization that can overcome the limitations of achieving high output due to the limited power gain of conventional transistors and the loss of passive components at high frequencies (>100 GHz).

In addition, the present invention aims to provide a core using the Gmax technique that does not occupy a large area by reducing the length of a transmission line, and a wideband high gain ultra-high frequency differential amplifier using the same.

A single-feeding oscillator for maximizing output power through transistor phase optimization to achieve the above-described purpose may be configured with an active network including a first transistor and a second transistor; and a passive network including a first capacitor connected between a gate and a ground of the first transistor, a first inductor connected between a drain of the first transistor and a gate of the second transistor, a second capacitor connected between the drain of the first transistor and the ground, a third capacitor connected between the gate of the second transistor and the ground, a second inductor connected between the drain of the second transistor and the gate of the first transistor, and a fourth capacitor connected between the drain of the second transistor and the ground.

A single-feeding oscillator for maximizing output power through transistor phase optimization may further include a third inductor connected between the gate and the drain of the first transistor and a fourth inductor connected between the gate and the drain of the second transistor.

A single-feeding oscillator for maximizing output power through transistor phase optimization may further include an output summing unit connected to the drain of the first transistor and the drain of the second transistor, and combining the outputs of the first transistor and the second transistor.

The first admittances of the first capacitor and the third capacitor are obtained through the following [Mathematical Formula 1], and the values of the first capacitor and the third capacitor can be calculated from the first admittance.

Here, Y _11: is the short-circuit input admittance of the transistor,

Y _12: is the reverse transconductance of the transistor.

Y _21: is the forward transconductance of the transistor.

Y _22: Short circuit output admittance of the transistor.

Aopt: Precomputed optimal transistor gain

△θ: Total phase shift required per stage at target oscillation frequency

The second admittances of the first inductor and the second inductor are obtained through the following [Mathematical Formula 2], and the values of the first inductor and the second inductor can be calculated from the second admittance.

Here, Y _11: is the short-circuit input admittance of the transistor,

Y _12: is the reverse transconductance of the transistor.

Y _21: is the forward transconductance of the transistor.

Y _22: Short circuit output admittance of the transistor.

Aopt: Precomputed optimal transistor gain

△θ: Total phase shift required per stage at target oscillation frequency

The third admittance of the second capacitor and the fourth capacitor is obtained through [Mathematical Formula 3] below, and the values of the third capacitor and the fourth capacitor can be calculated from the third admittance.

Here, Y _11: is the short-circuit input admittance of the transistor,

Y _12: is the reverse transconductance of the transistor.

Y _21: is the forward transconductance of the transistor.

Y _22: Short circuit output admittance of the transistor.

Aopt: Precomputed optimal transistor gain

△θ: Total phase shift required per stage at target oscillation frequency

According to another embodiment of the present invention, an N-stage oscillator for maximizing output power through transistor phase optimization may include an active network and a passive network connected to a preceding stage of the active network, which are repeatedly connected N times, wherein the active network includes a first transistor and a second transistor, and the passive network may include a first capacitor connected between a gate of the first transistor and a ground, a first inductor connected between a drain of the first transistor and a gate of the second transistor, a second capacitor connected between the drain of the first transistor and the ground, a third capacitor connected between the gate of the second transistor and the ground, a second inductor connected between the drain of the second transistor and the gate of the first transistor, and a fourth capacitor connected between the drain of the second transistor and the ground.

An N-stage oscillator for maximizing output power through transistor phase optimization may further include an output summing unit connected to a drain of a first transistor and a drain of the second transistor, and combining outputs of the first transistor and the second transistor.

According to another embodiment of the present invention, an N-stage oscillator for maximizing output power through transistor phase optimization may include an active network and a passive network connected to a preceding stage of the active network, which are repeatedly connected N times, wherein the active network includes a first transistor and a second transistor, and the passive network may include a first capacitor connected between a gate and a ground of the first transistor, a first inductor connected between a drain of the first transistor and a gate of the second transistor, a second capacitor connected between the drain of the first transistor and the ground, a third capacitor connected between the gate and the ground of the second transistor, a second inductor connected between the drain of the second transistor and the gate of the first transistor, a fourth capacitor connected between the drain of the second transistor and the ground, a third inductor connected between the gate and the drain of the first transistor, and a fourth inductor connected between the gate and the drain of the second transistor.

In order to maximize the output power through transistor phase optimization, the effective inductance (L _fd ) in the differential mode of the N-stage oscillator is calculated as shown in [Mathematical Formula 4] below.

The effective inductance (L _fd ) in the common mode can be calculated as shown in [Mathematical Formula 5] below.

According to the present invention, the output can be increased by combining a passive network at the front end of an active network.

In addition, according to the present invention, the driving in the differential mode can be suppressed and the effective inductance can be reduced in the common mode to increase the output power.

FIG. 1 is a diagram illustrating a circuit of a single-feeding oscillator for maximizing output power through transistor phase optimization according to one embodiment of the present invention.
FIG. 2 is a circuit model illustrating a single stage of a single-feeding oscillator for maximizing output power through transistor phase optimization according to one embodiment of the present invention.
Figure 3 is a graph explaining the change in the values of admittances according to phase shift.
FIG. 4 is a diagram illustrating a circuit of a single-feeding oscillator for maximizing output power through transistor phase optimization according to another embodiment of the present invention.
Figure 5 is a diagram for explaining an equivalent circuit in differential mode of the oscillator of Figure 4.
Fig. 6 is a diagram for explaining the equivalent circuit in the in-phase mode of the oscillator of Fig. 4.
Figure 7 is a graph explaining the conductance in the in-phase mode and the differential mode depending on the presence or absence of L _gd .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. The embodiments of the present invention may be modified in various forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. These embodiments are provided to explain the present invention in more detail to those skilled in the art to which the present invention pertains.

FIG. 1 is a diagram illustrating a circuit of a single-feeding oscillator for maximizing output power through transistor phase optimization according to one embodiment of the present invention.

Referring to FIG. 1, a single-feeding oscillator (100) for maximizing output power through transistor phase optimization includes a first transistor (110), a first capacitor (120), a first inductor (130), a second capacitor (140), a second transistor (150), a third capacitor (160), a second inductor (170), a fourth capacitor (180), and an output summation unit (190).

The first transistor (110) is an active network, and as the frequency increases, the difference from the optimal phase shift value becomes greater.

The first capacitor (120) is connected between the gate of the first transistor (110) and the ground.

The first inductor (130) is connected between the drain of the first transistor (110) and the gate of the second transistor (150).

A second capacitor (140) is connected between the drain of the first transistor (110) and the ground.

The second transistor (150) is an active network, and as the frequency increases, the difference from the optimal phase shift value becomes greater.

A third capacitor (160) is connected between the gate of the second transistor (150) and the ground.

A second inductor (170) can be connected between the drain of the second transistor (150) and the gate of the first transistor (110).

A fourth capacitor (180) can be connected between the drain (150) of the second transistor and ground.

The passive network includes a first capacitor (120), a first inductor (130), a second capacitor (140), a third capacitor (160), a second inductor (170), and a fourth capacitor (180).

The output summing unit (190) is connected to the drain of the first transistor (110) and the drain of the second transistor (150), and can sum the outputs of the first transistor (110) and the second transistor (150) and output them.

FIG. 2 is a circuit model illustrating a single stage of a single-feeding oscillator for maximizing output power through transistor phase optimization according to one embodiment of the present invention.

Referring to FIGS. 1 and 2, a circuit model (200) for explaining a single stage can be represented by an active network (210) and a passive network (220).

In this embodiment, the active network (210) represents a first transistor (110) or a second transistor (120), and corresponds to one transistor.

The passive network (220) represents a first capacitor (120), a first inductor (130), a second capacitor (140) or a third capacitor (160), a second inductor (170), and a fourth capacitor (180), corresponding to two capacitors and one inductor.

For example, the first admittance (Y _g ) may correspond to the first capacitor (120), the second admittance (Y _f ) may correspond to the first inductor (130), and the third admittance (Y _d ) may correspond to the second capacitor (140).

Below, the process of calculating the first admittance (Yg), second admittance (Yf), and third admittance (Yd) will be explained.

The active network (210) is defined as follows in terms of Y parameters.

The manual network (220) is defined as follows by Y-parameter.

Next, using the mathematical formula above, we can derive the Y-parameter below.

Since the generator is self-contained with no external current injection, assuming I ₁ = I ₂ = 0 and V ₂ /V ₁ = A _opt , the solution for the passive network components can be obtained as follows.

Here, Y _11: is the short-circuit input admittance of the transistor,

Y _12: is the reverse transconductance of the transistor.

Y _21: is the forward transconductance of the transistor.

Y _22: Short circuit output admittance of the transistor.

Aopt: Precomputed optimal transistor gain

△θ: Total phase shift required per stage at target oscillation frequency

The first admittance (Yg) of the first capacitor or the third capacitor is obtained through the above [Mathematical Formula 1], and the values of the first capacitor and the third capacitor can be calculated from the first admittance. For example, the admittance of the capacitor is calculated as Y=j*2*π*frequency*capacitance. Accordingly, when the admittance to be implemented as a capacitor is Yg, the value (capacitance) of the capacitor is calculated as Yg/(j*2*π*frequency).

Here, Y _11: is the short-circuit input admittance of the transistor,

Y _12: is the reverse transconductance of the transistor.

Y _21: is the forward transconductance of the transistor.

Y _22: Short circuit output admittance of the transistor.

Aopt: Precomputed optimal transistor gain

△θ: Total phase shift required per stage at target oscillation frequency

The second admittance (Y _f ) of the first inductor and the second inductor can be calculated from the second admittance, which is obtained through the above [Mathematical Formula 2]. For example, the admittance of a cross-connected inductor in a differential circuit is calculated as Y = j / (2 * π * frequency * inductance). Therefore, when the admittance to be implemented as an inductor is Y _f , the value (inductance) of the inductor is calculated as Y _f *2 * π * frequency / j.

Here, Y _11: is the short-circuit input admittance of the transistor,

Y _12: is the reverse transconductance of the transistor.

Y _21: is the forward transconductance of the transistor.

Y _22: Short circuit output admittance of the transistor.

Aopt: Precomputed optimal transistor gain

△θ: Total phase shift required per stage at target oscillation frequency

The third admittance (Y _d) of the second capacitor and the fourth capacitor is obtained through the above [Mathematical Formula 3], and the values of the third capacitor and the fourth capacitor can be calculated from the third admittance.

Figure 3 is a graph explaining the change in the values of admittances according to phase shift.

Referring to FIGS. 2 and 3, FIG. 3 shows an example of values of Y _g , Y _d , and Y _f for optimal transistor gain according to △θ at 150 GHz.

△θ can be determined by considering the number of stages and the implementation of the power combining network. For example, if △θ = 30° is selected, at least N = 12 is required to make the sum of the phase deviations of all stages an integer multiple of 2π. In this case, a total of 11 unwanted vibration modes occur, and combining the output power of 12 stages is very complicated in terms of layout.

Accordingly, in the present invention, for simplicity, △θ = 0° is selected to minimize the number of vibration modes and an N=2 power-coupled oscillator that can be implemented using only a simpler power coupling network is implemented.

FIG. 4 is a diagram illustrating a circuit of a single-feeding oscillator for maximizing output power through transistor phase optimization according to another embodiment of the present invention.

Referring to FIG. 4, a single-feeding oscillator (100) for maximizing output power through transistor phase optimization includes a first transistor (110), a first capacitor (120), a first inductor (130), a second capacitor (140), a second transistor (150), a third capacitor (160), a second inductor (170), a fourth capacitor (180), an output summing unit (190), a third inductor (195), and a fourth inductor (196).

The first transistor (110) is an active network, and as the frequency increases, the difference from the optimal phase shift value becomes greater.

The first capacitor (120) is connected between the gate of the first transistor (110) and the ground.

The first inductor (130) is connected between the drain of the first transistor (110) and the gate of the second transistor (150).

A second capacitor (140) is connected between the drain of the first transistor (110) and ground.

The second transistor (150) is an active network, and as the frequency increases, the difference from the optimal phase shift value becomes greater.

A third capacitor (160) is connected between the gate of the second transistor (150) and the ground.

A second inductor (170) can be connected between the drain of the second transistor (150) and the gate of the first transistor (110).

A fourth capacitor (180) can be connected between the drain (150) of the second transistor and ground.

The passive network includes a first capacitor (120), a first inductor (130), a second capacitor (140), a third capacitor (160), a second inductor (170), and a fourth capacitor (180).

The output summing unit (190) is connected to the drain of the first transistor (110) and the drain of the second transistor (150), and can sum the outputs of the first transistor (110) and the second transistor (150) and output them.

A third inductor (195) is connected between the gate and drain of the first transistor (110).

The fourth inductor (196) is connected between the gate and drain of the second transistor (150).

The two-stage oscillator according to the present embodiment can have two oscillation modes, in-phase/common mode and differential mode, respectively, since there are two values of △θ that satisfy N*△θ = m*2π, which are 0˚ and 180˚.

Among these, the differential mode (△θ = 180˚) requires additional components such as a balun for power coupling, but the in-phase oscillation mode (△θ = 0) can be easily implemented as a power coupling network by simply combining, making it suitable for increasing output power.

Therefore, in the present invention, in order to minimize unnecessary differential mode occurrence and maximize common mode occurrence, a third inductor (L _gd ) (195) and a fourth inductor (196) (L _gd ) are added between the drain terminal and the gate terminal of each transistor.

FIG. 5 is a drawing for explaining an equivalent circuit in differential mode of the oscillator of FIG. 4, and FIG. 6 is a drawing for explaining an equivalent circuit in in-phase mode of the oscillator of FIG. 4.

Referring to Fig. 5, the effective inductance (L _fd ) in differential mode is calculated as shown in [Mathematical Formula 4] below.

Referring to Fig. 6, the effective inductance (L _fd ) in the common mode is calculated as shown in [Mathematical Formula 5] below.

From the above equation, we can see that when L _f = L _gd , the effective inductance (L _fd ) in the differential mode increases infinitely, eliminating the cross-coupling of the transistor. Therefore, the oscillator cannot operate in the differential mode.

On the other hand, in the in-mode/common mode, adding L _gd reduces the effective inductance (L _fc ), so the output power can be further increased while maintaining the same oscillation frequency by increasing the transistor size.

Figure 7 is a graph explaining the conductance in the in-phase mode and the differential mode depending on the presence or absence of L _gd .

Referring to Fig. 7, if there is no inductor (L _gd ), g _diff ( As shown in the graph (labeled w/o L _gd ), the differential conductance (g _diff ) has negative values at frequencies below 120 GHz, indicating that differential oscillation may occur at these frequencies.

If we add an inductor (L _gd ), g _diff ( As shown in the graph (labeled with L _gd ), the differential mode is suppressed as the differential conductance (g _diff ) is positive at all frequencies.

In the common mode/in-common mode, the conductance (g _com ) is g _com ( As can be seen from the graph shown as with and w/o L _gd , it does not change regardless of the presence of the inductor (L _gd ) and is negative only within the required oscillation frequency band.

The configuration and operation method of the embodiments described above are not limited. The embodiments described above may be configured so that various modifications can be made by selectively combining all or part of each embodiment.

Claims (14)

An active network comprising a first transistor and a second transistor; and
A single-feeding oscillator for maximizing output power through transistor phase optimization, comprising a passive network including a first capacitor connected between the gate and ground of the first transistor, a first inductor connected between the drain of the first transistor and the gate of the second transistor, a second capacitor connected between the drain of the first transistor and the ground, a third capacitor connected between the gate of the second transistor and the ground, a second inductor connected between the drain of the second transistor and the gate of the first transistor, and a fourth capacitor connected between the drain of the second transistor and the ground.
In paragraph 1,
A single-feeding oscillator for maximizing output power through transistor phase optimization, further comprising a third inductor connected between the gate and the drain of the first transistor and a fourth inductor connected between the gate and the drain of the second transistor.
In paragraph 1,
A single-feeding oscillator for maximizing output power through transistor phase optimization, further comprising an output summing unit connected to the drain of the first transistor and the drain of the second transistor, the outputs of the first transistor and the second transistor being combined.
In paragraph 1,
The first admittance of the first capacitor and the third capacitor is obtained through the following [Mathematical Formula 1], and the values of the first capacitor and the third capacitor are calculated from the first admittance.

Here, Y _11: is the short-circuit input admittance of the transistor,
Y _12: is the reverse transconductance of the transistor.
Y _21: is the forward transconductance of the transistor.
Y _22: Short circuit output admittance of the transistor.
Aopt: Precomputed optimal transistor gain
△θ: Total phase shift required per stage at target oscillation frequency
Single-feeding oscillator for maximizing output power through transistor phase optimization.
In paragraph 1,
The second admittance of the first inductor and the second inductor is obtained through the following [Mathematical Formula 2], and the values of the first inductor and the second inductor are calculated from the second admittance.

Here, Y _11: is the short-circuit input admittance of the transistor,
Y _12: is the reverse transconductance of the transistor.
Y _21: is the forward transconductance of the transistor.
Y _22: Short circuit output admittance of the transistor.
Aopt: Precomputed optimal transistor gain
△θ: Total phase shift required per stage at target oscillation frequency
Single-feeding oscillator for maximizing output power through transistor phase optimization.
In paragraph 5,
The third admittance of the second capacitor and the fourth capacitor is obtained through the following [Mathematical Formula 3], and the values of the third capacitor and the fourth capacitor are calculated from the third admittance.

Here, Y _11: is the short-circuit input admittance of the transistor,
Y _12: is the reverse transconductance of the transistor.
Y _21: is the forward transconductance of the transistor.
Y _22: Short circuit output admittance of the transistor.
Aopt: Precomputed optimal transistor gain
△θ: Total phase shift required per stage at target oscillation frequency
Single-feeding oscillator for maximizing output power through transistor phase optimization.
In the second paragraph,
The effective inductance (L _fd ) in differential mode is calculated as shown in [Mathematical Formula 4] below.

The effective inductance (L _fd ) in the common mode is calculated as shown in [Mathematical Formula 5] below.

Single-feeding oscillator for maximizing output power through transistor phase optimization.
An active network and a passive network connected to the front end of the active network are repeatedly connected N times,
The above active network is,
comprising a first transistor and a second transistor,
The above manual network is,
An N-stage oscillator for maximizing output power through transistor phase optimization, comprising: a first capacitor connected between a gate of the first transistor and a ground, a first inductor connected between a drain of the first transistor and a gate of the second transistor, a second capacitor connected between the drain of the first transistor and a ground, a third capacitor connected between the gate of the second transistor and a ground, a second inductor connected between the drain of the second transistor and the gate of the first transistor, and a fourth capacitor connected between the drain of the second transistor and a ground.
In Article 8,
An N-stage oscillator for maximizing output power through transistor phase optimization, further comprising an output summing unit connected to the drain of the first transistor and the drain of the second transistor and combining the outputs of the first transistor and the second transistor.
In Article 8,
The first admittance of the first capacitor and the third capacitor is obtained through the following [Mathematical Formula 1], and the values of the first capacitor and the third capacitor are calculated from the first admittance.

Here, Y _11: is the short-circuit input admittance of the transistor,
Y _12: is the reverse transconductance of the transistor.
Y _21: is the forward transconductance of the transistor.
Y _22: Short circuit output admittance of the transistor.
Aopt: Precomputed optimal transistor gain
△θ: Total phase shift required per stage at target oscillation frequency
N-stage oscillator for maximizing output power through transistor phase optimization.
In Article 8,
The second admittance of the first inductor and the second inductor is obtained through the following [Mathematical Formula 2], and the values of the first inductor and the second inductor are calculated from the second admittance.

Here, Y _11: is the short-circuit input admittance of the transistor,
Y _12: is the reverse transconductance of the transistor.
Y _21: is the forward transconductance of the transistor.
Y _22: Short circuit output admittance of the transistor.
Aopt: Precomputed optimal transistor gain
△θ: Total phase shift required per stage at target oscillation frequency
N-stage oscillator for maximizing output power through transistor phase optimization.
In Article 8,
The third admittance of the second capacitor and the fourth capacitor is obtained through the following [Mathematical Formula 3], and the values of the third capacitor and the fourth capacitor are calculated from the third admittance.

Here, Y _11: is the short-circuit input admittance of the transistor,
Y _12: is the reverse transconductance of the transistor.
Y _21: is the forward transconductance of the transistor.
Y _22: Short circuit output admittance of the transistor.
Aopt: Precomputed optimal transistor gain
△θ: Total phase shift required per stage at target oscillation frequency
N-stage oscillator for maximizing output power through transistor phase optimization.
An active network and a passive network connected to the front end of the active network are repeatedly connected N times,
The above active network is,
comprising a first transistor and a second transistor,
The above manual network is,
An N-stage oscillator for maximizing output power through transistor phase optimization, comprising: a first capacitor connected between a gate and a ground of the first transistor, a first inductor connected between a drain of the first transistor and a gate of the second transistor, a second capacitor connected between the drain of the first transistor and the ground, a third capacitor connected between the gate of the second transistor and the ground, a second inductor connected between the drain of the second transistor and the gate of the first transistor, a fourth capacitor connected between the drain of the second transistor and the ground, a third inductor connected between the gate and the drain of the first transistor, and a fourth inductor connected between the gate and the drain of the second transistor.
In Article 13,
The effective inductance (L _fd ) in differential mode is calculated as shown in [Mathematical Formula 4] below.

The effective inductance (L _fd ) in the common mode is calculated as shown in [Mathematical Formula 5] below.

N-stage oscillator for maximizing output power through transistor phase optimization.

Images