KR20250123266A - Semiconductor package and method of manufacturing the semiconductor package - Google Patents

Abstract

A semiconductor package includes a first semiconductor chip having rear bonding pads on a rear surface, a second semiconductor chip disposed on the first semiconductor chip and having front bonding pads on a front surface, and conductive bump structures disposed between the first semiconductor chip and the second semiconductor chip and connecting the rear bonding pads and the front bonding pads, respectively. Each of the conductive bump structures includes a first bump disposed on the rear bonding pad and having a planar shape corresponding to a shape of an upper surface of the rear bonding pads and having a hemispherical shape that increases in height toward the center, and a second bump bonded to the first bump.

Description

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

The present invention relates to a semiconductor package and a method for manufacturing a semiconductor package, and more particularly, to a semiconductor package in which a plurality of semiconductor chips are stacked and a method for manufacturing the same.

In order to manufacture a multi-chip package in which at least four semiconductor chips are stacked, the semiconductor chips can be electrically connected using solder bumps. When connecting the semiconductor chips, a non-conductive film (NCF) can be placed on the semiconductor chip to cover the solder bumps, and then a thermocompression (TC) process can be performed to melt the solder bumps at a high temperature to bond them. If the thickness of the non-conductive film on the solder bumps is not constant, or the temperature distribution on the semiconductor chip or the distribution of pressure applied during the thermocompression process is not uniform, poor bonding may occur. To prevent poor bonding, a protrusion can be formed on the bonding pad where the solder bumps are bonded, but there is a problem in that a separate exposure process is required to form the protrusions. In addition, there is a problem in that wettability is reduced due to a difference in physical properties between the protrusions and the solder bumps, resulting in poor bonding.

An object of the present invention is to provide a semiconductor package capable of preventing defects from occurring in a thermal compression process.

Another object of the present invention is to provide a method for manufacturing the semiconductor package described above.

According to exemplary embodiments for achieving the above object of the present invention, a semiconductor package includes a first semiconductor chip having rear bonding pads on a rear surface, a second semiconductor chip disposed on the first semiconductor chip and having front bonding pads on a front surface, and conductive bump structures disposed between the first semiconductor chip and the second semiconductor chip and connecting the rear bonding pads and the front bonding pads, respectively, wherein each of the conductive bump structures includes a first bump disposed on the rear bonding pad, having a planar shape corresponding to a shape of an upper surface of the rear bonding pads, and having a hemispherical shape whose height increases toward the center, and a second bump bonded to the first bump.

According to exemplary embodiments for achieving the above object of the present invention, a semiconductor package includes first to fourth semiconductor chips sequentially stacked via conductive bump structures, and adhesive layers for filling spaces between the conductive bump structures and attaching the first to fourth semiconductor chips, wherein each of the first to fourth semiconductor chips has front bonding pads on a front surface, and each of the first to third semiconductor chips has rear bonding pads on a rear surface, and each of the conductive bump structures includes a first bump disposed on the rear bonding pad, having a planar shape corresponding to a shape of an upper surface of the rear bonding pad and having a hemispherical shape whose height increases toward the center, and a second bump bonded to the first bump.

According to exemplary embodiments, a semiconductor package may include a first semiconductor chip having rear bonding pads on a rear surface, a second semiconductor chip disposed on the first semiconductor chip and having front bonding pads on a front surface, and conductive bump structures disposed between the first semiconductor chip and the second semiconductor chip and connecting the rear bonding pads and the front bonding pads, respectively. Each of the conductive bump structures may include a first bump disposed on the rear bonding pad and having a planar shape corresponding to a shape of an upper surface of the rear bonding pads and having a hemispherical shape that increases in height toward the center, and a second bump bonded to the first bump.

Since the first bump has a hemispherical shape with a height increasing toward the center, when performing a thermal compression process, stress is concentrated in the central portion of the first bump, so that a penetration force can be applied to the second bump and the adhesive layer covering the second bump. Accordingly, the conductive bump structures on a plurality of semiconductor chips can be effectively bonded regardless of the height of the applied adhesive layer. In addition, since the first bump and the second bump include similar materials, they can provide high wettability when performing a thermal compression process, thereby reducing adhesion failure of the solder bump.

However, the effects of the present invention are not limited to the above-mentioned effects, and may be expanded in various ways without departing from the spirit and scope of the present invention.

FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments.
Figure 2 is an enlarged cross-sectional view showing part A of Figure 1.
Figure 3 is an enlarged cross-sectional view showing part B of Figure 1.
FIGS. 4 to 17 are drawings illustrating a method for manufacturing a semiconductor package according to exemplary embodiments.

Hereinafter, with reference to the attached drawings, a preferred embodiment of the present invention will be described in more detail.

Fig. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. Fig. 2 is an enlarged cross-sectional view showing part A of Fig. 1. Fig. 3 is an enlarged cross-sectional view showing part B of Fig. 1.

Referring to FIGS. 1 to 3, a semiconductor package (10) may include a first semiconductor chip (100a), second to fifth semiconductor chips (100b, 100c, 100d, 100e) sequentially stacked on the first semiconductor chip (100a), and a molding member (400) covering the second to fifth semiconductor chips (100b, 100c, 100d, 100e) on the first semiconductor chip (100a). In addition, the semiconductor package (10) may further include conductive bump structures (200) provided between the first to fifth semiconductor chips (100a, 100b, 100c, 100d, 100e). In addition, the semiconductor package (10) may further include adhesive layers (300) interposed between the first to fifth semiconductor chips (100a, 100b, 100c, 100d, 100e) and conductive bumps (500) provided on the lower surface of the first semiconductor chip (100a).

In this embodiment, the second to fifth semiconductor chips (100b, 100c, 100d, 100e) may be substantially identical or similar to each other. Accordingly, identical or similar components are indicated by identical or similar reference numerals, and further repetitive descriptions of identical components may be omitted.

The first to fifth semiconductor chips (100a, 100b, 100c, 100d, 100e) may be stacked on a package substrate such as a printed circuit board (PCB) or an interposer. In the present embodiment, the semiconductor package as a multi-chip package is exemplified as including five stacked semiconductor chips (100). However, it will be understood that the present invention is not limited thereto. For example, the semiconductor package may include four, eight, twelve, or sixteen stacked semiconductor chips on the first semiconductor chip.

For example, the semiconductor package (10) may include a High Bandwidth Memory (HBM) device. The HBM package may have a high bandwidth memory interface for faster data exchange with a processor chip. The HBM package may have an input/output (TSV I/O) structure including a large number of through-silicon via structures to implement the high bandwidth interface. The processor chip requiring support of the HBM package may be a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, a microcontroller, an application processor (AP), a digital signal processing core, and an application-specific integrated circuit (ASIC) chip including an interface for signal exchange.

A semiconductor package (10) may include a first semiconductor chip (100a) as a sequentially stacked buffer die and second to fifth semiconductor chips (100b, 100c, 100d, 100e) as memory dies. The first to fifth semiconductor chips (100a, 100b, 100c, 100d, 100e) may be electrically connected by first to fourth through-electrodes (150a, 150b, 150c, 150d). The memory die may include a memory element, and the buffer die may include a controller that controls the memory element.

In exemplary embodiments, the first semiconductor chip (100a) may include a first semiconductor substrate (110a), a front insulating film (120) provided on a first surface (112) of the first semiconductor substrate (110a), front bonding pads (142) provided on the front insulating film (120), first through-electrodes (150a) penetrating the first semiconductor substrate (110a), and back bonding pads (144) provided on a second surface (114) of the first semiconductor substrate (110a).

A first semiconductor substrate (110a) may have a first surface (112) and a second surface (114) that are opposite to each other. The first surface (112) may be an active surface, and the second surface (114) may be an inactive surface. Circuit patterns may be provided on the first surface (112) of the first semiconductor substrate (110a). The first surface (112) may be referred to as a front side surface on which the circuit patterns are formed, and the second surface (114) may be referred to as a backside surface. For example, the first semiconductor substrate (110a) may be a single crystal silicon substrate. The circuit patterns may include transistors, capacitors, diodes, and the like. The circuit patterns may constitute circuit elements. Therefore, the first semiconductor substrate (110a) may be a semiconductor device having a plurality of circuit elements formed therein.

As illustrated in FIG. 2, a front insulating film (120) may be formed on the first surface (112), i.e., the front surface, of the first semiconductor substrate (110a). The front insulating film (120) may include a plurality of insulating layers and wirings (123) within the insulating layers. In addition, front bonding pads (142) may be provided on the outermost insulating layer of the front insulating film (120).

For example, the front insulating film (120) may include a metal wiring layer (122) and a passivation film (124). The metal wiring layer (122) may include a plurality of wirings (123) therein. For example, the metal wiring layer (122) may include a metal wiring structure having a plurality of wirings (123) vertically stacked on buffer films and insulating films. The front bonding pad (142) may be formed on an uppermost wiring among the plurality of wirings (123). For example, the wirings may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof. The passivation film (124) is formed on the metal wiring layer (122) and may expose at least a portion of the front bonding pad (142). The front bonding pad (142) may be provided on the passivation film (124). The front bonding pad (142) can be exposed through the outer surface of the passivation film (124).

A first through silicon via (TSV) (150a) may vertically penetrate the interlayer insulating film and extend from a first surface (112) of a first semiconductor substrate (110a) to a second surface (114). The first through silicon via (TSV) (150a) may contact the lowermost wiring of the metal wiring structure. Accordingly, the first through silicon via (TSV) (150a) may be electrically connected to a front bonding pad (142) via wirings (123).

The rear insulating film (130) may be formed on the second surface (114), i.e., the rear surface, of the first semiconductor substrate (110a). The rear insulating film (130) may be provided with a rear bonding pad (144). For example, the rear bonding pad (144) may be disposed on the exposed surface of the first through-electrode (150a). The rear insulating film (130) may include silicon oxide, carbon-doped silicon oxide, silicon carbonitride (SiCN), or the like. Accordingly, the front and rear bonding pads (142, 144) may be electrically connected to each other by the first through-electrode (150a).

In exemplary embodiments, the second semiconductor chip (100b) may include a second semiconductor substrate (110b), a front insulating film (120) provided on a first surface of the second semiconductor substrate and having a front bonding pad (142), and a rear insulating film (130) provided on a second surface of the second semiconductor substrate and having a rear bonding pad (144). In addition, the second semiconductor chip (100b) may further include a second through-electrode (150b) penetrating the second semiconductor substrate and electrically connected to the front and rear bonding pads (142, 144).

Specifically, the second semiconductor substrate (110b) may have a first surface (112) and a second surface (114) that are opposite to each other. The first surface may be an active surface, and the second surface may be a non-active surface. Circuit elements may be formed on the first surface (112) of the second semiconductor substrate (110b). The circuit elements may include a plurality of memory elements. Examples of the memory elements include volatile semiconductor memory elements and non-volatile semiconductor memory elements. An interlayer insulating film covering the circuit elements may be formed on the first surface (112) of the second semiconductor substrate (110b).

As illustrated in FIG. 2, the front insulating film (120) may be formed as an interlayer insulating film on the first surface (112) of the second semiconductor substrate (110b), i.e., the front surface. The front insulating film (120) may include a plurality of insulating layers and wirings (123) within the insulating layers. In addition, front bonding pads (142) may be provided on the outermost insulating layer of the front insulating film (120).

For example, the front insulating film (120) may include a metal wiring layer (122) and a passivation film (124). The metal wiring layer (122) may include a plurality of wirings (123) therein. For example, the metal wiring layer (122) may include a metal wiring structure having a plurality of wirings (123) vertically stacked on buffer films and insulating films. The front bonding pad (142) may be formed on an uppermost wiring among the plurality of wirings (123). For example, the wirings may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof. The passivation film (124) is formed on the metal wiring layer (122) and may expose at least a portion of the front bonding pad (142). The front bonding pad (142) may be provided on the passivation film (124). The front bonding pad (142) can be exposed through the outer surface of the passivation film (124).

A second through silicon via (TSV) (150b) may vertically penetrate the interlayer insulating film and extend from the first surface (112) to the second surface (114) of the second semiconductor substrate (110b). The second through silicon via (TSV) (150b) may contact the lowermost wiring of the metal wiring structure. Accordingly, the second through silicon via (TSV) (150b) may be electrically connected to the front bonding pad (142) via the wirings (123).

The rear insulating film (130) may be formed on the second surface (114), i.e., the rear surface, of the second semiconductor substrate (110b). The rear insulating film (130) may be provided with a rear bonding pad (144). For example, the rear bonding pad (144) may be disposed on the exposed surface of the second through-electrode (150b). The rear insulating film (130) may include silicon oxide, carbon-doped silicon oxide, silicon carbonitride (SiCN), or the like. Accordingly, the front and rear bonding pads (142, 144) may be electrically connected to each other by the second through-electrode (150b).

In exemplary embodiments, a second semiconductor chip (100b) may be stacked on a first semiconductor chip (100a) by conductive bump structures (200). The conductive bump structure (200) may include a first bump (210) and a second bump (220). The conductive bump structure (200) may be provided between a back bonding pad (144) on a second surface (114) of the first semiconductor chip (100a) and a front bonding pad (142) on a first surface (112) of the second semiconductor chip (100b). The conductive bump structure (200) may electrically connect the back bonding pad and the lower bonding pad.

The first bump (210) may be provided on the rear bonding pad (144) on the first surface (112) of the first semiconductor chip (100a). The lower surface of the first bump (210) may have the same shape as the planar shape of the rear bonding pad (144). The first bump (210) may have a hemispherical structure whose height increases toward the center and may cover the rear bonding pad (144). For example, the first bump (210) may have a dome shape with a curved surface and may protrude in a direction perpendicular to the rear bonding pad (144). The height (H1) of the first bump (210) may be 5 μm or less. The ratio of the width (D1) of the rear bonding pad to the height (H1) of the first bump (210) may be 25 or less. Since the first bump (210) may have a shape in which the central portion protrudes the highest, when performing a thermocompression (TC) process, stress may be concentrated in the central portion to provide penetration force to the second bump (220).

The material of the first bump (210) may include a tin (Sn) series alloy. For example, the material of the first bump (210) may include at least one of a Sn-Sb alloy, a Sn-Mg alloy, a Sn-Zn alloy, and a Sn-Bi alloy. Since the second bump (220) also includes a tin (Sn) series metal, when performing the thermal compression process, the second bump (220) and the first bump (210) having similar compositions may be bonded to each other to have high wettability. The first bump (210) may include a material having a melting point similar to the melting point of the material of the second bump (220). Preferably, the first bump (210) may include a material having a melting point equal to or higher than the melting point of the material of the second bump (220). The first bump (210) may include a material having a higher yield strength than the yield strength of the material of the second bump (220). Accordingly, when the thermal compression process is performed, the first bump (210) may have a higher mechanical strength than the second bump (220), so that when the first bump and the connecting bump come into contact, the connecting bump may be relatively deformed to cover the first bump (210).

An adhesive layer (300) may be provided to fill a space between a conductive bump structure (200) between a first semiconductor chip (100a) and a second semiconductor chip (100b). Specifically, as illustrated in FIG. 2, the adhesive layer (300) may be provided between a back insulating film (130) of the first semiconductor chip (100a) and a passivation film (124) of a front insulating film (120) of the second semiconductor chip (100b). The adhesive layer (300) may include a non-conductive adhesive. For example, the adhesive layer (300) may include a non-conductive film (NCF).

For example, the second semiconductor chip (100b) and the first semiconductor chip (100a) can be attached to each other by a thermal compression process using the non-conductive film. In the thermal compression process, the non-conductive film is liquefied and has fluidity, and can flow between the conductive bump structure (200) between the second semiconductor chip (100b) and the first semiconductor chip (100a) and then harden to fill the space therebetween. A portion of the hardened adhesive layer (300) can protrude from the side surface of the second semiconductor chip (100b).

As illustrated in FIG. 3, the third semiconductor chip (100c) may include a third semiconductor substrate (110c), a front insulating film (120) provided on a first surface of the second semiconductor substrate and having a front bonding pad (142), and a rear insulating film (130) provided on a second surface of the third semiconductor substrate and having a rear bonding pad (144). In addition, the third semiconductor chip (100c) may further include a third through-electrode (150c) that penetrates the second semiconductor substrate and is electrically connected to the front and rear bonding pads (142, 144).

Specifically, the third semiconductor substrate (110c) may have a first surface (112) and a second surface (114) that are opposite to each other. The first surface may be an active surface, and the second surface may be a non-active surface. Circuit elements may be formed on the first surface (112) of the second semiconductor substrate (110b). The circuit elements may include a plurality of memory elements. Examples of the memory elements include volatile semiconductor memory elements and non-volatile semiconductor memory elements. An interlayer insulating film covering the circuit elements may be formed on the first surface (112) of the third semiconductor substrate (110c).

As illustrated in FIG. 3, the front insulating film (120) may be formed as an interlayer insulating film on the first surface (112) of the third semiconductor substrate (110c), i.e., the front surface. The front insulating film (120) may include a plurality of insulating layers and wirings (123) within the insulating layers. In addition, the outermost insulating layer of the front insulating film (120) may be provided with front bonding pads (142).

For example, the front insulating film (120) may include a metal wiring layer (122) and a passivation film (124). The metal wiring layer (122) may include a plurality of wirings (123) therein. For example, the metal wiring layer (122) may include a metal wiring structure having a plurality of wirings (123) vertically stacked on buffer films and insulating films. The front bonding pad (142) may be formed on an uppermost wiring among the plurality of wirings (123). For example, the wirings may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof. The passivation film (124) is formed on the metal wiring layer (122) and may expose at least a portion of the front bonding pad (142). The front bonding pad (142) may be provided on the passivation film (124). The front bonding pad (142) can be exposed through the outer surface of the passivation film (124).

A third through silicon via (TSV) (150c) may vertically penetrate the interlayer insulating film and extend from the first surface (112) to the second surface (114) of the third semiconductor substrate (110c). The third through silicon via (TSV) (150c) may contact the lowermost wiring of the metal wiring structure. Accordingly, the third through silicon via (TSV) (150c) may be electrically connected to the front bonding pad (142) via the wirings (123).

The rear insulating film (130) may be formed on the second surface (114), i.e., the rear surface, of the third semiconductor substrate (110c). The rear insulating film (130) may be provided with a rear bonding pad (144). For example, the rear bonding pad (144) may be disposed on the exposed surface of the third through-electrode (150c). The rear insulating film (130) may include silicon oxide, carbon-doped silicon oxide, silicon carbonitride (SiCN), or the like. Accordingly, the front and rear bonding pads (142, 144) may be electrically connected to each other by the third through-electrode (150c).

In exemplary embodiments, a third semiconductor chip (100c) may be stacked on a second semiconductor chip (100b) by conductive bump structures (200). The conductive bump structure (200) may include a first bump (210) and a second bump (220). The conductive bump structure (200) may be provided between a back bonding pad (144) on a second surface (114) of the second semiconductor chip (100b) and a front bonding pad (142) on a first surface (112) of the third semiconductor chip (100c). The conductive bump structure (200) may electrically connect the back bonding pad and the lower bonding pad.

Additionally, the adhesive layer (300) may be provided to fill the space between the conductive bump structure (200) between the second semiconductor chip (100b) and the third semiconductor chip (100c).

In exemplary embodiments, a fourth semiconductor chip (100d) may be stacked on a third semiconductor chip (100c) by conductive bump structures (200). The conductive bump structure (200) may include a first bump (210) and a second bump (220). The conductive bump structure (200) may be provided between a back bonding pad (144) on a second surface (114) of the third semiconductor chip (100c) and a front bonding pad (142) on a first surface (112) of the fourth semiconductor chip (100d). The conductive bump structure (200) may electrically connect the back bonding pad and the lower bonding pad.

Additionally, the adhesive layer (300) may be provided to fill the space between the conductive bump structure (200) between the third semiconductor chip (100c) and the fourth semiconductor chip (100d).

In exemplary embodiments, a fifth semiconductor chip (100e) may be stacked on a fourth semiconductor chip (100d) by conductive bump structures (200). The conductive bump structure (200) may include a first bump (210) and a second bump (220). The conductive bump structure (200) may be provided between a back bonding pad (144) on a second surface (114) of the fourth semiconductor chip (100d) and a front bonding pad (142) on a first surface (112) of the fifth semiconductor chip (100e). The conductive bump structure (200) may electrically connect the back bonding pad and the lower bonding pad.

Additionally, the adhesive layer (300) may be provided to fill the space between the conductive bump structure (200) between the fourth semiconductor chip (100d) and the fifth semiconductor chip (100e).

As described above, the semiconductor package (10) may include second to fifth semiconductor chips (100b, 100c, 100d, 100e) sequentially stacked on a first semiconductor chip (100a) via conductive bump structures (200).

Hereinafter, a method for manufacturing the semiconductor package of FIG. 1 will be described. The description will focus on the case where the semiconductor package includes a High Bandwidth Memory (HBM) device. However, it will be understood that the method for manufacturing the semiconductor package according to the exemplary embodiments is not limited thereto.

FIGS. 4 to 17 are drawings illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIG. 5 is an enlarged cross-sectional view illustrating portion C of FIG. 4. FIGS. 7 and 8 are enlarged cross-sectional views illustrating portion D of FIG. 6. FIG. 10 is an enlarged cross-sectional view illustrating portion E of FIG. 9. FIG. 13 is an enlarged cross-sectional view illustrating portion F of FIG. 12. FIG. 15 is an enlarged cross-sectional view illustrating portion G of FIG. 14.

Referring to FIGS. 4 and 5, a second wafer (W2) having a plurality of second semiconductor chips (dies) formed thereon can be provided.

In exemplary embodiments, the second wafer (W2) may include a second semiconductor substrate (110b) having a first surface (112) and a second surface (114) opposite the first surface (112). The second wafer (W2) may include a die area (DA) and a scribe lane area (SA) surrounding the die area (DA). The second wafer (W2) may be subsequently cut along the scribe lane area (SA) that separates the plurality of die areas (DA) of the second wafer (W2) by a sawing process to thereby individualize the plurality of second semiconductor chips.

Circuit elements may be formed in a die area (DA) on a first surface (112) of a second semiconductor substrate (110b). The circuit elements may include a plurality of memory elements. Examples of the memory elements include volatile semiconductor memory elements and non-volatile semiconductor memory elements. Examples of the volatile semiconductor memory elements include DRAM, SRAM, etc. Examples of the non-volatile semiconductor memory elements include EPROM, EEPROM, Flash EEPROM, etc.

For example, the second semiconductor substrate (110b) may include a semiconductor material such as silicon, germanium, silicon-germanium, or a group III-V compound semiconductor such as gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), or the like. According to some embodiments, the second semiconductor substrate (110b) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

The circuit patterns may include transistors, capacitors, diodes, etc. The circuit patterns may constitute circuit elements. Accordingly, the semiconductor chip may be a semiconductor device having a plurality of circuit elements formed therein. The circuit patterns may be formed by performing a FEOL (Front End of Line) process for manufacturing semiconductor elements on a first surface (112) of a second semiconductor substrate (110b). The surface of the substrate on which the FEOL process is performed may be referred to as the front side surface of the substrate, and the surface opposite to the front side may be referred to as the backside surface.

The circuit element may include a plurality of memory elements. Examples of the memory elements include volatile semiconductor memory elements and non-volatile semiconductor memory elements. Examples of the volatile semiconductor memory elements include DRAM, SRAM, etc. Examples of the non-volatile semiconductor memory elements include EPROM, EEPROM, Flash EEPROM, etc.

In exemplary embodiments, the second wafer (W2) may include a second semiconductor substrate (110b) and a front insulating film (120) having front bonding pads (142) on an outer surface thereof. The front insulating film (120) may include a plurality of insulating layers and wires (123) within the insulating layers. In addition, a front bonding pad (142) may be provided on the outermost insulating layer of the front insulating film (120). In addition, the second wafer (W2) may include a plurality of second through-electrodes (150b) that are provided within the second semiconductor substrate (110b) and are electrically connected to the front bonding pads (142).

The second wafer (W2) may include second bumps (220) provided on front bonding pads (142) on the front insulating film (120). The second bumps (220) may include solder bumps. The second wafer (W2) may be bonded to a carrier substrate (C1) having an adhesive film on an upper surface. The adhesive film may be filled between the second bumps (220).

As illustrated in FIG. 5, for example, the front insulating film (120) may include a metal wiring layer (122) and a passivation film (124).

The metal wiring layer (122) may include a plurality of wires (123) therein. For example, the metal wiring layer (122) may include a metal wiring structure having a plurality of wires (123) vertically stacked on buffer films and insulating films. The front bonding pad (142) may be formed on the uppermost wire among the plurality of wires (123). For example, the wires may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

A passivation film (124) is formed on the metal wiring layer (122) and may expose at least a portion of the front bonding pad (142). The passivation film (124) may include a plurality of stacked insulating films. For example, the passivation film (124) may be sequentially stacked and include a first passivation film including an oxide film and a second passivation film including a nitride film. The first passivation film may include silicon oxide, and the second passivation film may include silicon nitride or silicon carbonitride.

A front bonding pad (142) may be provided on the passivation film (124). The front bonding pad (142) may be exposed through the outer surface of the passivation film (124). Although not shown in the drawing, an interlayer insulating film may be provided on the first surface (112) of the second semiconductor substrate (110b) to cover the circuit patterns. The interlayer insulating film may be formed to include, for example, silicon oxide or a low-k material. The interlayer insulating film may include lower wirings electrically connected to the circuit patterns therein. Accordingly, the circuit pattern may be electrically connected to the front bonding pad (142) by the lower wirings and the wirings.

A second through silicon via (TSV) (150b) may vertically penetrate the interlayer insulating film and extend from the first surface (112) of the second semiconductor substrate (110b) to a predetermined depth. The second through silicon via (TSV) (150b) may contact the lowest wiring of the metal wiring structure. Accordingly, the second through silicon via (TSV) (150b) may be electrically connected to the front bonding pad (142) via the wirings (123).

A liner film (not shown) may be provided on the outer surface of the second through-hole electrode (150b). The liner film may include silicon oxide or carbon-doped silicon oxide. The liner film may electrically insulate the second through-hole electrode (150b) from the second semiconductor substrate (110b) and the first metal wiring layer (122).

The second through-electrode (150b) and the front bonding pad (142) may comprise the same metal. For example, the metal may comprise copper (Cu). However, the present invention is not limited thereto, and may comprise a material (e.g., gold (Au)) that can be bonded by mutual diffusion of metals through a high-temperature annealing process.

Referring to FIGS. 6 to 8, the second surface (114) of the second semiconductor substrate (110b) is partially removed to expose one end of the second through-hole electrode (150b), and a rear insulating film (130) and a first bump (210) can be formed.

As illustrated in FIG. 6, in exemplary embodiments, the second surface (114) of the second semiconductor substrate (110b) may be partially removed using a substrate support system (WSS). First, a second wafer (W2) is attached on a carrier substrate (C1) using an adhesive film, and then the second surface (114) of the second semiconductor substrate (110b) may be partially removed until a portion of the second through-electrode (150b) is exposed.

First, a grinding process, such as a back lap process, may be performed to partially remove the second surface (114) of the second semiconductor substrate (110b), and then an etching process, such as a silicon recess process, may be performed to expose one end of the second through-electrode (150b). Accordingly, the thickness of the second semiconductor substrate (110b) may be reduced to a desired thickness. For example, the second semiconductor substrate (110b) may have a thickness range of about 20 μm to 50 μm.

The above backlap process can grind the entire back surface of the second wafer (W2). The above silicon recess process can selectively etch only silicon on the back surface of the second wafer (W2). The etching process can be an isotropic dry etching process. The etching process can include a plasma etching process, etc. The plasma etching process can be performed using an inductively coupled plasma, a capacitively coupled plasma, a microwave plasma, etc.

Since the grinding process and the etching process are performed at the wafer level, the thickness can be reduced to a uniform thickness across the entire second surface (114) of the second semiconductor substrate (110b). Accordingly, one end of the second through-electrodes (150b) can protrude from the second surface (114) of the second semiconductor substrate (110b) to have the same heights across the entire second surface (114) of the second semiconductor substrate (110b).

As shown in FIGS. 7 and 8, a rear bonding pad (144), a first bump (210), and a rear insulating film (130) can be formed on the outer surface of the second surface (114) of the second semiconductor substrate (110b).

The rear insulating film (130) may expose one end of the second through-electrodes (150b). The one end of the second through-electrodes (150b) protrudes from the second surface (114) of the second semiconductor substrate (110b), and the rear insulating film (130) may cover the sidewalls of the one end of the second through-electrodes (150b) protruding from the second surface (114) of the second semiconductor substrate (110b). Accordingly, the upper surfaces of the second through-electrodes (150b) may be exposed by the rear insulating film (130). The upper surface of the rear insulating film (130) and the exposed upper surfaces of the second through-electrodes (150b) may be positioned on the same plane.

Thereafter, a photoresist film may be formed on the second surface (114) of the second semiconductor substrate (110b), and an exposure process may be performed on the photoresist film to form a photoresist pattern having openings exposing the second through-hole electrodes (150b), and then a plating process may be performed on the openings to form rear bonding pads (144). Thereafter, a conductive material may be filled on the rear bonding pads (144) in the openings to form a conductive member (212). The conductive member may have a shape corresponding to the planar shape of the rear bonding pads (144). Since the rear bonding pads (144) and the first bumps (210) may be formed together through a single photoresist process without the need to form protrusions on the rear bonding pads (144) through a separate photoresist process, the efficiency and speed of the process may be increased.

Referring to FIGS. 9 and 10, after removing the photoresist pattern, a reflow process can be performed on the conductive member (212) to form a first bump (210).

The conductive member (212) is melted at a high temperature during the reflow process, and the shape of the melted conductive member (212) changes so that the area in contact with the outside is the smallest due to the surface tension of the melted conductive member (212), and as the temperature decreases, it solidifies in the changed shape to form a first bump (210). The first bump (210) may have a dome shape or a hemispherical shape with a curved surface that increases in height toward the center.

Referring to FIG. 11, an adhesive material (302) is applied on the front insulating film (120) of the second wafer (W2), and the second wafer (W2) is cut along the scribe lane area (SA) to form individual second semiconductor chips (core dies) (110b).

An adhesive member (302) may be provided to fill the space between the second bumps (220) on the second semiconductor chip (100b). The adhesive member (302) may include a non-conductive adhesive. For example, the adhesive member (302) may include a non-conductive film (NCF).

Referring to FIGS. 12 to 15, second semiconductor chips (100b) can be stacked on a first wafer (W1). The second semiconductor chip (100b) can be stacked on the first wafer (W1) via a first bump (210) and a second bump (220).

In exemplary embodiments, a first wafer (W1) may include a first semiconductor substrate (110a) having a first surface (112) and a second surface (114) opposite the first surface (112). The first wafer (W1) may include a die area (DA) and a scribe lane area (SA) surrounding the die area (DA). The first wafer (W1) may be subsequently cut along the scribe lane area (SA) that separates a plurality of die areas (DA) of the first wafer (W1) by a sawing process to thereby individualize the plurality of first semiconductor chips.

Circuit elements may be formed in a die area (DA) on a first surface (112) of a first semiconductor substrate (110a). The first semiconductor chip may be a logic chip including a logic circuit. The logic chip may be a controller that controls memory elements of the second semiconductor chip. The first semiconductor chip may be a processor chip such as an ASIC or an AP (Application Processor) as a host such as a CPU, GPU, or SOC.

The circuit elements may include, for example, transistors, capacitors, wiring structures, etc. The circuit elements may be formed by performing a fab process called a front end of line (FEOL) process for manufacturing semiconductor elements on a first surface (112) of a first semiconductor substrate (110a). The surface of the first substrate on which the FEOL process is performed may be referred to as the front side surface of the first substrate, and the opposite surface of the front side may be referred to as the backside surface. An interlayer insulating film covering the circuit elements may be formed on the first surface (112) of the first semiconductor substrate (110a).

A first wafer (W) may include a front insulating film (120) provided on a first surface (112) of a first semiconductor substrate (110a), front bonding pads (142) provided on the front insulating film (120), first through-electrodes (150a) penetrating the first semiconductor substrate (110a), and back bonding pads (144) provided on a second surface (114) of the first semiconductor substrate (110a). The front bonding pads (142) may be electrically connected to the back bonding pads (144) by the first through-electrodes (150a).

A photoresist film may be formed on a second surface (114) of a first semiconductor substrate (110a), and an exposure process may be performed on the photoresist film to form a photoresist pattern having openings exposing the first through-hole electrodes (150a), and then a plating process may be performed on the openings to form rear bonding pads (144). Thereafter, a conductive material may be filled on the rear bonding pads (144) within the openings to form a conductive member (212). The conductive member may have a shape corresponding to the planar shape of the rear bonding pads (144). Thereafter, after the photoresist pattern is removed, a reflow process may be performed on the conductive member (212). The conductive member (212) is melted at a high temperature during the reflow process, and the shape of the melted conductive member (212) changes so that the area in contact with the outside is the smallest due to the surface tension of the melted conductive member (212), and as the temperature decreases, it solidifies in the changed shape to form a first bump (210). The first bump (210) may have a dome shape or a hemispherical shape with a curved surface that increases in height toward the center.

As illustrated in FIG. 12, a second semiconductor chip (100b) can be stacked on a first wafer (W1) using a substrate support system (WSS). The second semiconductor chips (100b) can be placed on the first wafer (W1) so as to correspond to respective die areas (DA).

As illustrated in FIG. 13, the first bumps (210) of the first semiconductor substrate (110a) may be positioned to correspond to the second bumps (220) of the second semiconductor substrate (110b). At this time, the adhesive member (302) covering the second bumps (220) on the first surface (112) of the second semiconductor substrate (110b) may have different thicknesses depending on the positions of the second bumps (220). The height (H1) of the first bump (210) may be 5 μm or less. The ratio of the width (D1) of the rear bonding pad to the height (H1) of the first bump (210) may be 25 or less. The first bump (210) may have a shape in which the central portion protrudes the highest, so that when performing a thermocompression (TC) process, stress is concentrated in the central portion to provide penetration force to the second bump (220). The height (H2) of the second bump (220) may be within a range of 15 μm to 50 μm, but is not limited thereto.

As illustrated in FIGS. 14 and 15, since a predetermined temperature is applied to the second semiconductor chip (100b) during the thermal compression process, the second bump (220) may be partially melted, and the adhesive member (302) may be liquefied to have fluidity and may flow between the second semiconductor chip (100b) and the first wafer (W1). Since the first bump (210) may have a shape in which the height increases toward the center, when the stress is concentrated at the center of the first bump (210), a penetrating force may be applied to the adhesive member (302) and the second bump (220) when the thermal compression process is performed. The first bump (210) may penetrate the adhesive member (302) covering the second bump (220) and apply force to the second bump (220), thereby deforming the shape of the second bump (220). The second bump (220) is deformed into a covering shape to cover the upper surface of the first bump (210), and is hardened in the deformed shape so that the first bump and the second bump can form a conductive bump structure (200). Accordingly, as illustrated in FIG. 13, the first bump (210) and the second bump (220) can be joined by providing penetration force regardless of whether the adhesive member (302) has different thicknesses depending on the location.

The first bump (210) may include a material similar to that of the second bump (220), that is, an alloy material including tin (Sn), and thus may have good wettability with the second bump (220). Accordingly, the first bump (210) may have a surface that penetrates the adhesive layer (300) and makes contact with the second bump (220), and when the thermal compression process is performed, the first bump (210) may also be partially melted, so that the partially melted material of the first bump (210) may penetrate the second bump (220) and form a conductive bump structure (200) by combining them to have a region where they are partially mixed. Through the conductive bump structure, the front bonding pad (142) of the second semiconductor chip (100b) and the back bonding pad (144) on the first wafer (W1) may be electrically connected.

The adhesive material having fluidity can flow between the conductive bump structures (200) and then be cured to form an adhesive layer (300) that fills the space between the conductive bump structures (200). A portion of the adhesive layer (300) can protrude from the side surface of the second semiconductor chip (100b).

Referring to FIG. 16, third to fifth semiconductor chips (100e) can be stacked on the second semiconductor chip (100b).

First, individualized third to fifth semiconductor chips (100c, 100d, 100e) may be formed by performing processes identical or similar to those described with reference to FIGS. 4 to 11, and the third to fifth semiconductor chips (100c, 100d, 100e) may be stacked on the second semiconductor chip (100b) by performing processes identical or similar to those described with reference to FIGS. 12 to 15.

In exemplary embodiments, the third semiconductor chip (100c) may include a front insulating film (120) provided on a first surface (112) of a third semiconductor substrate (110c), front bonding pads (142) provided on the front insulating film (120), third through-electrodes (150c) penetrating the third semiconductor substrate (110c), and back bonding pads (144) provided on a second surface (114) of the third semiconductor substrate (110c). In addition, the third semiconductor chip (100c) may include a second bump (220) formed on the front bonding pad (142) and an adhesive member (302) applied to cover the second bump (220).

A photoresist film may be formed on a second surface (114) of a third semiconductor substrate (110c), and an exposure process may be performed on the photoresist film to form a photoresist pattern having openings exposing third through-hole electrodes (150c), and then a plating process may be performed on the openings to form rear bonding pads (144). A conductive material may be filled on the rear bonding pads (144) within the openings to form a conductive member (212). The conductive member may have a shape corresponding to the planar shape of the rear bonding pads (144). Thereafter, after removing the photoresist pattern, a reflow process may be performed on the conductive member (212). The conductive member (212) is melted at a high temperature during the reflow process, and the shape of the melted conductive member (212) changes so that the area in contact with the outside is the smallest due to the surface tension of the melted conductive member (212), and as the temperature decreases, it solidifies in the changed shape to form a first bump (210). The first bump (210) may have a dome shape or a hemispherical shape with a curved surface that increases in height toward the center.

The third semiconductor chip (100c) can be stacked on the second semiconductor chip (100b) via conductive bump structures (200). The third semiconductor chip (100c) can be attached to the second semiconductor chip (100b) by performing a thermal compression process at a predetermined temperature (e.g., about 400°C or less). Through this thermal compression process, the third semiconductor chip (100c) and the second semiconductor chip (100b) can be bonded to each other.

During the above thermal compression process, since a predetermined temperature is applied to the third semiconductor chip (100c), the second bump (220) on the third semiconductor substrate (110c) may be partially melted, and the adhesive member (302) may be liquefied to have fluidity and may flow between the third semiconductor chip (100c) and the second semiconductor chip (100b). Since the first bump (210) on the second semiconductor substrate (110b) may have a shape in which the height increases toward the center, when the above thermal compression process is performed, a penetrating force may be applied to the adhesive member (302) and the second bump (220). The first bump (210) may penetrate the adhesive member (302) covering the second bump (220) and apply force to the second bump (220), thereby deforming the shape of the second bump (220). The second bump (220) is deformed into a covering shape to cover the upper surface of the first bump (210), and is hardened in the deformed shape so that the first bump and the second bump can form a conductive bump structure (200).

The first bump (210) may include a material similar to that of the second bump (220), that is, an alloy material including tin (Sn), and thus may have good wettability with the second bump (220). Accordingly, the first bump (210) may have a surface that penetrates the adhesive layer (300) and makes contact with the second bump (220), and when the thermal compression process is performed, the first bump (210) may also be partially melted, so that the partially melted material of the first bump (210) may penetrate the second bump (220) and be combined to have a region where it is partially mixed, thereby forming a conductive bump structure (200). Through the conductive bump structure, the front bonding pad (142) of the third semiconductor chip (100c) and the back bonding pad (144) of the second semiconductor chip (100b) may be electrically connected.

The adhesive material having fluidity can flow between the conductive bump structures (200) and then be cured to form an adhesive layer (300) that fills the space between the conductive bump structures (200). A portion of the adhesive layer (300) can protrude from the side surface of the second semiconductor chip (100b).

In exemplary embodiments, the fourth semiconductor chip (100d) may include a front insulating film (120) provided on a first surface (112) of a fourth semiconductor substrate (110d), front bonding pads (142) provided on the front insulating film (120), fourth through-electrodes (150d) penetrating the fourth semiconductor substrate (110d), and back bonding pads (144) provided on a second surface (114) of the fourth semiconductor substrate (110d). In addition, the fourth semiconductor chip (100d) may include a second bump (220) formed on the front bonding pad (142) and an adhesive member (302) applied to cover the second bump (220).

A photoresist film may be formed on a second surface (114) of a fourth semiconductor substrate (110d), and an exposure process may be performed on the photoresist film to form a photoresist pattern having openings exposing the fourth through-hole electrodes (150d), and then a plating process may be performed on the openings to form rear bonding pads (144). A conductive material may be filled on the rear bonding pads (144) within the openings to form a conductive member (212). The conductive member may have a shape corresponding to the planar shape of the rear bonding pads (144). Thereafter, after removing the photoresist pattern, a reflow process may be performed on the conductive member (212). The conductive member (212) is melted at a high temperature during the reflow process, and the shape of the melted conductive member (212) changes so that the area in contact with the outside is the smallest due to the surface tension of the melted conductive member (212), and as the temperature decreases, it solidifies in the changed shape to form a first bump (210). The first bump (210) may have a dome shape or a hemispherical shape with a curved surface that increases in height toward the center.

The fourth semiconductor chip (100d) can be stacked on the third semiconductor chip (100c) via conductive bump structures (200). The fourth semiconductor chip (100d) can be attached to the third semiconductor chip (100c) by performing a thermal compression process at a predetermined temperature (e.g., about 400°C or less). Through this thermal compression process, the fourth semiconductor chip (100d) and the third semiconductor chip (100c) can be bonded to each other.

During the above thermal compression process, since a predetermined temperature is applied to the fourth semiconductor chip (100d), the second bump (220) on the fourth semiconductor substrate (110d) may be partially melted, and the adhesive member (302) may be liquefied to have fluidity and may flow between the fourth semiconductor chip (100d) and the third semiconductor chip (100c). Since the first bump (210) on the third semiconductor substrate (110c) may have a shape in which the height increases toward the center, when the thermal compression process is performed, a penetrating force may be applied to the adhesive member (302) and the second bump (220). The first bump (210) may penetrate the adhesive member (302) covering the second bump (220) and apply force to the second bump (220), thereby deforming the shape of the second bump (220). The second bump (220) is deformed into a covering shape to cover the upper surface of the first bump (210), and is hardened in the deformed shape so that the first bump and the second bump can form a conductive bump structure (200).

The first bump (210) may include a material similar to that of the second bump (220), that is, an alloy material including tin (Sn), and thus may have good wettability with the second bump (220). Accordingly, the first bump (210) may have a surface that penetrates the adhesive layer (300) and makes contact with the second bump (220), and when the thermal compression process is performed, the first bump (210) may also be partially melted, so that the partially melted material of the first bump (210) may penetrate the second bump (220) and be combined to have a region where it is partially mixed, thereby forming a conductive bump structure (200). Through the conductive bump structure, the front bonding pad (142) of the fourth semiconductor chip (100d) and the back bonding pad (144) of the third semiconductor chip (100c) may be electrically connected.

The adhesive material having fluidity can flow between the conductive bump structures (200) and then be cured to form an adhesive layer (300) that fills the space between the conductive bump structures (200). A portion of the adhesive layer (300) can protrude from the side of the third semiconductor chip (100c).

In exemplary embodiments, the fifth semiconductor chip (100e) may include a front insulating film (120) provided on a first surface (112) of a fifth semiconductor substrate (110e), front bonding pads (142) provided on the front insulating film (120), a second bump (220) formed on the front bonding pad (142), and an adhesive member (302) applied to cover the second bump (220).

The fifth semiconductor chip (100e) can be stacked on the fourth semiconductor chip (100d) via conductive bump structures (200). The fifth semiconductor chip (100e) can be attached to the fourth semiconductor chip (100d) by performing a thermal compression process at a predetermined temperature (e.g., about 400°C or less). The fifth semiconductor chip (100e) and the fourth semiconductor chip (100d) can be bonded to each other by this thermal compression process.

During the above thermal compression process, since a predetermined temperature is applied to the fourth semiconductor chip (100d), the second bump (220) on the fifth semiconductor substrate (110d) may be partially melted, and the adhesive member (302) may be liquefied to have fluidity and may flow between the fifth semiconductor chip (100e) and the fourth semiconductor chip (100d). Since the first bump (210) on the fourth semiconductor substrate (110d) may have a shape in which the height increases toward the center, when the above thermal compression process is performed, a penetrating force may be applied to the adhesive member (302) and the second bump (220). The first bump (210) may penetrate the adhesive member (302) covering the second bump (220) and apply force to the second bump (220), thereby deforming the shape of the second bump (220). The second bump (220) is deformed into a covering shape to cover the upper surface of the first bump (210), and is hardened in the deformed shape so that the first bump and the second bump can form a conductive bump structure (200).

The first bump (210) may include a material similar to that of the second bump (220), that is, an alloy material including tin (Sn), and thus may have good wettability with the second bump (220). Accordingly, the first bump (210) may have a surface that penetrates the adhesive layer (300) and makes contact with the second bump (220), and when the thermal compression process is performed, the first bump (210) may also be partially melted, so that the partially melted material of the first bump (210) may penetrate the second bump (220) and be combined to have a region where they are partially mixed, thereby forming a conductive bump structure (200). Through the conductive bump structure, the front bonding pad (142) of the fifth semiconductor chip (100e) and the back bonding pad (144) of the fourth semiconductor chip (100d) may be electrically connected.

The adhesive material having fluidity can flow between the conductive bump structures (200) and then be cured to form an adhesive layer (300) that fills the space between the conductive bump structures (200). A portion of the adhesive layer (300) can protrude from the side of the fourth semiconductor chip (100d).

Referring to FIG. 17, a molding member (400) covering the side surfaces of the second to fifth semiconductor chips (100b, 100c, 100d, 100e) is formed on a first wafer (W1), and conductive bumps (500) are formed on the front bonding pads (142) of the first semiconductor chip (100a), and then the first wafer (W1) is cut along the scribe lane area (SA) to form the first semiconductor chip (100a), and the molding member (400) is also cut together to complete the semiconductor package (10) of FIG. 1.

In exemplary embodiments, the molding member (400) may be formed to fill the gaps between the first to fifth semiconductor chips (100a, 100b, 100c, 100d, 100e). The molding member (400) may expose an upper surface of the fifth semiconductor chip (100e). The molding member (400) may be formed using a polymer material such as an epoxy molding compound (EMC).

The semiconductor package described above may include semiconductor devices such as logic devices or memory devices. The semiconductor package may include logic devices such as a central processing unit (CPU, MPU), an application processor (AP), etc., volatile memory devices such as an SRAM device, a DRAM device, etc., and nonvolatile memory devices such as a flash memory device, a PRAM device, an MRAM device, an RRAM device, etc.

Although the present invention has been described above with reference to embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

10: Semiconductor package 100: Semiconductor chip
110: Semiconductor substrate 112: First side
114: Second side 120: Front insulation film
122: Metal wiring layer 123: Wires
124: Passivation film 130: Back insulation film
142: Front bonding pad 144: Rear bonding pad
150: Penetrating electrode 200: Conductive bump structure
210: First bump 212: Conductive member
220: Second bump 300: Adhesive layer
302: Adhesive member 400: Molding member
500: Challenge Bump

Claims (10)

A first semiconductor chip having rear bonding pads on the rear side;
A second semiconductor chip disposed on the first semiconductor chip and having front bonding pads on the front surface; and
It includes conductive bump structures disposed between the first semiconductor chip and the second semiconductor chip and connecting the rear bonding pads and the front bonding pads, respectively.
Each of the above-mentioned challenging bump structures,
A first bump disposed on the rear bonding pad, having a planar shape corresponding to the shape of the upper surface of the rear bonding pads, and having a hemispherical shape with a height increasing toward the center; and
A semiconductor package comprising a second bump bonded to the first bump. A semiconductor package according to claim 1, wherein the second bump comprises a solder bump. A semiconductor package in accordance with claim 1, wherein the first bump comprises a material having higher mechanical strength than the second bump. A semiconductor package in claim 1, wherein the first bump comprises at least one of a Sn-Sb alloy, a Sn-Mg alloy, a Sn-Zn alloy, and a Sn-Bi alloy. A semiconductor package in accordance with claim 1, wherein the first bump comprises a material having a higher melting point than the second bump. A semiconductor package according to claim 1, wherein the melting point of the first bump is between 200°C and 240°C. A semiconductor package in accordance with claim 1, wherein the height of the highest point of the first bump is 5 μm or less. A semiconductor package in accordance with claim 1, wherein the ratio of the width of the rear bonding pad to the height of the first bump is 25 or less. In the first paragraph,
A semiconductor package further comprising an adhesive layer provided between the second semiconductor chip and the first semiconductor chip and covering side surfaces of the conductive bump structures. First to fourth semiconductor chips sequentially stacked via conductive bump structures; and
Including adhesive layers for filling the space between the conductive bump structures between the first to fourth semiconductor chips and attaching the first to fourth semiconductor chips,
Each of the first to fourth semiconductor chips has front bonding pads on the front surface,
Each of the first to third semiconductor chips has rear bonding pads on the rear side,
Each of the above-mentioned challenging bump structures,
A first bump disposed on the rear bonding pad, having a planar shape corresponding to the shape of the upper surface of the rear bonding pad, and having a hemispherical shape with a height increasing toward the center; and
A semiconductor package comprising a second bump bonded to the first bump.