KR20250128799A - 3-dimensional integrated circuit including protection circuit - Google Patents

Abstract

A three-dimensional integrated circuit according to an embodiment of the present disclosure includes a first integrated circuit including a first substrate, a second integrated circuit stacked on the first integrated circuit, a through via penetrating the first substrate and electrically connecting the first integrated circuit and the second integrated circuit, and a plurality of protection circuits positioned on both sides of the through via within a keep out zone surrounding the through via and electrically connected to the through via.

Description

3-Dimensional Integrated Circuit Including Protection Circuit

The present disclosure relates to a three-dimensional integrated circuit including a protection circuit.

As electronic devices, such as portable electronic devices, become smaller, the semiconductor devices they incorporate are also becoming increasingly smaller and lighter. To accommodate this miniaturization, three-dimensional integrated circuits (3D integrated circuits) are being manufactured, consisting of multiple stacked chips, to accommodate more circuits in a limited space.

Meanwhile, processes involving charged ions, such as plasma etching, are commonly used in the manufacturing of integrated circuits. For example, during the manufacturing of an integrated circuit, the lowest metal layer closest to the substrate may be connected to the gate poly of a metal-oxide semiconductor (MOS) transistor. During the plasma etching process step of forming or interconnecting the metal layer, etc., the lowest metal layer may absorb charges from the plasma, thereby forming a sufficiently high voltage relative to the substrate, which may destroy the thin gate dielectric separating the gate poly from the substrate. This is called plasma-induced gate oxide damage or the antenna effect. This can cause yield and reliability issues for the integrated circuit.

One embodiment of the present disclosure is directed to providing a three-dimensional integrated circuit having at least one protection circuit disposed in a keep out zone (KoZ).

One embodiment of the present disclosure seeks to provide a three-dimensional integrated circuit that reduces spatial overhead.

A three-dimensional integrated circuit according to one embodiment may include a first integrated circuit including a first substrate, a second integrated circuit stacked on the first integrated circuit, a through via penetrating the first substrate and electrically connecting the first integrated circuit and the second integrated circuit, and a plurality of protection circuits positioned on both sides of the through via within a keep out zone surrounding the through via and electrically connected to the through via.

In one embodiment, an integrated circuit may include a through via penetrating a first substrate, a first keep-out zone positioned on the first substrate and including a first boundary spaced apart from the through via in a first direction by a first distance around the through via and a second boundary spaced apart from the through via in a second direction perpendicular to the first direction by a second distance, a second keep-out zone positioned on the first substrate and including a third boundary spaced apart from the through via in the first direction by a third distance, and a fourth boundary spaced apart from the through via in the second direction by the second distance, a first protection circuit positioned outside the first keep-out zone and inside the second keep-out zone and electrically connected to the through via, and an interface circuit positioned outside the second keep-out zone and electrically connected to the through via.

According to one embodiment, a three-dimensional integrated circuit may include a first substrate, a through via penetrating the first substrate, a first keep-out zone located on the first substrate and being an area extending a first distance from the through via around the through via, a second keep-out zone located on the first substrate and being an area extending a second distance from the first keep-out zone in a first direction and a direction opposite to the first direction, a protection circuit located outside the first keep-out zone and inside the second keep-out zone and being electrically connected to the through via, and an interface circuit adjacent to the first keep-out zone in a second direction perpendicular to the first direction and being electrically connected to the through via.

FIG. 1 is a diagram illustrating a three-dimensional integrated circuit according to one embodiment including a through via.
Figure 2 is a drawing for explaining a TSV cell and a protection circuit according to a comparative example.
FIG. 3 is a drawing for explaining a TSV cell according to one embodiment.
FIG. 4 is a drawing for explaining a TSV cell according to one embodiment.
Figure 5 is a cross-sectional view taken along line A-A' of Figure 4.
FIG. 6 is a drawing for explaining a TSV cell according to one embodiment.
Fig. 7 is a perspective view showing a cross-section taken along line B-B' of Fig. 6.
FIG. 8 is a drawing for explaining the effect of reducing the area occupied by a protection circuit according to one embodiment.
Figure 9 is a schematic diagram showing the layout of an integrated circuit.
Figure 10 is a drawing showing a TSV area according to a comparative example.
FIG. 11 is a drawing showing a TSV region according to one embodiment.
FIG. 12 is a diagram for explaining a signal transmission path of a logic signal according to one embodiment.
Fig. 13 is a drawing showing a semiconductor device according to an embodiment.

Below, with reference to the attached drawings, embodiments of the present invention are described in detail so that those skilled in the art can easily implement them. However, the present invention may be implemented in various different forms and is not limited to the embodiments described herein.

It should be understood that the embodiments described herein are intended to implement various features of the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the dimensions of the components are not limited to the disclosed ranges or values and may vary depending on process conditions and/or desired device properties. Furthermore, the formation of the first structure on or above the second structure in the following description may include embodiments in which the first and second structures are formed in direct contact, and may also include embodiments in which additional structures may be formed between the first and second structures so that the first and second structures do not directly contact each other. For simplicity and clarity, the various structures may be arbitrarily drawn at different scales.

Additionally, spatially related terms, such as "below," "lower," "lower," "above," "upper," etc., may be used for ease of explanation to describe the relationship of one element or structure to another element or structure illustrated in the drawings.

And in order to clearly explain the present invention in the drawings, parts that are not related to the description are omitted, and similar parts are given similar drawing reference numerals throughout the specification.

Additionally, expressions described in the singular may be interpreted as either singular or plural, unless explicitly stated as "one" or "single." Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the components are not limited by these terms. These terms may be used to distinguish one component from another.

FIG. 1 is a diagram illustrating a three-dimensional integrated circuit according to one embodiment including a through via. In one embodiment, the through via may be, but is not limited to, a through silicon via (TSV).

Referring to FIG. 1, a three-dimensional integrated circuit (3D IC) (100) may include integrated circuits (110, 130, 150) and a printed circuit board (PCB, 170). Each of the integrated circuits (110, 130, 150) of the three-dimensional integrated circuit (100) may be connected by through vias (120). Each of the integrated circuits (110, 130, 150) may transmit and receive a logic signal or a power voltage through the through vias (120).

In one embodiment, at least one through-via (120) may constitute a unit through-via structure (123). The unit through-via structure (123) may include a plurality of through-vias (121). The plurality of through-vias (121) may be arranged regularly. For example, each of the integrated circuits (110, 130, 150) may transmit and receive a logic signal or a power voltage through the unit through-via structure (123). The through-via (121) hereinafter may refer to any of the plurality of through-vias included in the unit through-via structure (123).

Although not shown in FIG. 1, bumps (e.g., micro bumps or solder bumps) or hybrid copper bonding (HCB) may be positioned between the integrated circuits (110, 130, 150). The integrated circuits (110, 130, 150) may be electrically connected through the bumps or hybrid copper bonding, etc. positioned between the integrated circuits (110, 130, 150). The integrated circuits (110, 130, 150) may transmit and receive logic signals or power voltages through the bumps or hybrid copper bonding, etc. positioned between the integrated circuits (110, 130, 150).

The first integrated circuit (150) may include a region (i.e., a keep-out zone (KoZ)) (160) in which a circuit is selectively placed to prevent defects due to the formation of a through-via (121). That is, by setting a keep-out zone (160) spaced apart from the through-via (121) by a predetermined distance in order to prevent the carrier mobility of active silicon existing near the through-via (121) from being reduced, a circuit or metal layer may not be placed within the keep-out zone (160). The keep-out zone (160) may include a keep-out zone in a front-end-of-line (FEOL) process and a keep-out zone in a back-end-of-line (BEOL) process. A specific description thereof will be described later with reference to FIG. 2. Hereinafter, the keep-out zone (160) including the through-via (121) may be referred to as a TSV cell.

In one embodiment, the TSV cell may include a protection circuit (161). The protection circuit (161) may be located in a keep-out zone (160). The protection circuit (161) may protect the integrated circuit from electrical effects occurring during the manufacturing process of the integrated circuit, etc. For example, the protection circuit (161) may protect the first integrated circuit (150) by preventing an antenna effect or electrostatic discharge (ESD). Hereinafter, the protection circuit (161) is illustrated and described as including a plurality of diodes, but the configuration of the protection circuit (161) is not limited thereto.

An integrated circuit includes a transistor, and a gate electrode of the transistor may include a first layer and a second layer. Here, the first layer may include a metal, and the second layer may include a polysilicon layer. Hereinafter, the second layer is described as a polysilicon layer of the gate electrode of the transistor.

In a three-dimensional integrated circuit (100), the antenna effect may be caused by damage to the gate poly due to charges generated during the etching step of the through-via (121). For example, the gate poly of a MOS transistor on a first integrated circuit (150) may be connected to the through-via (121) through a metal layer. During the manufacturing process of the integrated circuit, charges generated by the plasma etching process may accumulate on the floating gate poly on the first integrated circuit (150), thereby destroying the gate dielectric. To prevent this, the three-dimensional integrated circuit (100) may include a protection circuit (161) located in the TSV cell.

In one embodiment, the protection circuit (161) may include a first diode (D1) connected between a node (N) and a first power supply (VDD1) line, and a second diode (D2) connected between the node (N) and a ground power supply (VSS) line. The first diode (D1) and the second diode (D2) may be connected in reverse directions. The anode of the first diode (D1) may be connected to the node (N), and the cathode of the first diode (D1) may be connected to the first power supply (VDD1) having a higher voltage level than the node (N). The cathode of the second diode (D2) may be connected to the node (N), and the cathode of the second diode (D2) may be connected to the ground power supply (VSS) having a lower voltage level than the node (N). When a voltage having a signal level within a normal operating range is applied to the node (N), each diode (D1, D2) is reverse biased and therefore does not conduct. However, when a high voltage is applied to the node (N), the diodes (D1, D2) are turned on due to the strong reverse bias, and the charge due to static electricity can be discharged immediately to the first power supply (VDD1) line or the ground power supply (VSS) line. That is, the protection circuit (161) can create another electrical path for discharging the charge. However, the structure of the protection circuit (161) is merely exemplary and is not limited thereto.

According to one embodiment, since the protection circuit (161) is located in the keep-out zone (161), the area occupied by the protection circuit (161) in the first integrated circuit (150) can be reduced, and thus the area of the first integrated circuit (150) can be efficiently utilized.

Figure 2 is a drawing for explaining a TSV cell and a protection circuit according to a comparative example.

Referring to FIG. 2, a TSV cell (20) may include a through via (24). At least one through via (24) may be positioned. At least one through via (24) may constitute a unit through via structure (22). The unit through via structure (22) may include a plurality of through vias (24) that are regularly arranged. A boundary (21) of a first keep out zone (KoZ 1) and a boundary (23) of a second keep out zone (KoZ 2) may be determined by a distance from an edge of an outermost through via of the unit through via structure (22). For example, a boundary in a first direction (e.g., X direction) of a first keep out zone (KoZ 1) may be spaced apart from an outermost through-via in the first direction by a first distance (d1), and a boundary in a second direction (e.g., Y direction) of the first keep out zone (KoZ 1) may be spaced apart from an outermost through-via in the second direction by a second distance (d2). The first direction and the second direction may be perpendicular, and the first distance (d1) and the second distance (d2) may be the same as or different from each other. A boundary in a first direction (X direction) of a second keep out zone (KoZ 2) may be spaced apart from an outermost through-via in the first direction by a third distance (d3), and a boundary in a second direction (Y direction) of the second keep out zone (KoZ 2) may be spaced apart from an outermost through-via in the second direction by a second distance (d2). The first distance (d1) and the third distance (d3) may be different from each other, and the third distance (d3) may be greater than the first distance (d1). The boundary (23) of the second keep out zone (KoZ 2) may be expanded in the first direction (X direction) and in the opposite direction to the first direction from the boundary (21) of the first keep out zone (KoZ 1). The second keep out zone (KoZ 2) may be an area expanded in the first direction from the first keep out zone (KoZ 1). The first keep out zone (KoZ 1) may have a smaller area than the second keep out zone (KoZ 2). That is, the second keep out zone (KoZ 2) may occupy a larger area than the first keep out zone (KoZ 1).

The second keep-out zone (KoZ 2) may be an area where active semiconductor devices (i.e., transistors used to transmit/process signals) formed during the FEOL process are not placed. In the FEOL process, various layers and patterns required for the function of the active semiconductor devices can be formed. The second keep-out zone (KoZ 2) may be an area where active semiconductor devices are not placed to prevent interference between the through via (24) and the active semiconductor devices.

The first keep-out zone (KoZ 1) may be an area where no metal layers, vias, etc. formed during the BEOL process are placed. In the BEOL process, metal layers, etc. for connecting active semiconductor devices and other components may be formed. The first keep-out zone (KoZ 1) may be an area where no metal layers are placed except for predefined metal layers (e.g., metal layers connected to silicon through vias) to prevent interference between through vias (24) and metal layers.

The through via (24) of the TSV cell (20) can transmit a logic signal received from an adjacently arranged interface circuit (23) to another integrated circuit, or transmit a logic signal received from another integrated circuit to the interface circuit (23). The through via (24) and the interface circuit (23) can be connected through a plurality of metal layers (26). Here, the interface circuit (23) can include various logic elements. For example, the interface circuit (23) can be various logic elements such as an AND gate, an OR gate, a NOR gate, an XOR gate, an inverter, etc., or a memory element such as a latch, a flip-flop, etc.

The protection circuit (25) may be arranged on the path between the through via (24) and the interface circuit (23). That is, the protection circuit (25) may be connected to the metal layer (26) connecting the through via (24) and the interface circuit (23). The protection circuit (25) according to the comparative example may be arranged outside the TSV cell (20). The protection circuit (25) according to the comparative example may be arranged adjacent to the TSV cell (20) outside the TSV cell (20). The protection circuit (25) according to the comparative example may be located between the interface circuit (23) and the TSV cell (20) outside the TSV cell (20).

According to a comparative example, the protection circuit (25) placed outside the TSV cell (20) occupies a large area within the integrated circuit. That is, there is a problem in that the area of the integrated circuit cannot be efficiently utilized due to the protection circuit (25) placed outside the TSV cell (20).

FIG. 3 is a diagram illustrating a TSV cell according to one embodiment. Specifically, it is a schematic layout diagram illustrating a TSV cell including a protection circuit.

In one embodiment, the TSV cell (30) may include a protection circuit (35). Specifically, the protection circuit (35) may be disposed within a second keep out zone (KoZ 2) of the TSV cell (30). Since the protection circuit (35) includes a passive semiconductor device (i.e., a transistor that is not used to transmit/process a signal), it may be disposed within the second keep out zone (KoZ 2) (i.e., within the TSV cell boundary (31)). On the other hand, since unexpected damage to the protection circuit (35) may occur during the manufacturing process if the protection circuit (35) is disposed too close to the through via (34), the protection circuit (35) may be disposed outside the first keep out zone (KoZ 1). The protection circuit (35) may be an antenna protection circuit (e.g., antenna diode, etc.) to prevent the antenna effect, or an ESD protection circuit (e.g., ESD diode, clamp, etc.) to prevent ESD, but is not limited thereto.

In one embodiment, the TSV cell (30) and the interface circuit (33) may be arranged adjacent to each other in a first direction (X direction). The through via (34) of the TSV cell (30) may transmit a logic signal received from the adjacently arranged interface circuit (33) to another integrated circuit, or may transmit a logic signal received from another integrated circuit to the interface circuit (33). The through via (34) and the interface circuit (33) may be connected through a plurality of metal layers (36).

In one embodiment, a protection circuit (35) within a TSV cell (30) may be placed on a path between an interface circuit (33) and a through-via (34). That is, the protection circuit (35) may be connected to a plurality of metal layers (36) connecting the interface circuit (33) and the through-via (34). The protection circuit (35) may serve as an electrical path for discharging charges flowing toward the interface circuit (33) and may protect transistors within the interface circuit (33) from various electrical effects.

According to one embodiment, by placing the protection circuit (25) within the TSV cell (20), the area of the integrated circuit can be efficiently utilized. For example, there is an advantage in that the size of the integrated circuit can be reduced or a sufficient area can be secured on the integrated circuit in which logic elements can be placed.

FIG. 4 is a diagram illustrating a TSV cell according to one embodiment. Specifically, it is a schematic layout diagram illustrating a TSV cell including a plurality of protection circuits.

In one embodiment, the TSV cell (40) may include protection circuits (45, 47). A second keep out zone (KoZ 2) of the TSV cell (40) may include a first region (44) extending in a first direction (e.g., X direction) from the first keep out zone (KoZ 1) and a second region (42) extending in a direction opposite to the first direction. The TSV cell (40) may include a protection circuit (47) positioned in the first region (44) and a protection circuit (45) positioned in the second region (42). The protection circuits (45, 47) may be positioned in the second keep out zone (KoZ 2) on both sides of the through via (48). The protection circuits (45, 47) may be positioned outside the first keep out zone (KoZ 1) on both sides of the through via (48). The structures of the protection circuits (45, 47) may be the same or different.

In one embodiment, the protection circuits (45, 47) may be arranged on a path between the interface circuit (43) and the through via (48). That is, the protection circuits (45, 47) may be connected to a metal layer (46) connecting the interface circuit (43) and the through via (48). The protection circuits (45, 47) may serve as an electrical path for discharging charges flowing toward the interface circuit (43), and may protect the transistors within the interface circuit (43) from various electrical effects. The TSV cell (40) according to one embodiment may further enhance the protection effect on the transistors around the TSV cell through the protection circuits without increasing the area occupied by the protection circuits in the integrated circuit by including a plurality of protection circuits.

Figure 5 is a cross-sectional view taken along line A-A' of Figure 4.

Specifically, FIG. 5 is a cross-sectional view of one integrated circuit (500) among a plurality of integrated circuits constituting a three-dimensional integrated circuit. Referring to FIG. 5 , the three-dimensional integrated circuit according to one embodiment may further include additional integrated circuits above and/or below the integrated circuit (500). For example, the integrated circuit (500) may correspond to the first integrated circuit (150) according to FIG. 1 . Furthermore, although a portion of the integrated circuit (500) is illustrated herein, the integrated circuit (500) may include more configurations.

In one embodiment, the integrated circuit (500) may include a BEOL layer (510a) and a substrate layer (510c). The substrate layer (510c) may be or include a semiconductor substrate material, such as silicon. An interface circuit (520) may be disposed on and/or within the substrate layer (510c) for transmitting and receiving logic signals with other adjacent dies. The interface circuit (520) may be an active device, such as a MOS transistor. The substrate layer (510c) may include a through via (531) extending through the substrate layer (510c). The through via (531) may extend from a front surface (510f) of the substrate layer (510c) to a back surface (510b).

In one embodiment, a boundary of a first keep out zone (KoZ 1) in a first direction (X direction) around the through via (531) may be determined by a first distance (533) from the through via (531) on the substrate layer (510c). A boundary of a second keep out zone (KoZ 2) in the first direction (X direction) around the through via (531) may be determined by a second distance (535) from the through via (531). As described above with reference to FIG. 2, the first keep out zone (KoZ 1) may be an area where a metal layer, a via, etc. formed in a BEOL process are not arranged, and the second keep out zone (KoZ 2) may be an area where an active semiconductor device formed in a FEOL process is not arranged. In FIG. 5, the first keep out zone (KoZ 1) and the second keep out zone (KoZ 2) are illustrated as extending through the substrate layer (510c), but this is for convenience of understanding, and in reality, the first keep out zone (KoZ 1) and the second keep out zone (KoZ 2) are areas around the through via (531) on the substrate layer (510b), and may not extend through the substrate layer (510c).

In one embodiment, the substrate layer (510c) may include protection circuits (537) positioned on and/or within the substrate layer (510c). The protection circuits (537) may be positioned in the second keep out zone (KoZ 2) and may be positioned outside the first keep out zone (KoZ 1). The protection circuits (537) may be positioned outside the first keep out zone (KoZ 1) and inside the second keep out zone (KoZ 2) on both sides of the through via (531).

In one embodiment, the interface circuit (520) may be disposed adjacent to a first protection circuit (537_1) among a plurality of protection circuits (537) in a first direction (X direction). The first protection circuit (537_1) may be positioned between the interface circuit (520) and the through-via (531) in the first direction (X direction). In one embodiment, the interface circuit (520), the protection circuit (537_1), and the through-via (531) may be sequentially positioned in the first direction (X). Additionally, a protection circuit (537_2) may be further positioned on the opposite side of the protection circuit (537_1) with the through-via (531) as the center.

In one embodiment, the BEOL layer (510a) may include a plurality of metal layers (540). The plurality of metal layers (540) may include a plurality of metal lines and a plurality of metal vias connecting the metal lines. The interface circuit (520) may be electrically connected to the through vias (531) through the plurality of metal layers (540). Specifically, the interface circuit (520) may transmit a logic signal to the through vias (531) through the plurality of metal layers (540), or receive a logic signal from the through vias (531). The interface circuit (520) may transmit and receive a logic signal to and from the through vias (531) through the first path (560).

In one embodiment, the protection circuits (537) may be electrically connected to the through vias (531) through a plurality of metal layers (540). The protection circuits (537) may be electrically connected to the interface circuit (520) through a plurality of metal layers (540). For example, charge generated during an etching process to form the through vias (531) may flow to the protection circuits (537) through a second path (570). Charge generated during the etching process to form the through vias (531) may be discharged through the protection circuits (537) located in the second keep out zone (KoZ 2). In one embodiment, the protection circuits (537) may be connected to a plurality of metal layers (540) that connect the interface circuit (520) and the through vias (531). The protection circuits (537) serve as electrical paths for discharging charges flowing through the interface circuit (520), and can protect the transistors within the interface circuit (520) from various electrical effects.

In one embodiment, a redistribution layer (RDL) (551) may be positioned on the backside (510b) of the substrate layer (510c) to form electrical connections with adjacent dies. Through-vias (531) may provide electrical connections between the plurality of metal layers (540) and the redistribution layer (551) through conductive materials within the through-vias (531). The redistribution layer (551) may include a plurality of metallization patterns between adjacent dies. The redistribution layer (551) may form electrical connections with the plurality of metal layers (540) through conductive materials within the through-vias (531).

In one embodiment, the redistribution layer (551) may be connected to an interconnect structure (553). The interconnect structure (553) may include bumps (e.g., microbumps or solder bumps) or hybrid copper bonding, etc. The interconnect structure (553) may be formed of a conductive material such as copper, aluminum, etc. The interface circuit (520) may transmit and receive logic signals to and from the outside through the interconnect structure (553), the redistribution layer (551), the through vias (531), and the plurality of metal layers (540). However, some of these configurations may be omitted or other necessary configurations may be added as needed.

FIG. 6 is a diagram illustrating a TSV cell according to one embodiment. Specifically, it is a schematic layout diagram illustrating a TSV cell including a plurality of protection circuits.

In one embodiment, the TSV cell (60) may include protection circuits (65, 67) positioned in a second keep out zone (KoZ 2) extending in a first direction (X). Specifically, the second keep out zone (KoZ 2) may include a first region (64) extending in a first direction (X direction) from the first keep out zone (KoZ 1) and a second region (62) extending in a direction opposite to the first direction, each region including protection circuits (65, 67). The protection circuits (65, 67) may be positioned in the second keep out zone (KoZ 2) on both sides of the through via (68). The protection circuits (65, 67) may be positioned outside the first keep out zone (KoZ 1) on both sides of the through via (68). The structures of the protection circuits (65, 67) may be identical or different. However, the present invention is not limited thereto, and only one of the first region (64) and the second region (62) may include the protection circuit. The through via (68) and the protection circuits (65, 67) may be connected through a plurality of metal layers (66_1).

In one embodiment, the TSV cell (60) and the interface circuit (63) may be arranged adjacent to each other in a second direction (Y) that is perpendicular to the first direction (X direction). The interface circuit (63) may be arranged adjacent to the first keep out zone (KoZ 1) in the second direction (Y). No element may be positioned between the interface circuit (63) and the first keep out zone (KoZ 1) in the second direction (Y). The through via (68) of the TSV cell (60) may transmit a logic signal received from the adjacently arranged interface circuit (63) to another integrated circuit, or may transmit a logic signal received from another integrated circuit to the interface circuit (63). The through via (68) and the interface circuit (33) may be connected through a plurality of metal layers (66_2).

Fig. 7 is a perspective view showing a cross-section taken along line B-B' of Fig. 6.

Specifically, FIG. 7 is a cross-sectional view of one integrated circuit (700) among a plurality of integrated circuits constituting a three-dimensional integrated circuit. Referring to FIG. 7, the three-dimensional integrated circuit according to one embodiment may further include additional integrated circuits above and/or below the integrated circuit (700). For example, the integrated circuit (700) according to FIG. 7 may correspond to the first integrated circuit (150) according to FIG. 1. In addition, although a portion of the integrated circuit (700) is illustrated here, the integrated circuit (700) may include more configurations. Meanwhile, for the sake of simplicity, a description of configurations similar or identical to those of FIG. 5 is omitted here.

In one embodiment, the integrated circuit (700) may include an interface circuit (720) disposed on and/or within a substrate layer (710c). The substrate layer (710c) may include a through via (731) extending through the substrate layer (710c). A first keep out zone (KoZ 1) around the through via (731) may be determined on the substrate layer (710c) by a first distance (733) in a first direction (X) from the through via (731) and a second distance (734) in a second direction (Y) perpendicular to the first direction (X). On the substrate layer (710c), a second keep out zone (KoZ 2) around the through via (731) can be determined by a third distance (735) in the first direction (X) from the through via (731) and a second distance (734) in the second direction (Y) perpendicular to the first direction (X). The first distance (733) and the second distance (734) can be different from or the same as each other, and the third distance (735) can be greater than the first distance (733). Therefore, the second keep out zone (KoZ 2) can occupy a larger area than the first keep out zone (KoZ 1).

In one embodiment, the integrated circuit (700) may include a protection circuit (737) disposed on and/or within the substrate layer (710c). The protection circuit (737) may be located in the second keep out zone (KoZ 2) and may be located outside the first keep out zone (KoZ 1).

In one embodiment, the interface circuit (720) can be positioned adjacent to the through via (731) in a second direction (Y) that is perpendicular to the first direction (X direction). The interface circuit (720) can be positioned adjacent to the first keep out zone (KoZ 1) in a second direction (Y) that is perpendicular to the first direction (X direction). No components can be positioned between the interface circuit (720) and the first keep out zone (KoZ 1) in the second direction (Y). The interface circuit (720) and the protection circuit (737) can be positioned perpendicular to each other with respect to the through via (731) and can be positioned adjacent to the through via (731) in a perpendicular direction to each other.

In one embodiment, the interface circuit (720) can transmit logic signals to or receive logic signals from the through vias (731) through multiple metal layers (740) within the BEOL layer (710a). The interface circuit (720) can transmit and receive logic signals to and from the through vias (731) via a first path (760).

In one embodiment, the protection circuit (737) may be electrically connected to the through via (731) and the interface circuit (720) through a plurality of metal layers (740). For example, charge generated during the etching process to form the through via (731) may flow to the protection circuit (737) through the second path (770).

A semiconductor device (700) according to one embodiment can minimize the distance between an interface circuit (720) and a through via (731). Accordingly, the length of a metal layer (740) connecting the interface circuit (720) and the through via (731) is reduced, which has the advantage of improving characteristics of an integrated circuit, such as SI (Signal Integrity).

FIG. 8 is a drawing for explaining the effect of reducing the area occupied by a protection circuit according to one embodiment.

(a) shows a TSV cell (810), a protection circuit (811), and an interface circuit (813) according to a comparative example. According to the comparative example (a), the protection circuit (811) is positioned adjacent to the TSV cell (810) outside the TSV cell (810), and the protection circuit (811) and the interface circuit (813) are positioned adjacent to each other in the same direction (e.g., the first direction) as the direction in which the protection circuit (811) is adjacent to the TSV cell (810).

(b) illustrates a TSV cell (820), a protection circuit (821), and an interface circuit (823) according to one embodiment. According to one embodiment (b), the protection circuit (821) is positioned in a FEOL keep-out zone (822) inside the TSV cell (820), and the protection circuit (821) and the interface circuit (823) may be positioned adjacent to each other in the same direction (e.g., a first direction) as the direction in which the protection circuit (821) is positioned adjacent to the through via (825). Although the TSV cell (820) is illustrated here as including a plurality of protection circuits (821), the present invention is not limited thereto.

(c) illustrates a TSV cell (830), a protection circuit (821), and an interface circuit (823) according to one embodiment. According to one embodiment (c), the protection circuit (831) is positioned in a FEOL keep-out zone (832) inside the TSV cell (830), and the TSV cell (820) and the interface circuit (823) may be positioned adjacent to each other in a direction (e.g., a second direction) perpendicular to the direction (first direction) in which the protection circuit (821) is positioned adjacent to the through via (835).

(d) is a table illustrating the areas occupied by the TSV cell, protection circuit, and interface circuit according to the comparative example (a) and the embodiments (b) and (c) of the present invention. According to the table of (d) of Fig. 8, the length (X1) in the first direction of the TSV cell (810), protection circuit (811), and interface circuit (813) according to the comparative example (a) is 23 um, and the length (Y1) in the second direction is 10 um, so the area occupied by the TSV cell (810), protection circuit (811), and interface circuit (813) according to the comparative example (a) is 230 um2. Meanwhile, since the length (X2) in the first direction of the TSV cell (820), the protection circuit (821), and the interface circuit (823) according to one embodiment (b) is 18.5 um, and the length (Y2) in the second direction is 10 um, the area occupied by the TSV cell (820), the protection circuit (821), and the interface circuit (823) according to one embodiment (b) is 185 um, and since the length (X3) in the first direction of the TSV cell (830), the protection circuit (831), and the interface circuit (833) according to one embodiment (c) is 14 um, and the length (Y3) in the second direction is 14 um, the area occupied by the TSV cell (830), the protection circuit (831), and the interface circuit (833) according to one embodiment (c) is 196 um.

That is, compared to the area according to comparative example (a), the area occupied by the TSV cell, protection circuit, and interface circuit according to embodiments (b) and (c) can be reduced by 19.57% and 14.78%, respectively. There is an advantage in that the size of the semiconductor device can be reduced according to the reduced area, or the area of the integrated circuit can be efficiently utilized by arranging other logic elements.

FIG. 9 is a schematic diagram illustrating a layout of an integrated circuit. In one embodiment, the integrated circuit (900) may include a plurality of metal lines (ML) extending in a row direction (e.g., X direction). The plurality of metal lines (ML) may intersect to provide a power supply voltage (e.g., VDD) and a ground voltage (VSS).

In one embodiment, the integrated circuit (900) may include a plurality of standard cells. Here, the standard cells may include logic elements, memory elements, and filler cells. The plurality of standard cells may be arranged to overlap with metal lines (ML). Here, standard cells arranged in each row (R) are illustrated, but are not limited thereto, and the standard cells may be formed to span a plurality of rows (R).

In one embodiment, the integrated circuit (900) may further include a through-silicate via (TSV) area. The TSV area may include a TSV cell including a through-via, a protection circuit, and an interface circuit for transmitting and receiving logic signals with the through-via. The TSV areas may be regularly arranged on the integrated circuit (900). For example, a plurality of TSV areas may be arranged to be spaced apart from each other by a predetermined distance in a first direction (X) and a second direction (Y). Alternatively, the TSV areas may be irregularly arranged on the integrated circuit (900).

Meanwhile, the TSV cell, the protection circuit, and the interface circuit may be implemented as a single TSV module. In one embodiment, the TSV region may include TSV modules arranged in an m x n configuration (m and n are natural numbers greater than or equal to 1). For example, the TSV region may include one TSV module or may include a plurality of TSV modules. In one embodiment, some TSV regions among the plurality of TSV regions may include one TSV module, and the remaining TSV regions may include a plurality of TSV modules arranged in an m x n configuration.

The TSV region may further include standard cells. The TSV region may include TSV modules and standard cells placed in the remaining region. A detailed description of the TSV region is provided with reference to FIGS. 10 and 11.

Fig. 10 is a drawing showing a TSV region according to a comparative example. Specifically, the TSV region according to the comparative example of Fig. 10 is illustrated as including a plurality of TSV modules arranged in a 3 x 3 configuration, but is not limited thereto.

A TSV region (1000) according to a comparative example may include a plurality of TSV modules (1010, 1020, 1030). A first TSV module (1010) according to a comparative example may include a TSV cell (1012), a protection circuit (1013), and an interface circuit (1011). The protection circuit (1013) within the first TSV module (1010) according to the comparative example may be located outside the TSV cell (1012).

According to a comparative example, the first TSV module (1010) and the second TSV module (1020) may be arranged to be spaced apart from each other by a first distance (DX) that is predetermined in a first direction (X direction). The first TSV module (1010) and the third TSV module (1030) may be arranged to be spaced apart from each other by a second distance (DY) that is predetermined in a second direction (Y direction) that is perpendicular to the first direction.

According to a comparative example, the interface circuit (1021) for transmitting and receiving a logic signal and a through-via within the second TSV module (1020) may be arranged adjacent to the first TSV module (1010). For example, the interface circuit (1021) and the first TSV module (1010) may be arranged to be attached in the first direction (X direction). Accordingly, no standard cell may be positioned between the interface circuit (1021) and the first TSV module (1010).

According to a comparative example, the first TSV module (1010) and the third TSV module (1030) may be arranged adjacently in the second direction (Y direction). The first TSV module (1010) and the third TSV module (1030) may be spaced apart from each other by a third distance (RY) in the second direction (Y direction). A plurality of standard cells may be positioned between the first TSV module (1010) and the third TSV module (1030). In addition, a plurality of metal layers may be positioned between the first TSV module (1010) and the third TSV module (1030).

According to a comparative example, the area where standard cells can be positioned in the TSV area (1000) is only the area of the third distance (RY) between the first TSV module (1010) and the third TSV module (1030). That is, many standard cells are positioned in a limited space, which may cause various problems such as routing congestion.

FIG. 11 is a diagram illustrating a TSV region according to one embodiment. Specifically, the TSV region according to one embodiment of FIG. 11 is illustrated as including, but not limited to, a plurality of TSV cells, protection circuits, and interface circuits arranged in a 3 x 3 configuration. In addition, each TSV cell, protection circuit, and interface circuit may be implemented as a single TSV module.

A TSV region (1100) according to one embodiment may include a plurality of TSV modules (1110, 1120, 1130). A first TSV module (1110) according to one embodiment may include a TSV cell (1114), a protection circuit (1113), and an interface circuit (1111). A protection circuit (1113) in a second TSV module (1110) according to one embodiment may be located inside a TSV cell (1114). A protection circuit (1113) in a second TSV module (1110) according to one embodiment may be located in a second keep out zone (KoZ 2) in a TSV cell (1114). Meanwhile, the structure of the protection circuit (1113) is not limited thereto.

In one embodiment, the first TSV module (1110) and the second TSV module (1120) may be arranged to be spaced apart from each other by a first distance (DX) that is predetermined in a first direction (X direction). The first TSV module (1110) and the third TSV module (1130) may be arranged to be spaced apart from each other by a second distance (DY) that is predetermined in a second direction (Y direction) that is perpendicular to the first direction. In one embodiment, the first TSV module (1110) and the second TSV module (1020) may be spaced apart from each other by the first distance (DX) in the first direction (X direction), such that a space of a third distance (RX') in the first direction (X direction) may exist between the first TSV module (1110) and the second TSV module (1020). In addition, since the first TSV module (1110) and the third TSV module (1030) are spaced apart by a second distance (DY) in the second direction (Y direction), a space of a fourth distance (RY') in the second direction (Y direction) may exist between the first TSV module (1110) and the third TSV module (1030).

In one embodiment, a plurality of standard cells may be positioned in the region of the third distance (RX') and the region of the fourth distance (RY'). That is, since the protection circuit is positioned within the TSV cell, the area in which the standard cells can be positioned within the TSV region (1100) increases, the area can be utilized efficiently, and there is an advantage in that problems such as routing congestion can be solved. In addition, the TSV region (1100) according to one embodiment can reduce the first distance (DX) and the second distance (DY) as needed. That is, by positioning a plurality of TSV modules (1110, 1120, 1130) closer to each other, there is an advantage in that the area occupied by the TSV region (1100) in the integrated circuit can be reduced.

FIG. 12 is a diagram illustrating a signal transmission path of a logic signal according to one embodiment. Specifically, it illustrates a signal transmission path of a logic signal transmitted from a first integrated circuit to a second integrated circuit through a through via.

In one embodiment, a three-dimensional integrated circuit (1200) may include a first integrated circuit (1210) and a second integrated circuit (1220). The first integrated circuit (1210) may include a logic circuit (1212), an interface circuit (1213), and a TSV cell (1215). In one embodiment, the interface circuit (1213) and the TSV cell (1215) may be implemented as a TSV module. In one embodiment, the TSV cell (1215) may include a through via (1216) and may include a protection circuit (1214) within a region spaced a predetermined distance from the through via (1216). In one embodiment, the second integrated circuit (1210) may include an interface circuit (1222) and a logic circuit (1223). The second integrated circuit (1220) may further include a protection circuit (1221). However, as needed, some components within each die may be omitted or other necessary components may be added.

In one embodiment, the first integrated circuit (1210) can receive a logic signal from the outside through an input port (1211). The logic signal can be transmitted to a through-substrate via (1215) through a logic circuit (1212) and an interface circuit (1213) within the first integrated circuit (1210). The logic signal can be transmitted to the second integrated circuit (1220) through an interconnect structure (1230). The logic signal can be transmitted to the outside through an output port (1224) through an interface circuit (1222) and a logic circuit (1223) within the second integrated circuit (1220).

Fig. 13 is a drawing showing a semiconductor device according to an embodiment.

Referring to FIG. 13, a semiconductor device (1300) may be a memory module including at least one stack semiconductor chip (1330) mounted on a package substrate (1310) such as a printed circuit board and a system-on-chip (SOC) (1350).

An interposer (1320) may be optionally further provided on the package substrate (1310). The stacked semiconductor chip (1330) may be formed as a chip-on-chip (CoC). The stacked semiconductor chip (1330) may include at least one memory chip (1340) stacked on a buffer chip (1360), such as a logic chip. The buffer chip (1360) and the at least one memory chip (1340) may be connected to each other by a through silicon via (TSV). In one embodiment, the buffer chip (1360) and the at least one memory chip (1340) may include the protection circuit and interface circuits described with reference to FIGS. 1 to 12. Accordingly, the semiconductor device (1300) according to one embodiment may include a through-substrate via electrically connecting the stack semiconductor chips (1330), and at least one memory chip (1340) may include a first keep-out zone and a second keep-out zone around the through-substrate via. The semiconductor device (1300) according to one embodiment may efficiently utilize the area of the semiconductor device (1300) by designing a protection circuit in the at least one memory chip (1340) to be located within the second keep-out zone around the through-substrate via. In one embodiment, the stack semiconductor chip (1330) may be, for example, a high bandwidth memory (HBM) of 500 GB/sec to 1 TB/sec, or more.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the following claims also fall within the scope of the present invention.

Claims (20)

A first integrated circuit comprising a first substrate,
A second integrated circuit stacked on the first integrated circuit,
A through via penetrating the first substrate and electrically connecting the first integrated circuit and the second integrated circuit, and
A plurality of protection circuits located on both sides of the through via within a keep out zone surrounding the through via and electrically connected to the through via.
A three-dimensional integrated circuit comprising: In the first paragraph,
A first keep out zone including an area spaced apart from the periphery of the above through via by a first distance in a first direction, and
a second keep out zone including an area spaced apart from the first through-via by a second distance greater than the first distance in the first direction from the periphery of the first keep out zone,
A three-dimensional integrated circuit, wherein the plurality of protection circuits are located within the second keep out zone. In the first paragraph,
An interface circuit adjacent to the first protection circuit among the plurality of protection circuits in the first direction outside the second keep-out zone and transmitting and receiving a logic signal with the second integrated circuit through the through via.
A three-dimensional integrated circuit comprising: In the third paragraph,
The second keep out zone includes a first region and a second region which are outer regions of the first keep out zone on both sides of the through via,
A three-dimensional integrated circuit, wherein the first protection circuit is located in the first region, and the second protection circuit among the plurality of protection circuits is located in the second region. In the third paragraph,
A three-dimensional integrated circuit, wherein the above through via and the interface circuit are electrically connected through a plurality of metal layers, and the plurality of protection circuits are electrically connected to the plurality of metal layers. In the first paragraph,
An interface circuit adjacent to the first keep-out zone in a second direction perpendicular to the first direction outside the second keep-out zone, and transmitting and receiving a logic signal with the second integrated circuit through the through via.
A three-dimensional integrated circuit comprising: In the first paragraph,
The above first keep out zone is an area that does not include a metal layer other than the metal layer connected to the through via,
A three-dimensional integrated circuit, wherein the second keep-out zone is an area in which no active semiconductor devices are placed. In the first paragraph,
A three-dimensional integrated circuit, wherein the plurality of protection circuits are antenna protection circuits configured to provide antenna effect protection to the first integrated circuit. In paragraph 8,
The above antenna protection circuit is a three-dimensional integrated circuit, which is an antenna diode. In the first paragraph,
A three-dimensional integrated circuit, wherein the plurality of protection circuits are ESD (Electrostatic Discharge) protection circuits configured to provide ESD protection to the first integrated circuit. Through vias penetrating the first substrate,
A first keep out zone located on the first substrate, the first boundary spaced apart from the through via in a first direction by a first distance around the through via, and a second boundary spaced apart from the through via in a second direction perpendicular to the first direction by a second distance,
A second keep out zone located on the first substrate, the second keep out zone including a third boundary spaced apart from the through via in the first direction by a third distance around the through via, and a fourth boundary spaced apart from the through via in the second direction by the second distance,
A first protection circuit located outside the first keep-out zone and inside the second keep-out zone, and electrically connected to the through via, and
An interface circuit located outside the second keep-out zone and electrically connected to the through via.
An integrated circuit comprising: In Article 11,
An integrated circuit wherein the third distance is greater than the first distance. In Article 11,
An integrated circuit, wherein the interface circuit, the first protection circuit, and the through via are sequentially arranged in the first direction. In Article 13,
An integrated circuit further comprising a second protection circuit positioned outside the first keep out zone and inside the second keep out zone, and positioned on the opposite side of the first protection circuit with respect to the through via. In Article 11,
An integrated circuit wherein the interface circuit is positioned adjacent to the first keep out zone in the second direction. In Article 15,
An integrated circuit in which no element is located between the interface circuit and the first keep out zone. In Article 11,
An integrated circuit, wherein the first protection circuit is one of an antenna protection circuit configured to provide antenna effect protection to a transistor located on the first substrate and an ESD protection circuit configured to provide ESD protection. 1st substrate,
A through via penetrating the first substrate,
A first keep out zone located on the first substrate and including an area around the through via and extending a first distance from the through via,
A second keep-out zone located on the first substrate and including an area extending from the first keep-out zone in a first direction and a second distance in a direction opposite to the first direction,
A protection circuit located outside the first keep-out zone and inside the second keep-out zone, and electrically connected to the through via, and
An interface circuit adjacent to the first keep-out zone in a second direction perpendicular to the first direction and electrically connected to the through via.
A three-dimensional integrated circuit comprising: In Article 18,
A three-dimensional integrated circuit, wherein the first keep out zone is a keep out zone in a back-end-of-line (BEOL) process, and the second keep out zone is a keep out zone in a front-end-of-line (FEOL) process. In Article 18,
A three-dimensional integrated circuit in which no elements are located between the interface circuit and the first keep-out zone.