KR20250128860A - A magnetoresistive random access memory device - Google Patents

Abstract

A magnetoresistive memory device according to one or more embodiments of the present disclosure includes a memory structure disposed between an upper wiring layer and a lower wiring layer, and a cobalt capping layer disposed between the lower wiring included in the lower wiring layer and the memory structure, wherein the memory structure includes a lower pad in contact with an upper surface of the cobalt capping layer and having a lower surface having a horizontal width wider than a horizontal width of the upper surface of the cobalt capping layer, and an MTJ structure disposed on an upper surface of the lower pad, wherein the horizontal width of the upper surface of the lower pad is the same as the horizontal width of the lower surface of the MTJ structure, and the horizontal width of the lower surface of the cobalt capping layer is the same as the horizontal width of the upper surface of the lower wiring, and the upper wiring layer and the lower wiring layer may be two wiring layers disposed adjacent to each other among a plurality of wiring layers disposed on an upper surface of a transistor structure.

Description

Magnetoresistive random access memory device {A MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a magnetoresistive memory device (MRAM device).

Embedded MRAM cell structures are continuously being developed. In embedded MRAM cell structures, MRAM cells can be positioned between multiple wiring layers formed during the BEOL process. Recently, research is being conducted to reduce the circuit line width and vertical thickness of MRAM devices.

The problem to be solved by the present invention is to provide a magnetoresistive memory device having a reduced circuit line width and reduced vertical thickness.

However, the problems to be solved by the present invention are not limited to the problems mentioned above, and other problems can be clearly understood by those skilled in the art from the description below.

In order to solve the above-described problem, a magnetoresistive memory device according to an embodiment of the present disclosure includes a memory structure disposed between an upper wiring layer and a lower wiring layer, and a cobalt capping layer disposed between the lower wiring included in the lower wiring layer and the memory structure, wherein the memory structure includes a lower pad in contact with an upper surface of the cobalt capping layer and having a lower surface having a horizontal width wider than a horizontal width of the upper surface of the cobalt capping layer, and an MTJ structure disposed on an upper surface of the lower pad, wherein the horizontal width of the upper surface of the lower pad is the same as the horizontal width of the lower surface of the MTJ structure, and the horizontal width of the lower surface of the cobalt capping layer is the same as the horizontal width of the upper surface of the lower wiring, and the upper wiring layer and the lower wiring layer may be two wiring layers disposed adjacent to each other among a plurality of wiring layers disposed on an upper portion of a transistor structure.

A magnetoresistive memory device according to one or more embodiments of the present disclosure can form a stable connection between an MTJ structure and the lower wiring by including a cobalt capping layer formed on an upper surface of a lower wiring and a lower pad disposed on an upper surface of the cobalt capping layer, and can reduce a circuit line width of the device and a vertical thickness of the device.

The effects of the present invention are not limited to the effects described above, and effects not mentioned can be clearly understood by a person skilled in the art to which the present invention pertains from this specification and the attached drawings.

FIG. 1 is a cross-sectional view of a magnetoresistive memory device according to one embodiment of the present disclosure.
FIG. 2 is a cross-sectional view of an embedded cell structure according to one embodiment of the present disclosure.
FIGS. 3 to 10 are cross-sectional views illustrating a method for manufacturing a magnetoresistive memory element according to one embodiment of the present disclosure.
FIG. 11 is a cross-sectional view of an embedded cell structure according to one embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. Identical components in the drawings are designated by the same reference numerals, and redundant descriptions thereof will be omitted.

Hereinafter, embodiments of the present disclosure will be described clearly and in detail to such an extent that a person having ordinary skill in the art of the present disclosure can easily practice the present disclosure.

In this specification, elements described as being “isolated” from other elements in a particular direction (e.g., vertically spaced, horizontally spaced, etc.) and/or elements described as being “isolated” from other elements will be understood to be isolated from direct contact with other elements in the particular direction (e.g., vertically spaced, horizontally spaced, etc.). Similarly, elements described as being “isolated” from one another in a particular direction (e.g., vertically spaced, horizontally spaced, etc.) and/or elements described as being “isolated” from one another will be understood to be isolated from direct contact with one another in the particular direction (e.g., vertically spaced, horizontally spaced, etc.). Similarly, a structure positioned between two other structures and separating the two other structures from one another will be understood to be configured to be isolated such that the two other structures do not come into direct contact with one another.

FIG. 1 is a cross-sectional view of a magnetoresistive memory element (10) according to one embodiment of the present disclosure.

Referring to FIG. 1, a magnetoresistive memory element (10) may include a transistor structure (100), an embedded cell structure (300), and a bit line (400).

The transistor structure (100) may include a substrate (101), a lower interlayer insulating layer (110a), and an upper interlayer insulating layer (110b).

The substrate (101) may include a device isolation layer (102) and a cell transistor (200). The substrate (101) may include silicon, germanium, silicon-germanium, or a group III-V compound such as GaP, GaAs, GaSb, etc.

A device isolation layer (102) may be formed on a substrate (101). The device isolation layer (102) may divide the substrate (101) into an active region and a field region. The device isolation layer (102) may be formed through a shallow trench isolation (STI) process. A cell transistor (200) may be formed in the active region divided by the device isolation layer (102).

A cell transistor (200) may be formed in an active area of a substrate (101). The cell transistor (200) may be electrically connected to a memory structure (MS). In some embodiments, as illustrated in FIG. 1, two cell transistors (200) may be formed in an active area separated by a device isolation layer (102).

In some embodiments, the cell transistor (200) may be a buried gate transistor. In this case, the cell transistor (200) may include a gate insulating layer (202), a gate electrode (203), a hard mask pattern (204), a first impurity region (210), and a second impurity region (212). The gate insulating layer (202), the gate electrode (203), and the hard mask pattern (204) may be disposed within a trench (201) extending in the second horizontal direction (Y direction). In addition, the first impurity region (210) and the second impurity region (212) may be formed by implanting impurities into active regions disposed on both sides of the gate, respectively. As illustrated in FIG. 1, the first impurity region (210) may be a common source region for two cell transistors (200). As illustrated in FIG. 1, the first impurity region (210) may be a source region, and the second impurity region (212) may be a drain region.

Although Fig. 1 only illustrates that the cell transistor (200) of the transistor structure (100) is a buried gate type transistor, this is only for convenience of explanation. It goes without saying that the cell transistor (200) that may be included in the transistor structure (100) may be implemented as various types of transistors, such as a planar gate type transistor or a fin type transistor.

The source line (114) may be arranged to penetrate the lower interlayer insulating layer (110a). The source line (114) may be in contact with the upper surface of the first impurity region (210). The source line (114) may include, for example, at least one of a metal such as tungsten, titanium, tantalum, etc., or a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, etc.

The contact plug (112) may be positioned to penetrate the lower interlayer insulating layer (110a) and the upper interlayer insulating layer (110b). The contact plug (112) may be in contact with the upper surface of the second impurity region (212). The upper surface of the contact plug (112) may be positioned at a vertical level higher than the upper surface of the source line (114).

In addition, although not illustrated in detail in FIG. 1, a first wiring included in a first wiring layer may be arranged on a contact plug (112), and a first wiring inter-insulating layer may be arranged between a plurality of first wirings. The contact plug (112) may be electrically connected to the first wiring.

Here, the first wiring layer may refer to the lowest wiring layer positioned at the bottom among the plurality of wiring layers positioned on the upper portion of the transistor structure (100). For example, the plurality of wiring layers may include the first to tenth wiring layers. In this case, among the ten wiring layers, the first wiring layer is the lowest wiring layer, and the tenth wiring layer is the uppermost wiring layer. The lowermost wiring layer may be in contact with the contact plug (112), and the uppermost wiring layer may be in contact with the bit line (400).

The embedded cell structure (300) may include a lower wiring layer and a memory structure (MS).

The lower wiring layer may include a plurality of lower wirings (302) and an inter-lower wiring insulation layer (301) surrounding the plurality of lower wirings (302). The lower wiring layer may refer to a wiring layer disposed at the bottom of the memory structure (MS).

The memory structure (MS) may be disposed between two adjacent wiring layers. In one embodiment, the memory structure (MS) may be disposed between the third wiring layer and the fourth wiring layer, in which case the lower wiring layer may be the third wiring layer. In another embodiment, the memory structure (MS) may be disposed between the fifth wiring layer and the sixth wiring layer, in which case the lower wiring layer may be the fifth wiring layer. In the present disclosure, for convenience of explanation, it is assumed that the lower wiring layer is the Nth wiring layer (N is a natural number greater than or equal to 1).

The lower wiring (302) may include a metal. In some embodiments, the lower wiring (302) may be composed of copper or a copper alloy. In this case, the lower wiring (302) may be formed through a damascene process. In addition, the lower wiring (302) may not include aluminum or may contain little aluminum. The above examples are merely illustrative of the types of metals included in the lower wiring (302), and it is to be understood that the lower wiring (302) may include various types of metals, such as tungsten, titanium, and tantalum.

The lower interconnection insulating layer (301) can surround a plurality of lower interconnections (302). The lower interconnection insulating layer (301) can be formed of silicon oxide or an insulating material having a lower dielectric constant than silicon oxide. The lower interconnection insulating layer (301) can be formed of a tetraethyl orthosilicate (TEOS) film, an ultra low K (ULK) film, or an extreme low-k (ELK) film. In some embodiments, the ULK film or the ELK film can have a dielectric constant of about 2 to about 3.5. In some embodiments, the lower interconnection insulating layer (301) can include a SiOC film, a SiOF film, a SiCH film, a SiCOH film, or a combination thereof.

A cobalt capping layer (310) may be disposed on the upper surface of the lower wiring (302). The vertical thickness of the cobalt capping layer (310) may be several nm to several tens of nm. The cobalt capping layer (310) may include cobalt (Co) and may be formed by a selective deposition process on the upper surface of the lower wiring (302). The horizontal width of the lower surface of the cobalt capping layer (310) may be substantially the same as the horizontal width of the upper surface of the lower wiring (302).

An etch-stop layer (311) may be disposed on top of the lower wiring inter-insulating layer (301). The etch-stop layer (311) may include a material having a high etching selectivity with respect to the first insulating layer (321). In some embodiments, the etch-stop layer (311) may include silicon nitride, and the first insulating layer (321) may include silicon carbide.

The lower surface of the etch-stop layer (311) and the lower surface of the cobalt capping layer (310) may be arranged at the same vertical level. The vertical thickness of the etch-stop layer (311) may be greater than the vertical thickness of the cobalt capping layer (310). The etch-stop layer (311) may surround the sidewall of the cobalt capping layer (310).

The first insulating layer (321) may be disposed on the upper surface of the etch stop layer (311) and may be disposed under the protective layer (342). The first insulating layer (321) may include silicon carbide, aluminum nitride, or a combination thereof. The first insulating layer (321) may be disposed between a plurality of lower pads (322). The first insulating layer (321) may surround the lower structure of the lower pads (322). Since the first insulating layer (321) includes a wide band gap material such as silicon carbide, aluminum nitride, or the like, a phenomenon in which leakage current flows between adjacent lower pads (322) and lower wiring (302) may be prevented.

As illustrated in FIG. 1, the lower surface of the first insulating layer (321) may have a flat shape, while the upper surface of the first insulating layer (321) may have a concave shape with respect to the vertical direction. Specifically, the upper surface of the first insulating layer (321) may have a convex shape in the downward direction. The side wall of the first insulating layer (321) may be inclined at a constant incline with respect to the vertical direction. The side wall of the first insulating layer (321) may be inclined in a direction away from the central axis of the first insulating layer (321) as it goes from the top to the bottom.

The memory structure (MS) may include a lower pad (322), an MTJ structure (330), and an upper pad (341).

The lower pad (322) may be in contact with the upper surface of the cobalt capping layer (310). The horizontal width of the lower surface of the lower pad (322) may be greater than the horizontal width of the upper surface of the cobalt capping layer (310). The horizontal width of the upper surface of the lower pad (322) may be the same as the horizontal width of the lower surface of the MTJ structure (330). In addition, the lower pad (322) may include tantalum (Ta), tantalum nitride (TaN), tantalum oxide (TaOx), or a combination thereof.

The lower pad (322) can electrically connect the lower wiring (302) and the MTJ structure (330). The lower pad (322) can be formed in a negative manner. The method for forming the lower pad (322) in a negative manner will be described in detail in the description of FIGS. 6 to 8 below.

The MTJ structure (330) may include a fixed layer (331), a tunnel barrier layer (332), and a free layer (333). The fixed layer (331), the tunnel barrier layer (332), and the free layer (333) may be sequentially stacked. The side walls of the MTJ structure (330) may be inclined at a constant inclination with respect to the vertical direction. The side walls of the MTJ structure (330) may be inclined in a direction away from the central axis of the MTJ structure (330) as they go from the top to the bottom.

The upper pad (341) may be arranged on the upper side of the MTJ structure (330). The horizontal width of the lower side of the upper pad (341) may be the same as the horizontal width of the upper side of the MTJ structure (330). The upper pad (341) may also function as an etching mask in an etching process for forming the MTJ structure (330) arranged thereunder. The upper pad (341) may include at least one of a metal such as tungsten, titanium, tantalum, iron, or a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, or the like. The sidewall of the upper pad (341) may be inclined. For example, as illustrated in FIG. 1, the sidewall of the upper pad (341) may be inclined at the same incline as the sidewall of the MTJ structure (330). Although not shown in detail in FIG. 1, the upper pad (341) may be in contact with the upper wiring of the upper wiring layer disposed on the upper side of the embedded cell structure (300).

The protective layer (342) may be a material layer that protects the memory structure (MS). The protective layer (342) may surround the sidewall of the memory structure (MS). The protective layer (342) may be in contact with the upper surface of the first insulating layer (321). The protective layer (342) may include silicon nitride.

On the protective layer (342), a second insulating layer (350) may be disposed to surround the protective layer (342) and be formed at a relatively higher vertical level than the first insulating layer (321). Although not illustrated in detail in FIG. 1, the second insulating layer (350) may be in contact with the upper inter-wire insulating layer of the upper wiring layer disposed on top of the embedded cell structure (300).

The bit line (400) may include a barrier metal layer (401) and a metal layer (402). The barrier metal layer (401) may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The metal layer (402) may include copper, tungsten, aluminum, or the like. The bit line (400) may be in contact with the top wiring layer. In some embodiments, when the wiring layer is not disposed on top of the embedded cell structure (300), the bit line (400) may be in contact with the top pad (341).

A magnetoresistive memory device (10) according to one embodiment of the present disclosure includes a cobalt capping layer (310) and a lower pad (322) disposed between an MTJ structure (330) and a lower wiring (302), thereby forming a stable connection structure even when the circuit line width and vertical thickness are reduced.

Even when the pitch between the plurality of lower wirings (302) is very small, the cobalt capping layer (310) formed on the upper surface of the lower wirings (302) can suppress leakage current that may occur between the plurality of lower wirings (302). In addition, the cobalt capping layer (310) can also perform a barrier function that prevents the material constituting the lower wirings (302) from diffusing toward the MTJ structure (330).

In addition, since a lower pad (322) is arranged between the lower wiring (302) and the MTJ structure (330), the magnetoresistive memory element (10) may not include a bottom electrode contact (BEC) that extends vertically. The bottom pad (322) has a wider horizontal width than the MTJ structure (330) and the lower wiring (302), and may be formed in an engraved manner. Accordingly, even if a bottom electrode contact that extends vertically does not exist between the lower wiring (302) and the MTJ structure (330), the lower wiring (302) is not exposed in an etching process (e.g., an IBE process, which will be described in detail in FIG. 9 below) for forming the MTJ structure (330).

In addition, since the lower pad (322) is placed between the lower wiring (302) and the MTJ structure (330), the lower pad (322) can also perform a barrier function to prevent wet chemicals used in an etching process, a cleaning process, etc. from penetrating into the lower wiring (302). The lower pad (322) not only physically separates the lower wiring (302) and the MTJ structure (330) from each other, but can also suppress the penetration of wet chemicals by being composed of an amorphous material such as tantalum (Ta), tantalum nitride (TaN), or tantalum oxide (TaOx).

In the description of FIG. 2 described below, the structure of the lower pad (322) as described above will be described in detail.

FIG. 2 is a cross-sectional view of an embedded cell structure (300) according to one embodiment of the present disclosure.

In the description of Fig. 2, any overlapping parts with the description of Fig. 1 will be omitted, and the description will focus on the configurations not specifically described in the description of Fig. 1.

Referring to FIG. 2, the vertical thickness (h3) of the lower pad (322) may be smaller than the vertical thickness (h4) of the MTJ structure (330). Since the vertical thickness (h3) of the lower pad (322) is implemented to be smaller than the vertical thickness (h4) of the MTJ structure (330), a reduced vertical thickness may be achieved compared to a magnetoresistive memory element including a lower electrode contact (BEC).

In addition, the horizontal width (w2) of the lower surface of the lower pad (322) may be relatively larger than the horizontal width (w4) of the upper surface of the lower pad (322). In addition, the horizontal width (w2) of the lower surface of the lower pad (322) may be relatively larger than the horizontal width (w1) of the cobalt capping layer (310) and the horizontal width of the lower wiring (302). As described above, since the horizontal width (w2) of the lower surface of the lower pad (322) is configured to be larger than the horizontal width (w1) of the cobalt capping layer (310) and the horizontal width of the lower wiring (302), the lower pad (322) may function as a physical barrier for the lower wiring (302).

In addition, the lower pad (322) may include a lower pad structure (322l) and an upper pad structure (322u). Specifically, the lower pad (322) may be divided into a lower pad structure (322l) and an upper pad structure (322u) depending on the shape of the side wall. The upper pad structure (322u) is disposed on the lower pad structure (322l), and the side wall of the upper pad structure (322u) is connected to the side wall of the MTJ structure (330), so that the side wall may be continuous with the shape of the side wall of the MTJ structure (330). On the other hand, the side wall of the lower pad structure (322l) may be discontinuous with the side wall of the MTJ structure (330).

In some embodiments, as illustrated in FIG. 2, the lower pad (322) may have a maximum horizontal width (w3) at the boundary between the upper pad structure (322u) and the lower pad structure (322l).

The maximum horizontal width (w3) of the lower pad (322) may be smaller than the pitch (p) of the lower wiring (302) and larger than the horizontal width (w4) of the lower surface of the MTJ structure (330). Here, the pitch (p) of the lower wiring (302) may refer to the horizontal distance between the centers of two adjacent lower wirings (302) among the plurality of lower wirings (302) (e.g., A1 and A2 of FIG. 2). By implementing the maximum horizontal width (w3) of the lower pad (322) to be smaller than the pitch (p) of the lower wiring (302), a first insulating layer (321) may be disposed between two adjacent lower pads (322), and a phenomenon in which two adjacent lower wirings (302) are electrically connected may be prevented.

The side wall of the upper pad structure (322u) may have a curved slanted structure. The curved slanted structure may have a convex shape in a downward direction, and the side wall of the upper pad structure (322u) may have a rounded shape toward the central axis of the lower pad (322). The upper pad structure (322u) may have a structure in which the horizontal cross-sectional area decreases as it goes upward. Specifically, the side wall of the upper pad structure (322u) may have a slanted structure that moves away from the central axis of the lower pad (322) as it goes downward from the top.

The side wall of the lower pad structure (322l) may have a linear slope structure. That is, the side wall of the lower pad structure (322l) may be sloped at a constant incline. The lower pad structure (322l) may have a structure in which the horizontal cross-sectional area increases as it goes upward. Specifically, the side wall of the lower pad structure (322l) may have a slope structure in which it gets closer to the central axis of the lower pad (322) as it goes downward from the top.

As described above, the sidewall shape of the upper pad structure (322u) and the sidewall shape of the lower pad structure (322l) may be different from each other. This is because the upper pad structure (322u) is the upper structure of the lower pad (322) formed as a result of etching by an etching process (e.g., IBE process) for forming the MTJ structure (330), and the lower pad structure (322l) is the lower structure of the lower pad (322) that has not been etched by the etching process.

In some embodiments, the vertical thickness (h2) of the upper pad structure (322u) may be relatively larger than the vertical thickness (h1) of the lower pad structure (322l). Accordingly, electrical isolation between the plurality of memory structures (MS) may be ensured, and the lower wiring (302) may not be exposed to the etching process.

Specifically, in order to achieve precise electrical isolation between a plurality of memory structures (MS), the etching process (e.g., IBE process) may be performed until a deep recess is formed in the first insulating layer (321) disposed between two adjacent memory structures (MS). Accordingly, the lower pad (322) in contact with the first insulating layer (321) may also be deeply etched by the etching process. Consequently, the vertical thickness (h2) of the upper pad structure (322u), which is a portion of the lower pad (322) etched by the etching process, may be relatively larger than the vertical thickness (h1) of the lower pad structure (322l), which is the remaining portion of the lower pad (322) that is not etched. In addition, since there is a lower pad structure (322l) that is not etched by the above etching process and has a wide horizontal width (w2) of the lower surface, the lower wiring (302) and the cobalt capping layer (310) may not be exposed by the etching process.

In some embodiments, as illustrated in FIG. 2, the sidewall of the upper pad structure (322u) may be surrounded by a protective layer (342), and the sidewall of the lower pad structure (322l) may be surrounded by a first insulating layer (321) and an etch-stop layer (311). The sidewall of the upper pad structure (322u) and the sidewall of the lower pad structure (322l) may be surrounded by the protective layer (342), the first insulating layer (321), and the etch-stop layer (311) made of an insulating material, and electrical isolation between adjacent memory structures (MS) may be ensured.

In the description of FIGS. 3 to 10 described below, the manufacturing method of the above-described magnetoresistive memory element (10) will be described in detail.

FIGS. 3 to 10 are cross-sectional views illustrating a method for manufacturing a magnetoresistive memory element according to one embodiment of the present disclosure.

Referring to FIG. 3, a lower wiring insulation layer (301) may be formed, and a lower wiring (302) penetrating the lower wiring insulation layer (301) may be formed. Here, as described above in FIG. 1, the lower wiring layer including the lower wiring insulation layer (301) and the lower wiring (302) may be the Nth wiring layer (N is a natural number greater than or equal to 1) among a plurality of wiring layers arranged on top of the transistor structure (100 in FIG. 1).

In some embodiments, the lower wiring (302) may be formed in an engraved manner. Specifically, the lower wiring inter-insulating layer (301) may be etched to form an opening penetrating the lower wiring inter-insulating layer (301). A metal material layer (e.g., a copper (Cu) layer) filling the interior of the opening may be formed and planarized to form the lower wiring (302). The planarization process may include a chemical mechanical polishing process (CMP) process. The lower wiring (302) penetrates the lower wiring inter-insulating layer (301), and the upper surface of the lower wiring (302) is formed at the same vertical level as the upper surface of the lower wiring inter-insulating layer (301).

The process of forming a metal material layer inside the above-mentioned opening can be performed based on various processes such as a copper electroplating process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. In addition, the lower wiring insulation layer (301) can be formed based on various processes such as a chemical vapor deposition process, an atomic layer deposition process, or a spin coating process.

Referring to FIG. 4, a cobalt capping layer (310) may be formed on the upper surface of the lower wiring (302). The cobalt capping layer (310) includes cobalt (Co), and the vertical thickness of the cobalt capping layer (310) may be several nm to several tens of nm. The horizontal width of the lower surface of the cobalt capping layer (310) may be substantially the same as the horizontal width of the upper surface of the lower wiring (302).

In some embodiments, the process of forming the cobalt capping layer (310) may be performed based on a selective deposition process. The selective deposition process may refer to a process of depositing cobalt only on the surface of the metal and not depositing cobalt on the surface of the insulating layer. For example, the cobalt capping layer (310) may be formed based on a chemical vapor deposition process or an atomic layer deposition process using a cobalt precursor gas. The cobalt precursor gas may be implemented with various materials containing cobalt (Co) as a component, such as Co(CO) ₄ , _Co2 (CO) ₈ , etc.

In some embodiments, a hydrophobic functional group may be adsorbed onto the upper surface of the lower interconnection insulating layer (301) before the cobalt precursor gas is adsorbed onto the upper surface of the lower interconnection (302). The hydrophobic functional group may be a material having a property of reacting well with the insulating layer and not reacting well with the metal layer. For example, the hydrophobic functional group may be composed of a material such as hexaemthyldisiazane (HMDS). Since the hydrophobic functional group is not adsorbed onto the upper surface of the lower interconnection (302) but is adsorbed only onto the upper surface of the lower interconnection insulating layer (301), the selective deposition characteristics of cobalt may be further enhanced.

Referring to FIG. 5, an etch-stop layer (311) surrounding the upper surface of the lower wiring interlayer insulating layer (301) and the cobalt capping layer (310) may be formed. In addition, a first insulating layer (321) covering the upper surface of the etch-stop layer (311) may be formed.

The lower surface of the etch-stop layer (311) may be arranged at the same vertical level as the lower surface of the cobalt capping layer (310), and the upper surface of the etch-stop layer (311) may be arranged at a higher vertical level than the upper surface of the cobalt capping layer (310). As described above, the etch-stop layer (311) may include a material having a high etching selectivity with respect to the first insulating layer (321).

The lower surface of the first insulating layer (321) may be in contact with the upper surface of the etch-stop layer (311). The vertical thickness of the first insulating layer (321) may be greater than the vertical thickness of the etch-stop layer (311). The first insulating layer (321) may include aluminum nitride, silicon carbide, or a combination thereof. The first insulating layer (321) may be formed based on a chemical vapor deposition process or an atomic layer deposition process.

Referring to FIG. 6, an etching mask (360) can be placed on the upper surface of the first insulating layer (321). Here, the etching mask (360) can include an etching pattern formed through exposure and development.

Next, an opening penetrating the first insulating layer (321) and a portion of the etch-stop layer (311) can be formed through an etching process using an etching mask (360). As illustrated in FIG. 6, the upper surface of the cobalt capping layer (310), a portion of the etch-stop layer (311), and a portion of the first insulating layer (321) can be exposed to the outside through the opening penetrating the first insulating layer (321). The process of forming the opening using the etching mask (360) can be performed based on an etching process such as a reactive ion etching (RIE) process or a plasma etching process.

The lower horizontal width of the opening may be smaller than the upper horizontal width of the opening. Specifically, the side surfaces of the opening may be inclined with respect to the vertical direction. As illustrated in FIG. 6, all side surfaces surrounding the opening may be inclined in a direction that becomes closer to the central axis of the opening as they go from top to bottom. In addition, the horizontal width of the lower surface of the opening may be larger than the horizontal width of the cobalt capping layer (310).

Referring to FIG. 7, the etching mask (360) may be removed and a lower pad (322) may be formed to fill the opening penetrating the first insulating layer (321). The lower pad (322) may cover the upper surface of the first insulating layer (321). The lower pad (322) may include tantalum (Ta), tantalum nitride (TaN), tantalum oxide (TaOx), or a combination thereof. The process of forming the lower pad (322) to fill the opening may be performed based on a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like.

Referring to Fig. 8, the lower pad (322) can be flattened. The upper surface of the flattened lower pad (322) can be placed at the same vertical level as the upper surface of the first insulating layer (321). The flattening process for the lower pad (322) can be performed based on a chemical mechanical polishing process, etc.

As illustrated in FIG. 8, the flattened lower pad (322) may have a lower critical dimension (CD) smaller than an upper critical dimension. In addition, the sidewall of the lower pad (322) may be inclined at a constant incline with respect to the vertical direction. The sidewall of the lower pad (322) may be inclined in a direction that becomes closer to the central axis of the lower pad (322) as it goes from the top to the bottom. The lower pad (322) may cover the upper surface of the cobalt capping layer (310) and may be in contact with the first insulating layer (321) and the etch-stop layer (311).

As described in FIGS. 6 to 8, the lower pad (322) can be formed through an engraving process. The lower pad (322) formed through an engraving process can function as a barrier to prevent the cobalt capping layer (310) and the lower wiring (302) from being exposed during a subsequent etching process.

Referring to Fig. 9, an MTJ structure (330) can be formed on the lower pad (322) and the first insulating layer (321). The MTJ structure (330) can include a sequentially stacked fixed layer (331), a tunnel barrier layer (332), and a free layer (333).

The fixed layer (331) may include a ferromagnetic material such as cobalt, platinum, iron, nickel, etc. In some embodiments, the fixed layer (331) may include an alloy of cobalt and platinum, or may have a composite layer structure in which cobalt films and platinum films are alternately laminated. The tunnel barrier layer (332) may include, for example, magnesium oxide or aluminum oxide. The free layer (333) may include, for example, a ferromagnetic material such as cobalt, platinum, iron, nickel, etc.

The fixed layer (331), the tunnel barrier layer (332), and the free layer (333) may be sequentially formed on the first insulating layer (321) and the lower pad (322). The process of forming the fixed layer (331), the tunnel barrier layer (332), and the free layer (333) may be performed based on a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like. Here, the vertical thickness of the MTJ structure (330) may be greater than the vertical thickness of the lower pad (322).

Next, an MTJ etching mask (370) may be placed on top of the free layer (333). The MTJ etching mask (370) may be an etching mask provided for etching the MTJ structure (330). In some embodiments, the MTJ etching mask (370) may include the same material as the etching mask (360) of FIG. 6 described above. In another embodiment, the MTJ etching mask (370) is a metal hard mask provided for the etching process of the MTJ structure (330), and after performing the etching process, may be implemented as the upper pad (341) of FIG. 1.

The MTJ etch mask (370) may be arranged in an aligned state with respect to the lower pad (322). In one embodiment, the MTJ etch mask (370) may be aligned so that the central axis of the MTJ etch mask (370) and the central axis of the lower pad (322) have the same horizontal coordinate. In this case, the central axes of the lower wiring (302), the cobalt capping layer (310), the lower pad (322), and the MTJ etch mask (370) may all be aligned to the same horizontal coordinate.

Referring to FIG. 10, an etching process of an MTJ structure (330) may be performed using an MTJ etching mask (370). The etched MTJ structure (330) may have a lower critical dimension that is larger than an upper critical dimension. Specifically, the sidewall of the MTJ structure (330) may be inclined at a constant slope with respect to the vertical direction. The sidewall of the MTJ structure (330) may be inclined in a direction away from the central axis of the MTJ structure (330) as it goes down from the top to the bottom. The etching process may be performed based on an ion beam etching (IBE) process.

Here, the ion beam etching process is a physical etching process that utilizes ionized inert gases. Furthermore, unlike plasma etching and reactive ion etching, the ion beam etching process does not utilize neutral species (e.g., radicals) or electrons.

Due to the ion beam etching process, the fixed layer (331), the tunnel barrier layer (332), the free layer (333), the first insulating layer (321), and the lower pad (322) of FIG. 9 can be etched. As illustrated in FIG. 10, a deep recess can be formed on the outside of the MTJ structure (330). Specifically, a recess can be formed on each of the right and left sides of the MTJ structure (330). The recess formed on the right side of the MTJ structure (330) and the recess formed on the left side of the MTJ structure (330) can have shapes that are symmetrical with respect to the central axis of the MTJ structure (330). In addition, although not illustrated in detail in FIG. 10, the recesses formed on the left and right sides of the MTJ structure (330) have a structure that is connected to each other and can surround the MTJ structure (330).

As described above, even when a deep recess is formed due to the ion beam etching process, whereby most of the first insulating layer (321) is removed, the lower pad (322) is positioned on the lower side of the MTJ structure (330) and has a wider horizontal width than the MTJ structure (330) and the lower wiring (302), so that the lower wiring (302) may not be exposed to the ion beam etching process.

FIG. 11 is a cross-sectional view of an embedded cell structure (300) according to one embodiment of the present disclosure.

Returning to FIG. 9, the ion beam etching process may be performed with the MTJ etching mask (370) misaligned with respect to the lower pad (322). In this case, referring to FIG. 11, the central axis of the MTJ structure (330) and the central axis of the lower wiring (302) may be located at different horizontal coordinates.

When misalignment occurs, as illustrated in FIG. 11, the two side walls of the lower pad (322a) may be implemented in different shapes. The first side wall (322sw-1) of the lower pad (322a) may have a larger proportion of rounded side wall portions, and the second side wall (322sw-2) of the lower pad (322a) may have a larger proportion of straight side wall portions. Here, the first side wall (322sw-1) may be one side wall that is relatively farther away from the MTJ structure (330) than the second side wall (322sw-2). Conversely, the second side wall (322sw-2) may be one side wall that is relatively closer to the MTJ structure (330) than the first side wall (322sw-1).

Even when misalignment occurs, the lower wiring (302), cobalt capping layer (310), lower pad (322a), and MTJ structure (330) can have a sequentially stacked structure. In this case, the lower pad (322a) can completely cover the upper surface of the lower wiring (302), and the lower wiring (302) can not be exposed to the ion beam etching process. Accordingly, defects in the lower wiring (302) can be prevented.

As described above, the magnetoresistive memory element (10) according to one embodiment of the present disclosure can prevent physical and chemical damage that may be applied to the lower wiring (302), and can have a reduced circuit line width and element thickness.

While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary. Those skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

10: Magnetoresistive memory device
100: Transistor structure 200: Cell transistor
300: Embedded cell structure 301: Lower wiring insulation layer
302: Lower wiring 310: Cobalt capping layer
311: Etch stop layer 321: First insulating layer
322, 322a: Lower pad 330: MTJ structure
341: Top pad 342: Protective layer
350: Second insulation layer 400: Bit line
MS: Memory Structure

Claims (10)

A memory structure disposed between an upper wiring layer and a lower wiring layer; and
A cobalt capping layer disposed between the lower wiring included in the lower wiring layer and the memory structure;
The above memory structure,
A lower pad that is in contact with the upper surface of the cobalt capping layer and has a lower surface having a horizontal width wider than the horizontal width of the upper surface of the cobalt capping layer; and
An MTJ structure disposed on the upper surface of the lower pad;
The horizontal width of the upper surface of the above lower pad is the same as the horizontal width of the lower surface of the above MTJ structure,
The horizontal width of the lower surface of the above cobalt capping layer is the same as the horizontal width of the upper surface of the above lower wiring,
A magnetoresistive memory element, wherein the upper wiring layer and the lower wiring layer are two wiring layers arranged adjacent to each other among a plurality of wiring layers arranged on the upper portion of a transistor structure. In the first paragraph,
The above lower pad comprises tantalum (Ta), tantalum nitride (TaN), tantalum oxide (TaOx) or a combination thereof,
A magnetoresistive memory element wherein the vertical thickness of the lower pad is smaller than the vertical thickness of the MTJ structure. In the first paragraph,
The maximum horizontal width of the above lower pad is greater than the maximum horizontal width of the above MTJ structure,
The maximum horizontal width of the lower pad is smaller than the pitch of the lower wiring,
A magnetoresistive memory element in which the pitch of the lower wiring is the horizontal distance between the centers of two adjacent lower wirings among a plurality of lower wirings included in the lower wiring layer. In the first paragraph,
The above lower pad includes an upper pad structure having a side wall of a curved slope structure and a lower pad structure having a side wall of a straight slope structure,
A magnetoresistive memory element in which the upper pad structure is disposed on the lower pad structure. In paragraph 4,
A magnetoresistive memory element in which the vertical thickness of the upper pad structure is greater than or equal to the vertical "??* thickness of the lower pad structure. In paragraph 4,
The above upper pad structure has a horizontal cross-sectional area that decreases as it goes upward,
The above lower pad structure is a magnetoresistive memory element in which the horizontal cross-sectional area increases as it goes upward. In paragraph 6,
A magnetoresistive memory element wherein the upper pad structure includes a side wall rounded toward the central axis of the lower pad. In paragraph 4,
A protective layer surrounding the side walls of the above memory structure;
A first insulating layer disposed between the protective layer and the lower wiring layer; and
Further comprising a second insulating layer formed at a relatively higher vertical level than the first insulating layer, surrounding the protective layer;
The side wall of the above upper pad structure is surrounded by the above protective layer,
A magnetoresistive memory element, wherein the side wall of the lower pad structure is surrounded by the first insulating layer. In paragraph 8,
A magnetoresistive memory element, wherein the first insulating layer comprises aluminum nitride (AlN), silicon carbide (SiC), or a combination thereof. In the first paragraph,
A magnetoresistive memory device, wherein the cobalt capping layer is formed based on selective deposition on the upper surface of the lower wiring.