KR20250132417A - Semiconductor design method for extrapolation-free characterization and computing system performing the same - Google Patents

Abstract

A semiconductor design method includes a step of performing timing analysis based on a Liberty file extracted from a gate level netlist and parasitic element information generated from a layout design to determine whether extrapolation exists, and when the extrapolation exists, modifying parameters of a basic timing table of the Liberty file and performing characterization based on the modified parameters to generate a modified timing table.

Description

Semiconductor design method for extrapolation-free characterization and computing system performing the same

The present invention relates to integrated circuit design technology, and more particularly, to a semiconductor design method for characterization free from extrapolation and a computing system performing the same.

In general, circuits of semiconductor devices are designed using a digital design method, and engineers can design various logics using EDA (Electronic Design Automation) software. In order to efficiently design various logics, the EDA software may designate unit logic circuits such as NAND, NOR, OR, AND, inverter, and FLIP-FLOP as standard cells, and may include a timing table and/or a liberty file that characterize the standard cells. The timing table may be a simulation result that measures the output transition timing and propagation delay of the standard cell while changing the input slope of an input signal input to the standard cell and the output capacitance of the standard cell. A plurality of timing tables for a plurality of standard cells may be stored in a cell library of the EDA software.

When designing an Application Specific Integrated Circuit (ASIC), design rule constraints may be strictly observed. For example, the maximum capacitance value when n standard cells having the largest capacitance among the plurality of standard cells are provided may be set as a design rule, and the design of a logic circuit having a fanout exceeding the maximum capacitance value may be prohibited. Since non-memory chips such as ASICs are designed under the limitations of the above design rule constraints, extrapolation may not occur even if static timing analysis is performed on the results of combining timing tables existing in the cell library. However, during the process of placing and routing a digitally designed chip, extrapolation may occur in which the capacitance value of the actual design is greater than the capacitance value of the capacitance stored in the timing table due to the resistive-capacitive (RC) value of the metal line. Furthermore, because memory chips, such as DRAM, are designed in a fully custom manner without design rule constraints, there may be instances where the input slope of an input signal listed in the timing table is less than the minimum value or the output capacitance is greater than the maximum value. Therefore, performing static timing analysis using only the combination of timing tables stored in the cell library can lead to problems that prevent proper design verification.

An embodiment of the present invention can provide a semiconductor design method and a computing system that can perform timing analysis based on a basic timing table for a standard cell and parasitic element information of a layout design, and update the basic timing table with a corrected timing table when extrapolation exists.

An embodiment of the present invention can provide a semiconductor design method capable of generating a correction timing table that is free from extrapolation and performing design verification based on the correction timing table, and a computing system for performing the same.

A semiconductor design method according to an embodiment of the present invention may include: a step of performing timing analysis based on a liberty file of a standard cell extracted from a gate level netlist and parasitic element information generated from a layout design to determine whether extrapolation exists; when the extrapolation exists, a step of modifying parameters of a basic timing table of the liberty file to set parameters of a modified timing table, performing characterization based on the parameters of the modified timing table to generate the modified timing table, and updating the basic timing table of the liberty file with the modified timing table; and a step of performing timing verification using the liberty file including the modified timing table.

A computing system according to an embodiment of the present invention may include a memory for storing standard cell information, a gate level net list, and a layout design, and loading a timing analysis tool; and a processor for executing the timing analysis tool. The timing analysis tool may determine whether extrapolation exists by utilizing a liberty file of a standard cell and parasitic element information of the layout design, and, when extrapolation exists, modify parameters of the basic timing table of the liberty file, perform characterization based on the modified parameters, and generate a modified timing table, and update the basic timing table with the modified timing table.

An embodiment of the present invention can improve the consistency between the timing analysis result by a timing analysis tool and the timing analysis result by electrical simulation, thereby increasing the efficiency of semiconductor design verification and reducing the semiconductor design verification time.

FIG. 1 is a diagram schematically showing the configuration of a timing analysis system according to an embodiment of the present invention.
FIG. 2 is a diagram showing a standard cell and a timing table of the standard cell according to an embodiment of the present invention.
Figure 3a is a graph showing the difference between the actual output transition timing and the predicted output transition timing when extrapolation related to the input slope occurs.
Figure 3b is a graph showing the difference between the actual output transition timing and the predicted output transition timing when extrapolation related to the output capacitance occurs.
Figure 4 is a flowchart showing a design method of a semiconductor device according to an embodiment of the present invention.
Figure 5 is a diagram showing the connection between a standard cell and a full custom logic block.
FIG. 6 is a flowchart showing more specifically a method of setting parameters of a modification timing table among design methods according to an embodiment of the present invention.
FIG. 7a and FIG. 7b are graphs showing the distribution of the actual effective capacitance of a specific standard cell and a method for setting parameters of a modified timing table.
FIG. 8 is a diagram showing the configuration of a computing system according to an embodiment of the present invention.

FIG. 1 is a diagram schematically showing the configuration of a timing analysis system (100) according to an embodiment of the present invention. Referring to FIG. 1, the timing analysis system (100) may include a design information medium (110), a cell library (120), and a timing analysis tool (130). The design information medium (110) may store various semiconductor design information. For example, the semiconductor design information may include standard cell information, a gate-level netlist, and parasitic element information of a layout design. The gate-level netlist may be generated from a schematic design. The schematic design may be a circuit diagram that graphically represents circuit connections of transistors and/or logic gates. In the schematic design, all connections of transistors identical to those of standard cells are detected, and the gate-level netlist may be generated by expressing the connections of transistors identical to those of the standard cells as logic gate circuits. For example, a transistor level netlist may be extracted from the schematic design, and the transistor level netlist may be converted into the gate level netlist. The gate level netlist may be generated using a specific tool. The specific tool may be a commercial tool or an in-house tool having different characteristics for each semiconductor manufacturing company. The specific tool may convert the schematic design into the transistor level netlist, and then convert the transistor level netlist into the gate level netlist. Parasitic element information of the layout design may include resistance and capacitance (RC) information of all nodes and/or logic pins present in the layout design. The parasitic element information may be a Standard Parasitic Exchange Format (SPEF) generated from the layout design using a commercial tool such as StarRC®. The design information medium may provide the standard cell information, the gate level netlist, and the parasitic element information to the timing analysis tool (130) upon request of the timing analysis tool.

The cell library (120) can store a plurality of standard cells and a plurality of liberty files, each of which is associated with a plurality of standard cells. The liberty file may correspond to a result of performing characterization on a specific standard cell and may include a basic timing table. For example, the basic timing table may include propagation delay times and/or output transition timings of the standard cell for various values of input slope and output capacitance. The basic timing table may be a lookup table that sets the input slope and the output capacitance as parameters and includes the results of measuring the propagation delay times and/or output transition timings of the standard cell through an electrical simulation, such as a spice simulation. The cell library (120) receives a request from the timing analysis tool (130) and provides a liberty file for a specific standard cell to the timing analysis tool (130). The cell library (120) may store not only liberty files for the plurality of standard cells but also liberty files for a plurality of custom cells. The standard cell is a logic block that is basically used in the design of various semiconductor chips, and may include, for example, an inverter, various logic gates, flip-flops, multiplexers, etc. The cell library (120) basically stores a liberty file for the standard cell and may be provided together with a digital design tool such as EDA software. The custom cell is a logic block that is only used in a specific semiconductor chip designed using a custom design method, and may include, for example, a pass gate, a switch, a differential logic, etc. The liberty file for the custom cell may be generated through characterization by the electrical simulation according to the designer's intention, and the designer may store the liberty file for the custom cell together with the liberty file for the standard cell in the cell library (120). Custom cell information related to the custom cell may be stored in the design information medium (110).

The timing analysis tool (130) may receive various design information from the design information medium (110) and may receive Liberty files related to a plurality of standard cells from the cell library (120) to perform timing analysis. When an extrapolation exists in the timing analysis result, the timing analysis tool (130) may re-perform characterization for a specific standard cell and modify a Liberty file related to the specific standard cell. The timing analysis tool (130) may include a timing analysis engine (131) and a Liberty modification engine (132).

The timing analysis engine (131) can perform timing analysis based on the gate level netlist received from the design information medium (110) and parasitic element information of the layout design. The timing analysis engine (131) can receive the plurality of Liberty files for each of the plurality of standard cells included in the gate level netlist from the cell library (120). The timing analysis engine (130) can perform static timing analysis to generate actual effective slopes and actual effective capacitances of input nodes and output nodes of each of the plurality of standard cells. The timing analysis engine (131) can include PrimeTime® or Tempus® as a commercial tool capable of performing the static timing analysis. The timing analysis engine (131) can compare the input slope and the output capacitance described in the basic timing table of the Liberty file with the actual effective slope and the actual effective capacitance generated by the timing analysis to determine whether extrapolation exists. For example, the timing analysis engine (131) may determine that the extrapolation exists when the actual effective slope is less than the minimum value of the input slope or the actual effective slope is greater than the maximum value of the input slope. The timing analysis engine (131) may determine that the extrapolation exists when the actual effective capacitance is less than the minimum value of the output capacitance or the actual effective capacitance is greater than the maximum value of the output capacitance. The timing analysis engine (131) may provide the result of determining whether the extrapolation exists to the liberty correction engine (132).

The Liberty correction engine (132) may receive a determination result as to whether the extrapolation exists from the timing analysis engine (131). When the extrapolation does not exist in the timing analysis result by the timing analysis engine (131), the Liberty correction engine (132) may not modify the Liberty file related to the standard cell, and the parameters described in the basic timing table included in the Liberty file may be maintained. When the extrapolation exists in the timing analysis result by the timing analysis engine (131), the Liberty correction engine (132) may determine whether to modify the Liberty file related to the standard cell. The Liberty correction engine (132) may selectively modify the basic timing table by considering the number of times extrapolation has occurred for one type of standard cell, the values of the actual effective slope and the actual effective capacitance corresponding to the extrapolation. The Liberty correction engine (132) can change at least one of the minimum value of the input slope, the maximum value of the input slope, the minimum value of the output capacitance, and the maximum value of the output capacitance described in the basic timing table, and can modify parameters of the basic timing table. The Liberty correction engine (132) can set the modified parameter as a parameter of the modified timing table, and perform characterization on the standard cell to generate the modified timing table. The modified timing table can include output transition timing for the newly set values of the input slope and output capacitance. The Liberty correction engine (132) can modify the Liberty file by providing the modified timing table to the cell library (120) and updating the basic timing table of the Liberty file stored in the cell library (120) with the modified timing table. Thereafter, when design verification is performed on the standard cell, the Liberty file including the modified timing table can be utilized.

FIG. 2 is a diagram showing a standard cell and a timing table of the standard cell according to an embodiment of the present invention. Referring to FIG. 2, the standard cell (200) may be an inverter. The standard cell (200) may be characterized through the electrical simulation, and the characterization result may be stored as the timing table (220). The Liberty file stored in the cell library (120) illustrated in FIG. 1 may include the timing table (220). The timing table (220) may be an m-to-n lookup table, and may be expressed in the form of an 8X8 matrix, for example. The rows of the timing table (220) may include parameters (S1-Sm) from a minimum value of an input slope (S) of an input signal (IN) applied to an input node of the standard cell (210) to a maximum value of the input slope (S). The columns of the timing table (220) may include parameters (CE1-CEn) from the minimum value of the output capacitance (CE) of the output node (ON) of the standard cell (210) to the maximum value of the output capacitance (CE). The timing table (220) may include various types of delay parameters, such as a rising delay time, a falling delay time, or a transition delay time of the standard cell, which are determined according to the input slope (S) and the output capacitance (CE). For example, the delay parameter may be an output transition timing (T) of an output signal (OUT) output through the standard cell (210). The timing table may include parameters (T11-Tnm) of m*n output transition timings. The parameters (S1-Sm) between the minimum value of the input slope (S) and the maximum value of the input slope (S) may have equally divided values, or may have values having critical significance when the electrical simulation is performed. In one embodiment, the parameters may be a mixture of equally divided values and values having critical significance. Similarly, the parameters (CE1-CEn) between the minimum value of the output capacitance (CE) and the maximum value of the output capacitance (CE) may have equally divided values, or may have values having critical significance, or may be a mixture of the equally divided values and values having critical significance.

For example, the first output transition timing (T11) may represent the output transition timing (T) of the output signal (OUT) outputted through the standard cell (210) when the standard cell (210) provides an input slope (S1) having a first value (minimum value) and is connected to a network that provides an output capacitance (CE1) having the first value (minimum value). The second output transition timing (T22) may represent the output transition timing (T) of the output signal (OUT) outputted through the standard cell (210) when the standard cell (210) provides an input slope (S2) having a second value and is connected to a network that provides an output capacitance (CE) having the second value. The above third transition timing (Tnm) may represent the output transition timing (T) of the output signal (OUT) output through the standard cell (210) when the standard cell (210) is connected to a network that provides an input slope (Sm) having an m-th value (maximum value) and provides an output capacitance (CEn) having an n-th value (maximum value).

The timing analysis tool (130) can predict and calculate the output transition timing (T) of the output signal (OUT) by interpolation or extrapolation when the actual effective slope is not equal to the parameters (S1-Sm) of the input slope described in the timing table (210). The timing analysis tool (130) can predict and calculate the output transition timing (T) of the output signal (OUT) by interpolation or extrapolation when the actual effective capacitance is not equal to the parameters (CE1, CE2-CEn) of the output capacitance described in the timing table (210). However, the output transition timing (T) predicted by the extrapolation may include a larger error than the transition timing predicted by the interpolation.

Fig. 3a is a graph showing the difference between the actual output transition timing and the predicted output transition timing when extrapolation related to the input slope occurs. In Fig. 3a, the horizontal axis of the graph may be the magnitude of the input slope, and the vertical axis of the graph may be the output transition timing and/or propagation delay time. S_min may be the minimum value of the input slope described in the timing table related to a specific standard cell (e.g., S1 in Fig. 2), and S_max may be the maximum value of the input slope described in the timing table related to a specific standard cell (e.g., Sm in Fig. 2). The bold line may represent the output transition timing and/or propagation delay time generated through the electrical simulation based on the parameters of the input slope. The dashed line is a trend line indicating the trend of the change in the output transition timing, and may be, for example, a straight line or a curve connecting the value of the output transition timing by the minimum value (S_min) of the input slope and the value of the output transition timing by the maximum value (S_max) of the input slope. When interpolation related to the input slope occurs during timing analysis for the standard cell, the timing analysis tool (130) calculates an approximate value on the trend line as a predicted value of the output transition timing, and the predicted value of the output transition timing may not have a large difference from the actual value. When extrapolation related to the input slope occurs during timing analysis for the standard cell, the timing analysis tool (130) may extend the trend line to calculate the predicted value of the output transition timing. However, when the actual value of the output transition timing changes as in the dashed line, a significant difference may occur between the actual value of the output transition timing and the predicted value by the timing analysis tool (130). The difference between the predicted value and the actual value of the above output transition timing may reduce the reliability of the timing analysis and/or timing verification results performed using the timing analysis tool (130), and may reduce the consistency between the electrical simulation results and the timing verification results using the timing analysis tool (130).

Fig. 3b is a graph showing the difference between the actual transition timing and the predicted transition timing when extrapolation related to the output capacitance occurs. In Fig. 3b, the horizontal axis of the graph may be the magnitude of the output capacitance (CE), and the vertical axis of the graph may be the output transition timing and/or propagation delay time. CE_min may be the minimum value of the output capacitance described in the timing table of a specific standard cell (e.g., CE1 in Fig. 2), and CE_max may be the maximum value of the output capacitance described in the timing table of a specific standard cell (e.g., CEn in Fig. 2). The bold line may represent the output transition timing and/or propagation delay time generated through the electrical simulation based on the parameters of the output capacitance. The dashed line is a trend line representing the change in the output transition timing in a straight line, and may be, for example, a straight line connecting the value of the output transition timing by the minimum value (CE_min) of the output capacitance and the value of the output transition timing by the maximum value of the output capacitance. When interpolation related to the output capacitance occurs during timing analysis for the standard cell, the timing analysis tool (130) calculates an approximate value on the trend line as a predicted value of the output transition timing, and the predicted value of the output transition timing may not have a large difference from the actual value. When extrapolation related to the output capacitance occurs during timing analysis for the standard cell, the timing analysis tool (130) may extend the trend line to calculate the predicted value of the output transition timing. However, when the actual value of the output transition timing changes as in the dotted line, a significant difference may occur between the actual value of the output transition timing and the predicted value by the timing analysis tool (130). The difference between the predicted value and the actual value of the above output transition timing may lower the reliability of the timing analysis and/or timing verification results performed using the timing analysis tool (130), and may reduce the consistency between the timing analysis results by the electrical simulation and the timing verification results by the timing analysis tool.

The timing analysis tool (130) can perform timing verification of a semiconductor design in a shorter time than the electrical simulation. However, if there is a lack of consistency between the timing verification result of the timing analysis tool (130) and the timing verification result of the electrical simulation, the timing verification using the timing analysis tool cannot be utilized. In particular, in the design process of a semiconductor device that is manufactured through a full custom design method without being restricted by design rule constraints, the extrapolation inevitably occurs. Therefore, in order to shorten the timing verification time of a semiconductor design by using the timing analysis tool (130) and to improve the consistency between the timing verification result by the timing analysis tool (130) and the timing verification result by the electrical simulation, it may be necessary to modify a timing table that may include the extrapolation.

FIG. 4 is a flowchart illustrating a method for designing a semiconductor device according to an embodiment of the present invention. Referring to FIG. 4, at S301, a schematic design may be performed by a designer. The designer may perform the schematic design by drawing a transistor-level circuit diagram. At S301, the designer may first draw a transistor-level logic block that can be configured with standard cells. At S302, the schematic design composed of the standard cells may be converted into a gate-level netlist. The gate-level netlist may be stored in the design information medium (110) illustrated in FIG. 1. At S303, a layout design may be performed using the schematic design. The layout design may be performed by designing a full custom logic block that cannot be configured with standard cells or custom cells, and then electrically connecting the full custom logic block with the standard cells and the custom cells. At S304, parasitic element information for the layout design may be generated. Resistance and capacitance (RC) information of all nodes and/or logic pins present in the above layout design can be generated as the parasitic element information. The parasitic element information can be stored in the design information medium (110) illustrated in FIG. 1. In S305, standard cell information present in the gate level netlist can be extracted, and liberty files related to the standard cells can be extracted. For example, the timing analysis tool (130) illustrated in FIG. 1 can extract various types of standard cell information and custom cell information from the gate level netlist stored in the design information medium (110), and read liberty files related to each of the various types of standard cells and custom cells from the cell library (120).

At S306, timing analysis can be performed based on the Liberty file and the parasitic element information. The timing analysis tool (130) can perform timing analysis by utilizing the basic timing table included in the Liberty file and the parasitic element information to generate the actual effective capacitance of the input node of the various types of standard cells and the actual effective slope of the output node of the standard cell. At S307, whether extrapolation exists can be determined. The timing analysis tool (130) can determine whether extrapolation exists by comparing the input slope and the output capacitance described in the basic timing table of the Liberty file related to the standard cell with the actual effective capacitance and the actual effective slope.

FIG. 5 is a diagram showing a connection relationship between a standard cell and a full custom logic block. Referring to FIG. 5 together, the full custom logic block (410) may be connected between a first standard cell (420) and a second standard cell (430) as a result of the layout design. For example, the first standard cell (420) may be an inverter, and an output node (ON1) of the first standard cell (420) may be connected to an input terminal of the full custom logic block (410). The second standard cell (430) may be a NAND gate, and an input node (IN2) of the second standard cell (430) may be connected to an output terminal of the full custom logic block (410). The timing analysis tool (130) can generate a value of the actual effective capacitance of the output node (ON1) of the first standard cell (420) connected to the input terminal of the full custom logic block (410), and can generate a value of the actual effective slope of the input node (IN2) of the second standard cell (430) connected to the output terminal of the full custom logic block (410).

The timing analysis tool (130) can determine whether extrapolation exists by comparing the output capacitance described in the basic timing table related to the first standard cell (420) with the actual effective capacitance of the output node (ON1). If the actual effective capacitance has a value between the minimum value and the maximum value of the output capacitance described in the basic timing table, it can be determined that the extrapolation did not occur. If the actual effective capacitance is smaller than the minimum value of the output capacitance described in the basic timing table or greater than the maximum value of the output capacitance, it can be determined that the extrapolation occurred. Thereafter, the timing analysis tool (130) can determine whether extrapolation exists by comparing the input slope described in the basic timing table of the Liberty file related to the second standard cell (430) with the actual effective slope of the input node (IN2). If the actual effective slope has a value between the minimum and maximum values of the input slopes described in the basic timing table, it may be determined that the extrapolation does not exist. If the actual effective slope is less than the minimum value of the input slope described in the basic timing table or greater than the maximum value of the input slope, it may be determined that the extrapolation exists.

The timing analysis tool (130) can extract information related to all standard cells existing in the layout design from the gate level netlist. The standard cell information can include the type of standard cell and the total number of standard cells of each type. The timing analysis tool (130) can determine whether extrapolation exists for each type of standard cell. If there are 100 types of standard cells in the gate level netlist, the timing analysis tool (130) can sequentially determine whether extrapolation exists in the 100 types of standard cells.

When it is determined that the extrapolation does not exist (when the result of S307 is "No"), in S308, the parameters of the basic timing table of the Liberty file related to the standard cell may not be changed, and the basic timing table may be maintained as is. When it is determined that the extrapolation exists (when the result of S307 is "Yes"), in S309, the parameters of the basic timing table may be modified to set the parameters of the modified timing table. When the timing analysis result indicates that the extrapolation has occurred, the timing analysis tool (130) may set the minimum and maximum values of the modified timing table based on the actual effective capacitance and the actual effective slope corresponding to the extrapolation.

For example, if the actual effective capacitance of the first output node (ON1) is smaller than the minimum value of the output capacitance described in the basic timing table associated with the first standard cell (420), the minimum value of the output capacitance of the modified timing table may be set to the value of the actual effective capacitance. Conversely, if the actual effective capacitance of the first output node (ON1) is larger than the maximum value of the output capacitance described in the basic timing table associated with the first standard cell (420), the maximum value of the output capacitance of the modified timing table may be set to the value of the actual effective capacitance. Parameters between the minimum value and the maximum value of the output capacitance of the modified timing table may be set by evenly dividing the values between the minimum value and the maximum value of the actual effective capacitance, or may be set based on a distribution of the actual effective capacitance values.

In addition, if the actual effective slope of the second input node (IN2) is less than the minimum value of the input slope described in the basic timing table related to the second standard cell, the minimum value of the input slope of the modified timing table may be set to the value of the actual effective slope. Conversely, if the actual effective slope of the second input node (IN2) is greater than the maximum value of the input slope described in the basic timing table related to the second standard cell (430), the maximum value of the input slope of the modified timing table may be set to the value of the actual effective slope. The parameters between the minimum value and the maximum value of the input slope of the modified timing table may be set by evenly dividing the values between the minimum value and the maximum value of the actual effective slope, or may be set based on the distribution of the actual effective slope values.

In S310, the modified timing table may be generated by performing characterization based on the parameters of the modified timing table. The timing analysis tool (130) may perform characterization on the first standard cell based on the parameters of the modified timing table set in S309. The timing analysis tool (130) may calculate an output transition timing for the modified parameters through the electrical simulation and generate the modified timing table in which the output transition timing is described. The timing analysis tool (130) may provide the modified timing table to the cell library (120) to modify the liberty file related to the first standard cell (420). The basic timing table may be replaced with the modified timing table, and the liberty file related to the first standard cell (420) may include the modified timing table. Thereafter, when the timing analysis tool (130) reads the Liberty file for the first standard cell (420), the Liberty file including the modified timing table can be provided to the timing analysis tool (130).

Similarly, the timing analysis tool (130) can set parameters of a modified timing table for the second standard cell (430) and perform characterization of the second standard cell based on the parameters of the modified timing table. The output transition timing for the modified parameters can be calculated through the electrical simulation and a modified timing table in which the output transition timing is described can be generated. The timing analysis tool (130) can provide the modified timing table to the cell library (120) to modify a liberty file related to the second standard cell (430). The basic timing table is replaced with the modified timing table, and the liberty file related to the second standard cell (430) can include the modified timing table. Thereafter, when the timing analysis tool (130) reads the liberty file for the second standard cell (430), the liberty file including the modified timing table can be provided to the timing analysis tool (130). Thereafter, when the timing analysis tool reads the Liberty file for the second standard cell (430), the Liberty file including the modified timing table can be provided to the timing analysis tool.

In S311, timing analysis can be performed using a Liberty file that is free from extrapolation. The timing analysis tool (130) can perform timing verification for a semiconductor design using Liberty files associated with a plurality of standard cells. Through S306 to S310, the basic timing table of a standard cell in which extrapolation occurred can be replaced with a modified timing table, and the basic timing table of a standard cell in which extrapolation did not occur can be maintained. Accordingly, all Liberty files stored in the cell library (120) can be free from extrapolation. For example, assume that there is no extrapolation in the timing analysis result associated with the first standard cell, and there is extrapolation in the timing analysis result associated with the second standard cell. Through S308 to S310, the Liberty file associated with the first standard cell will include the basic timing table, and the Liberty file associated with the second standard cell will include the modified timing table. All of the Liberty files related to the first and second standard cells may be free from extrapolation, and the timing analysis results of the timing analysis tool (130) performed based on the Liberty files free from extrapolation may have high consistency with the timing analysis results through the electrical simulation.

FIG. 6 is a flowchart showing in more detail a method of setting parameters of a modified timing table among design methods according to an embodiment of the present invention. The method illustrated in FIG. 6 can be performed through the timing analysis tool (130) and the Liberty correction engine (132) illustrated in FIG. 1. The timing analysis tool (130) and the Liberty correction engine (132) can set parameters of the modified timing table by a statistical method. Referring to FIG. 6, in S401, the values of the actual effective slope of the input node of the standard cell and the actual effective capacitance of the output node of the standard cell can be loaded. For example, when the layout design includes 100 "first standard cells," the values of the actual effective slope and the values of the actual effective capacitance related to the 100 "first standard cells" can be loaded. In S402, data preprocessing can be performed. In the above data preprocessing process, missing values and noise can be removed. In step S403, it can be determined whether the distribution of the values of the actual effective slope for which the data preprocessing has been completed and the distribution of the values of the actual effective capacitance for which the data preprocessing has been completed are normal distributions. In step S403, a normality test such as the Shapiro-Wilk test or the Kolmogorov-Smirnov test can be performed to determine the distribution of the values of the actual effective slope or the values of the actual effective capacitance.

When the distribution of the values of the actual effective slope or the values of the actual effective capacitance is determined to be a normal distribution (when the result of S402 is “Yes”), an outlier of the normal distribution can be identified in S404. For example, but not limited to, a method for identifying an outlier of the normal distribution may include at least one of a sigma value utilization method, a Z-Score utilization method, and a T-Score utilization method. The sigma value utilization method may set a threshold by calculating the average and standard deviation of the values of the actual effective slope or the values of the actual effective capacitance, and then identify values of the actual effective slope or the actual effective capacitance exceeding the threshold sigma value as outliers. The above Z-Score utilization method can calculate the average, standard deviation and Z-score of the values of the actual effective slope or the values of the actual effective capacitance, set a threshold Z-Score value, and then identify the values of the actual effective slope or the actual effective capacitance that exceed the threshold Z-Score value as abnormal values. The above T-Score utilization method can calculate the average, standard deviation and T-Score of the values of the actual effective slope or the values of the actual effective capacitance, set a threshold T-Score value, and then identify the values of the actual effective slope or the actual effective capacitance that exceed the threshold T-Score value as abnormal values.

When the distribution of the values of the actual effective slope or the values of the actual effective capacitance is determined to be non-normally distributed (when the result of S402 is “No”), an outlier of the non-normal distribution can be identified in S405. For example, but not limited to, a method for identifying an outlier of the non-normal distribution can include at least one of a robust standardization method and a density-based method. The robust standardization method can calculate the median and interquartile range (IQR) of the values of the actual effective slope or the values of the actual effective capacitance and set a threshold range value, and then identify the values of the actual effective slope or the values of the actual effective capacitance that exceed the threshold range value as outliers. The density-based method calculates the density of the values of the actual effective slope or the values of the actual effective capacitance through Kernel Density Estimation (KDE), sets a critical density value, and then identifies the values of the actual effective slope or the actual effective capacitance having a density lower than the critical density value as outliers.

When outliers are identified through S404 and S405, it may be determined in S406 whether the number of the identified outliers is less than or equal to a threshold ratio. The threshold ratio may be a percentage of the number of outliers among the total values of the actual effective slope or the actual effective capacitance. For example, but not limited to, the threshold ratio may be 5%, but the threshold ratio may vary depending on the designer's intention. When the identified outliers are greater than or equal to the threshold ratio (when the result of S406 is "No"), the threshold value condition may be relaxed in S407. For example, in the sigma value utilization method, the Z-Score utilization method, and the T-Score utilization method, the threshold sigma value, the threshold Z-Score value, and the threshold T-Score value may each be changed. A threshold value associated with a minimum value distribution may be decreased, and a threshold value associated with a maximum value distribution may be increased. Additionally, in the robust standardization method, the interquartile range can be increased, and in the density-based method, the critical density value can be decreased. After relaxing the threshold condition in S406, S403, S404, S405, and S406 can be performed again. In S406, the threshold condition can be gradually relaxed until the number of identified outliers becomes less than or equal to the threshold ratio.

When the identified abnormal value is less than or equal to the threshold ratio (when the result of S406 is “Yes”), in S408, a minimum value of the values of the actual effective slope or the actual effective capacitance in which the identified abnormal value is excluded or in which at least one of the identified abnormal values is included may be set as a minimum value of the correction timing table, and a maximum value of the actual effective slope or the actual effective capacitance in which the identified abnormal value is excluded or in which at least one of the identified abnormal values is included may be set as a maximum value of the correction timing table. In S409, parameters between the minimum value and the maximum value of the correction timing table may be set. In one embodiment, the parameters between the minimum value and the maximum value of the correction timing table may be set to values that are evenly divided between the minimum value and the maximum value. In one embodiment, the parameters between the minimum value and the maximum value may be set to values having critical significance (e.g., having a relatively high density) among the values between the minimum value and the maximum value.

FIGS. 7A and 7B are graphs showing the distribution of the actual effective capacitance of a specific standard cell and a method for setting parameters of a modified timing table. The step (S309) of modifying the timing table illustrated in FIG. 4 will be described in more detail with reference to FIGS. 1, 2, 4, 7A and 7B as follows. The timing analysis tool (130) and the Liberty correction engine (132) can set parameters of the modified timing table through statistical analysis. The timing analysis tool (130) and the Liberty correction engine (132) can identify outliers and reduce the number of outliers through any one of various statistical analysis methods according to the distribution of the actual effective capacitance values. The timing analysis tool (130) and the Liberty correction engine (132) can set the minimum or maximum value of the actual effective capacitance values from which the abnormal values are excluded as the minimum or maximum value of the correction timing table when the number of abnormal values among the actual effective capacitance values corresponding to the extrapolation is less than or equal to the threshold ratio.

The horizontal axis of the graphs of FIGS. 7A and 7B may be the value of the actual effective capacitance of the input node of the specific standard cell, and the vertical axis may be the frequency at which the value of the actual effective capacitance occurs. As illustrated in FIG. 7A, when an extrapolation occurs in which the values of the actual effective capacitance are greater than the maximum value of the output capacitance of the basic timing table, the threshold condition may be sequentially relaxed to CrA, CrB, CrC, and CrD until the number of abnormal values becomes less than or equal to a threshold ratio. When the threshold condition is set to CrD, the number of abnormal values may become less than or equal to the threshold ratio, and the values of the actual effective capacitance identified as abnormal values by the threshold value may be excluded. Among the values of the actual effective capacitance from which the abnormal values are excluded, the maximum value (S_max_new) may be set to the maximum value (NCE8) of the modified timing table. Since no extrapolation smaller than the minimum value (CE_min) of the output capacitance of the basic timing table has occurred, the minimum value (CE_min) of the output capacitance described in the basic timing table can be set to the minimum value (NCE1) of the modified timing table. As illustrated in FIG. 7A, when the distribution of the values of the actual effective capacitance is not diverse, the remaining parameters (NCE2, NCE3, NCE4, NCE5, NCE6, NCE7) of the modified timing table can be set by evenly dividing the values between the minimum value (NCE1) and the maximum value (NCE8). In one embodiment, the remaining parameters (NCE2, NCE3, NCE4, NCE5, NCE6, NCE7) of the constantly modified timing table may not have evenly divided values, and may have values at points where a plurality of actual effective capacitances are distributed. For example, the parameters (NCE2, NCE3, NCE4, NCE5) of the above-described modified timing table can be set by evenly dividing the actual capacitance value corresponding to the distribution adjacent to the minimum value (NCE1), and the parameters (NCE6, NCE7) of the above-described modified timing table can be set by evenly dividing the actual effective capacitance value corresponding to the distribution adjacent to the maximum value (NCE2).

As illustrated in FIG. 7B, when an extrapolation occurs in which the values of the actual effective capacitance are greater than the maximum value of the output capacitance of the basic timing table, the threshold condition may be sequentially relaxed to CrA, CrB, and CrC until the number of abnormal values becomes less than or equal to a threshold ratio. When the threshold condition is set to CrC, the number of abnormal values may become less than or equal to the threshold ratio, and the values of the actual effective capacitance identified as abnormal values by the threshold value may be excluded. Among the values of the actual effective capacitance from which the abnormal values are excluded, the maximum value (S_max_new) may be set to the maximum value (NCE8) of the modified timing table. Since an extrapolation less than the minimum value (CE_min) of the output capacitance of the basic timing table has not occurred, the minimum value (CE_min) of the output capacitance described in the basic timing table may be set to the minimum value (NCE1) of the modified timing table. As illustrated in FIG. 7b, when the distribution of the values of the actual effective slope is diverse, the values of the actual effective capacitance at points having a critical significance between the minimum value (NCE1) and the maximum value (NCE8) may be set to the remaining parameters (NCE2, NCE3, NCE4, NCE5, NCE6, NCE7) of the modified timing table. The remaining parameters (NCE2, NCE3, NCE4, NCE5, NCE6, NCE7) may each be set to the actual effective capacitance values at points where a relatively large number of frequencies are distributed, and may not have an equal difference. Although FIG. 7b exemplarily describes setting the parameters of the modified timing table based on the actual effective slope or the actual effective capacitance excluding all of the identified abnormal values, some or all of the identified abnormal values may be considered to set the parameters of the modified timing table. Among the above-identified abnormal values, abnormal values that have critical significance or meet design requirements are not excluded and can be utilized to set the parameters of the above-mentioned modified timing table.

In FIGS. 7A and 7B, only the method of modifying the maximum value of the output capacitance when an extrapolation in which the actual effective capacitance is greater than the maximum value of the output capacitance occurs has been described, but the minimum value of the output capacitance, the minimum value of the input slope, and the maximum value of the input slope may also be modified by the same principle. In addition, the method of setting the parameters of the modified timing table is not limited to the exemplified FIGS. 7A and 7B, and may be modified and changed by various statistical analysis methods. For example, the parameters between the minimum and maximum values may be set by formulating numerical values such as the mean, variance, and standard deviation that can be extracted from the values of the actual effective capacitance. In addition, a model capable of minimizing errors from the electrical simulation may be developed by utilizing machine learning or an algorithm to set the optimal minimum value, the optimal maximum value, and the parameters between the optimal minimum and maximum values.

FIG. 8 is a diagram showing the configuration of a computing system (500) according to an embodiment of the present invention. The computer system (500) may include a processor (510), a network interface (520), an input/output device (530), storage (540), memory (550), and a bus (501). The bus (501) may interconnect the processor (510), the network interface (520), the input/output device (530), the storage (540), and the memory (550). The processor (510) may execute program instructions to load the timing analysis tool (130) illustrated in FIG. 1 into the memory and execute the timing analysis engine (131) and the Liberty correction engine (132) of the timing analysis tool (130) so as to perform a design method according to an embodiment of the present invention. The timing analysis tool (130) may be configured to perform steps S305 to S311 illustrated in FIG. 4.

The above network interface (520) may be configured to access program instructions and data accessed by program instructions stored remotely via a network (not shown).

The input/output device (530) may include input devices and output devices configured to enable interaction between the computing system (500) and the designer. For example, the input devices may include, for example, a keyboard, a mouse, and other devices, and the output devices may include, for example, a display, a printer, and other devices.

The storage (540) is configured to store program instructions and data accessed by the program instructions. For example, the storage (540) includes a non-transitory computer-readable storage medium, such as a flash memory, a magnetic disk, an optical disk, or the like. The storage (540) can load the timing analysis tool (130) illustrated in FIG. 1 into the memory (540) based on the program instructions of the processor (510). In addition, the storage (540) can store the gate-level netlist and the parasitic element information illustrated in FIG. 1 as the design information, and store the liberty file of the standard cell as the cell library. The storage (540) can load the gate-level netlist, the parasitic element information, the standard cell information, and the liberty file of the standard cell into the memory based on the program instructions of the processor (510).

The memory (550) is configured to store program instructions executed by the processor (510) and data accessed by the program instructions. For example, the memory (550) includes any combination of random access memory (RAM), other volatile storage devices, read-only memory (ROM), and other non-volatile storage devices.

Those skilled in the art should understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential characteristics thereof, and therefore, the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the claims below rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be interpreted as being included within the scope of the present invention.

Claims (12)

A step of performing timing analysis based on the liberty file of the standard cell extracted from the gate level netlist and the parasitic element information generated from the layout design to determine whether extrapolation exists;
When the extrapolation exists, a step of modifying the parameters of the basic timing table included in the Liberty file to set the parameters of the modified timing table, performing characterization based on the parameters of the modified timing table to generate the modified timing table, and updating the basic timing table of the Liberty file with the modified timing table; and
A semiconductor design method comprising the step of performing timing verification using the Liberty file including the modified timing table. In the first paragraph,
The step of determining whether the above extrapolation exists comprises the steps of comparing the input slope described in the basic timing table with the actual effective slope of the input node of the standard cell,
A semiconductor design method comprising a step of comparing the output capacitance described in the above basic timing table with the actual effective capacitance of the output node of the standard cell. In the second paragraph,
A semiconductor design method, wherein the step of comparing the input slope described in the basic timing table with the actual effective slope of the input node of the standard cell determines that the extrapolation exists when the actual effective slope is less than the minimum value of the input slope and when the actual effective slope is greater than the maximum value of the input slope. In the second paragraph,
A semiconductor design method, wherein the step of comparing the output capacitance described in the basic timing table with the actual effective capacitance of the output node of the standard cell determines that the extrapolation exists when the actual effective capacitance is less than the minimum value of the output capacitance and when the actual effective capacitance is greater than the maximum value of the output capacitance. In the first paragraph,
A semiconductor design method in which the parameters of the above-mentioned modified timing table are set based on a statistical analysis of the actual effective slope of the input node of the standard cell and the actual effective capacitance of the output node of the standard cell. In paragraph 5,
A semiconductor design method for setting parameters of the above-described correction timing table, wherein the step of setting parameters of the above-described correction timing table comprises: excluding at least one abnormal value from among values of the actual effective capacitance; setting the minimum or maximum value of the actual effective capacitance from which the at least one abnormal value has been excluded as a new minimum or maximum value of the output capacitance; and equally dividing values between the new minimum value and the new maximum value to set parameters of the above-described correction timing table. In paragraph 5,
A semiconductor design method in which the step of setting the parameters of the above-mentioned correction timing table comprises: excluding at least one abnormal value from among the values of the actual effective capacitance, setting the minimum or maximum value of the actual effective capacitance from which the at least one abnormal value has been excluded as a new minimum or maximum value of the output capacitance, and setting a value having a critical significance between the new minimum value and the new maximum value based on a distribution of the actual effective capacitance as a parameter of the above-mentioned correction timing table. In paragraph 5,
A semiconductor design method for setting parameters of the above-described correction timing table, wherein the step of setting parameters of the above-described correction timing table comprises: excluding at least one abnormal value from among the values of the actual effective slope, setting the minimum or maximum value of the actual effective slope from which the at least one abnormal value has been excluded as a new minimum or maximum value of the output capacitance, and evenly dividing values between the new minimum value and the new maximum value to set parameters of the above-described correction timing table. In paragraph 5,
A semiconductor design method in which the step of setting the parameters of the above-mentioned modified timing table comprises: excluding at least one abnormal value from among the values of the actual effective slope, setting the minimum or maximum value of the actual effective slope from which the at least one abnormal value has been excluded as a new minimum or maximum value of the input slope, and setting a value having a critical significance between the new minimum value and the new maximum value based on a distribution of the actual effective slope as a parameter of the above-mentioned modified timing table. In the first paragraph,
The above characterization is a semiconductor design method for calculating output transition timing by performing electrical simulation based on parameters of the above modified timing table. In the first paragraph,
Before the step of performing the above timing analysis to determine whether extrapolation exists,
A step of performing schematic design and performing layout design based on the schematic design;
A step of converting the schematic design into the gate level netlist and extracting standard cell information and Liberty files related to the standard cell from the gate level netlist; and
A semiconductor design method further comprising a step of extracting parasitic element information of the layout design. Memory for storing standard cell information, gate-level netlists and layout designs, and loading timing analysis tools; and
comprising a processor that executes the timing analysis tool;
A computing system in which the timing analysis tool determines whether extrapolation exists by utilizing the liberty file of the standard cell and the parasitic element information of the layout design, modifies the parameters of the basic timing table of the liberty file when extrapolation exists, performs characterization based on the modified parameters, and generates a modified timing table, and updates the basic timing table with the modified timing table.