KR910003163B1 - Floppy Disk Controller - Google Patents

Abstract

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Description

Floppy Disk Controller

1 is a functional block diagram of the present invention.

2 is a block diagram of an embodiment of the present invention.

3 is a block diagram showing a specific configuration of a microprocessor of the present invention.

4A is a flowchart of step processing according to the present invention.

4B is a flowchart of a timer assignment process according to the present invention.

5A, 5B and 5C show the relationship between the step pulse and the drive clock according to the present invention.

6 is a diagram for explaining movement (at low speed) of the head carriage in the embodiment of the present invention.

7 is a configuration diagram of a step motor.

8 is a driving pulse waveform diagram of a step motor.

9A, 9B, and 9C are diagrams showing a relationship between a step pulse and a driving clock according to a conventional method.

10 is a diagram for explaining the movement (at high speed) of the conventional head carriage.

11 is a diagram for explaining the movement (at low speed) of a conventional head carriage.

Although a step motor is used for the movement of the head of the floppy disk device, a resonance of the carrier occurs due to the movement step plate, and unnecessary sounds are generated at the time of seek. According to the present invention, the head is moved by controlling the clock for driving the step motor by the step rate of the step pulse applied to the floppy disk device. According to the present invention, a floppy disk control device capable of smoothly moving the head and preventing the generation of unnecessary sounds is possible.

The present invention relates to a floppy disk device, and more particularly to a floppy disk control device for controlling the movement of the head.

Floppy disk devices are small storage devices, but are inexpensive and compact and are used in various devices such as personal computers and word processors.

Floppy disk devices typically rotate diskettes (recording media) and store data in tracks set on concentric circles. Data reading and writing are generally performed in track units or in selector units provided in a plurality of tracks. The heads are moved and set at a desired track position for writing or reading. For example, when a sector in a track that stores desired data is read out, the head is moved to a track position where the sector is installed and then read out.

The movement of the above-mentioned head is conventionally performed such that, for example, as shown in FIGS. 7 to 9, a step motor having a four-phase with respect to one rotation and a pulse for driving control thereof are used, and for example, move by one track for two phases. The rotation is converted to a straight line. That is, FIG. 7 is a schematic diagram of a step motor. 8 is a pulse waveform for driving control of a step motor. In the drawing, 10-13 is a step motor coil for stator excitation wound around each stator, and 14 is rotated by an excitation action of each coil 10-13. The stop position of the rotor 14 engaged with the head is shown. The diagonal lines of (10)-(13) are the sections in which driving current flows through the coils 10-13, and 15 is the head movement pulse applied to the step motor driver from the floppy disk controller through the receiver in the floppy disk device. 16 indicates a step pulse and is a drive clock set in the step motor driver in the floppy disk device in response to the step pulse, and switching of the energization section to each coil 10-13 is performed by the timing of the clock. .

The step motor controls the energization sections 10 and 13 of the coils 10-13 sequentially so that the rotor 14 rotates a predetermined number of times to move the head. Stops and the head is positioned at a predetermined track position.

The floppy disk controller, which controls the floppy disk device, moves the step pulse driver 15 of the movement at a predetermined period t ₁ to move the target track having the circuit which generates the step pulse 15 for moving the above-mentioned head. Is putting on. In response to the step pulse, the step motor driver sets the drive clock 16 at a constant period t ₂ to drive the step motor to move the head.

By the way, the pulse period t ₁ so-called step rate of step pulse 15 differs depending on the type of floppy disk controller, and there are about 20 or more kinds of step rates t ₁ currently used, such as 3 msec, 4 msec, 6 msec, 10 msec, and 20 msec.

When the above-mentioned conventional head is moved and in other words controlled by the head seek step motor, the step motor driver sets the period T ₂ of the drive clock 16 of the step motor so that the step motor 15 can respond to the step pulse 15 of the highest speed rate t ₁ . there was. Therefore, when the step rate was slow, the head carriage was not uniformly fed and the head carriage was resonating. 9 is a diagram showing the relationship between the step pulse 15 and the drive clock 16 in the high speed mode (A), the medium speed mode (B), and the low speed mode (C). 10 is a diagram showing a movement of a conventional head carriage at high speed. 11 is a diagram showing the movement of the carriage of the conventional head at low speed. In the 10th and 11th degrees, the horizontal axis represents time, the vertical axis represents the carriage movement amount, the solid line represents the target movement position by the drive clock 16 (signal for rotating the pulse motor 1/4), and the dotted line represents the actual movement amount of the head carriage. .

As described above, in the conventional floppy disk device, as shown in FIG. 9A, the period t ₂ of the drive clock 16 of the step motor (for example, ₁ msec) can be responded to the step pulse 15 of the fast step rate t ₁ (for example, 3 msec). ), The driving of the step motor becomes constant, and as shown in FIG. 10, the movement of the head carriage smoothly changes with time. Medium staff rate t _'1 (e.g. 6msec) or low speed staff rate t _"1 (e.g. 10msec), particularly when the low speed the cycle driving clock 16 of t ₂ as high speed when, and for two consecutive times, then the staff pulse 15 The drive clock 16 is not applied until it is applied, and when the step pulse 15 is applied, the drive clock 16 is repeatedly repeated two times. As a result, the step motor is repeatedly driven (rotated) and stopped. It resonated like the 0 of the dotted line part.

The above-mentioned resonance has caused a problem that noise is generated, that is, noise and noise occurs whenever the head is moved.

An object of the present invention is to provide a floppy disk control device which smoothly moves the head and prevents the occurrence of unnecessary sound, even in the case of a fast or low step rate, in view of the above-mentioned drawbacks.

1 is a functional block diagram of the present invention. 1 is a floppy disk controller, which generates a step pulse, generates a control signal for reading or writing data, and drives the floppy disk device. 2 is a step rate determining means and determines the time interval of the head pulse pulse step pulses applied from the controller 1 of the floppy disk. Reference numeral 3 is a head moving means for moving the head corresponding to the time interval with the drive clock of the step motor as a result of the step plate discriminating means.

In addition, the step plate discriminating means 2 and the head moving means 3 are provided inside the floppy disk device.

Floppy disk controller 1 applies a head movement pulse to the floppy disk device to move the head to the desired track. The head moving pulses vary depending on the type of floppy disk controller 1, and the step rate determining means 2 obtains the time interval of the head moving pulses (step pulses) applied from the floppy disk controller 1. The time interval to be obtained is, for example, three stages of high speed, normal (medium speed), and low speed, and the step rate discriminating means determines which stage the applied head moving pulse is at, and applies the result to the head moving means 3. The head moving means 3 drives the step motor and moves the head at a corresponding speed, for example, by three steps of speed control, i.e., a drive clock.

If the head is moved at a speed of more than three types, the movement of the head is particularly smooth, and unnecessary head carriage resonance does not occur.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 2 is a block diagram of an embodiment of the present invention. The floppy disk controller 1 is a circuit that controls the floppy disk device 4 and writes or reads data. Naturally, a control signal relating to this writing and reading is applied from the floppy disk controller 1 to the floppy disk device 4. This control signal is applied to microprocessor 6 via receiver 5 in floppy disk device 4. The receiver 5 is a circuit which controls whether or not to insert the above-mentioned signal from the floppy disk controller 1, and is applied when the drive selection signal applied from the floppy disk controller 1 matches the value already set. The control signal is outputted to the microprocessor 6 in which the control signal is embedded.

The microprocessor 6 is a circuit which performs various kinds of control by the control signal applied through the receiver 5, and as shown in the circuit block of FIG. 3, a read-only memory in which a program for controlling the change of the step plate is stored ( ROM 61 and an output port 62 for outputting signals to the step motor driver 7, and a random access memory (RAM) 63 in the work area used in the above-described program 61. In addition, the microprocessor 6 sets a timer for changing the step plates 15 of the floppy disk controller input through the receiver 5 and the latch plates 64, 65, and step pulse 15 for holding the selection signal in the rotation direction for a predetermined time. 66, with a central processing unit 67 to control each function block 61-66.

The central processing unit 67 controls the set and reset of the step pulse 15 to the latches 64 and 65 and the rotation direction selection signal via the control line 68, and when these signals are set to the latches 64 and 65, the inputs are assigned from the latches 64 and 65. A signal is inputted to the central processing unit 67 via the control line 69 to read the step pulse 15 and the like.

The central processing unit 67 controls the timer start and stop of the timer 66 via the control line 70. When the timer 66 reaches the set time, the allocation request signal is input from the timer 66 to the central processing unit 67 via the control line 71. .

In addition, the control transmits the set time signal from the central processing unit 67 to the timer 66 (TA, TB, TC, TD described later) and the transfer of the specified set time signal from the timer 66 to the central processing unit 67. It is done via.

The central processing unit 67 also controls the program 61, the RAM 63 and the output port 62 via the control line 72, and reads the stored program in the program 61 to the central processing unit 67 via the data bus 74. Then, as described in FIGS. 4A and 4B, in accordance with the step processing by the program, the central processing unit 67 determines the step rate of the step pulse 15, and controls the timer 66 in response to the determination result and sets the designated time. By using this method, a drive clock having a predetermined pulse interval is created, and the drive clock is temporarily stored in the RAM 63 and written to the output port 62. The drive clock is sent to the step motor driver 7 from the output port 62, and the step motor driver 7 drives the step motor 8 at the timing of the drive clock. Thus, the control program moves the head to the desired track, reads the data, writes data, and inputs data to an external circuit. Although the circuits of the embodiment of the present invention of Figs. 2 and 3 are described, other writing and reading circuits are not directly related to the present invention and are omitted for the sake of brevity of explanation.

When a step pulse is applied to the microprocessor 6 via the receiver 5 to read the desired data from the floppy disk controller 1, the microprocessor 6 applies a step signal corresponding to the step pulse to the step motor driver 7. The step motor driver 7 drives and rotates the step motor 8 in synchronization with the step signal. Although not shown, the step motor 8 and the head carriage 9 (the head is installed) are mechanically connected, and the head carriage 9 moves linearly with the head on each track in the diskette in response to the rotation of the step motor.

The present invention relates to the movement of the head described above. 4A is a flowchart of step processing when a step pulse is applied to the microprocessor 6. FIG.

In the embodiment of the present invention, three kinds of movement speed control are performed on the step pulse. For example, when the first step pulse is applied, firstly, determination processing S1 of whether or not in high speed mode is performed. In the high speed mode Y, the first internal step S2 is executed. The first internal step is a process for rotating the clock by one clock with respect to the step motor. In the embodiment of the present invention, the step motor is rotated 1/4 clockwise to 1 clock and 2 clocks in other words to move one track in two phases. In the first internal step in the process S2, it is a process of making a quarter turn (for 1/2 track) outward or inward from the stationary position, that is, the position on the track. Next, the process 3 which sets to high speed mode is performed. Since discrimination is made in discrimination S1 as the high speed mode, this process S3 is insignificant at this time, but is effective also when a step pulse corresponding to the high speed mode is applied from the state of the normal mode or the low speed mode as described later. After the process S3, the timer setting (TA) process S4 is performed, and the process waits until this TA timeout. After the TA time elapses, the second internal step processing S5 is performed, and a quarter turn of the second step motor is performed for one step pulse. By this process S5, it becomes a target rotation amount. Next, the timer assignment set processing (after the TD time) S6 and the timer assignment flag set processing S7 are performed to finish the processing for the first step pulse. In the case of the high speed mode, the next step pulse is applied slightly earlier than the Td time set in the timer assignment set process S6, so that the above-described processes S1, S2, S3, S4, S5, S6, and S7 are repeated in sequence. By this repetition, in the high speed mode, a time of T / A is given between the first quarter rotation of the first motor and the quarter rotation of the second motor and driven.

On the other hand, when the applied step pulse is not in the high speed mode, the timer assignment occurs after the completion of the above-described processes S1-S7 and the timer assignment processing is performed. In the above-mentioned timer assignment set, when the processing S6 is executed again within the TD time, no allocation occurs, but in the high speed mode, no allocation occurs in the high speed mode because a pulse is applied after the TD time elapses after the second internal step. Otherwise, an assignment process is performed.

4B is a flowchart of the timer assignment process.

Processing of FIG. 4B is performed by assignment of a timer. First, a determination process ST1 is performed to determine whether the current mode is the high speed mode. In the high speed mode (Y), the reset process ST2 in the high speed mode is performed. As described above, since no allocation occurs in the high speed mode, the reset processing ST2 resets the high speed mode to assume that the high speed mode is not the high speed mode. In addition, the mode becomes the normal mode by resetting the high speed mode.

Then, the internal step processing ST3, followed by the timer assignment set processing (TD) ST4 is performed. Timer assignment processing (TD) ST4 is a processing for generating a next assignment when no step pulse is applied within the next TD time. For example, when the head is moved to the desired position and the step pulse is not applied, timer assignment is generated again and timer assignment processing is executed again. Then, it is determined that the high speed mode is not the high speed mode (N) (the high speed mode is reset in the process ST2 of the previous timer assignment processing). Then, it is determined whether the timer allocation flag is set, that is, whether it is ON. Since the timer assignment flag is set in the step S7 of step processing in FIG. 4A, ON is determined (Y), and then the assignment set (TE) process ST6 and the timer assignment flag OFF process ST7 are performed to complete the assignment process. do. In the setting time of the processing ST6, the TE time is, for example, 20 msec or the like, which is much longer than the setting time of the step processing. This is a means for detecting that the movement of the head is completed. In other words, when the TE time step pulse is not applied, the timer assignment process is executed again. In the assignment at this time, of course, the timer assignment flag is OFF (it is turned OFF in the above-described process ST7). In the switching process ST9, the power is switched to the step motor stop. The step motor has a stop torque even if no voltage is applied, but a voltage lower than the voltage at the time of rotation is applied to the pulse motor to achieve the desired stop torque. This not only prevents unnecessary power consumption but also prevents heat generation.

Again, the description will return to FIG. 4A. When it is determined in the discrimination processing S1 that it is not in the high speed mode (N), it is next determined whether or not it is in the low speed mode. In the low speed mode, first, the process of setting to the low speed mode is performed. This processing S9 is the same as the setting in the high speed mode. Then, the first internal step processing S10 and the timer setting (TB) processing S11 are performed. The time in the timer setting process S11 at this time is a time for performing the second internal step process S5 in the low speed mode, for example, 4 msec. After that, the processes S5, S6, and S7 are performed as described above.

On the other hand, when it is not the high speed mode or the low speed mode, it is determined whether or not the timer assignment flag is set next. If it is not set, the process from S14 is started because it is the first step process of head movement. If it is set, this step processing determines whether the time T from the previous step processing (set at the same time as the timer assignment set processing) is greater than the specific time T ₁ . When not greater than the specific time T ₁ (N), since the step pulse is applied again in a short time, the process is performed in the high speed mode at this time, and the process starts from the above-described process S3. When it is larger than the specific time T ₁ (Y), it is determined whether it is larger than the specific time T ₂ or not. If it is larger than the specified time T ₂ (Y), the next step pulse is applied in reverse to the above-described high speed mode, so that the process starts from the above-described process S9 of setting to the above-described low speed mode.

When the time T is not greater than T ₂ (in this case, T ₁ < T < T ₂ ), the normal mode is set, and the first internal staff S15 and timer setting (TC) processing S16 are performed. At this time, the timer setting time is TC and is an intermediate value between the high speed mode and the low speed mode. For example, when TA is 1.5 msec and TB is 4 msec, TC is 3 msec. After the setting processing, the above-described second internal step S5 is executed.

In the embodiment of the present invention, the stop mode is neither the high speed mode nor the low speed mode. This is because the high speed mode and the low speed mode are reset by the processing ST1 and the processing ST8 when the step pulse is not applied. That is, this state is the normal mode, and when the power is turned on. That is, when it is determined that the comparison between the time T and the specific time T ₁ , T ₂ described above is smaller than T ₁ (N in process S12), it is determined that the high speed mode is set in process S3 and is larger than T ₂ (Y in process S13). Is set to the low speed mode in S9. For this reason, these processes S3 and S9 are needed.

FIG. 5 shows the relationship between step pulse 15 and drive clock 16 given by the step processing in FIGS. 4A and 4B, where (A) is a high speed mode, (B) is a normal mode, and (C) is a low speed mode.

6 is a diagram for explaining the movement (lowering) of the head carriage in the embodiment of the present invention. In addition, the horizontal axis represents time, the vertical axis represents the movement amount, the solid line represents the target movement position by the step pulse, and the dotted line represents the actual movement amount of the head carriage.

In the embodiment of the present invention, since the step motor is driven to divide the carriage into three types of high speed, low speed, and normal speed, the movement is smooth. That is, at low speed, the movement as shown in FIG. 6 (... part) and at high speed, as shown in FIG. 10, the smooth movement as in the prior art and the smooth movement at the normal speed are achieved.

As mentioned above, although demonstrated using the Example of this invention, this invention does not limit the kind of movement of a step motor to three types. For example, even four or more types are possible in the East, and smoother movement is possible by increasing the type.

As described above, the present invention controls the clock of the pulse motor in response to the step pulse applied from the controller of the floppy disk. According to the present invention, the head moves smoothly in the fast step plate and the late step plate. It is possible to obtain a control device of the floppy disk which prevented the occurrence.

Claims (3)

In the floppy disk apparatus, the step plate discriminating means (2) for determining the time interval of the head moving pulses applied from the floppy disk controller (1), and the step motor for moving the head based on the result of the discriminating means (2). And a head moving means (3) for moving the head by changing the drive clock corresponding to the time interval. The step plate discriminating means comprises a processor circuit having an allotment timer, and the floppy according to claim 1, wherein the time interval of the head movement pulse is determined by an assignment to the processor circuit by the timer. Disk Control. 2. The floppy disk control apparatus according to claim 1, wherein the step plate discriminating means discriminates the time interval of the head moving pulses into at least three types of time intervals of high speed, medium speed, and low speed.

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