[go: up one dir, main page]

KR920010764A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
KR920010764A
KR920010764A KR1019900017987A KR900017987A KR920010764A KR 920010764 A KR920010764 A KR 920010764A KR 1019900017987 A KR1019900017987 A KR 1019900017987A KR 900017987 A KR900017987 A KR 900017987A KR 920010764 A KR920010764 A KR 920010764A
Authority
KR
South Korea
Prior art keywords
manufacturing
semiconductor device
film
metal film
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1019900017987A
Other languages
Korean (ko)
Inventor
이규필
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019900017987A priority Critical patent/KR920010764A/en
Publication of KR920010764A publication Critical patent/KR920010764A/en
Abandoned legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음No content

Description

반도체 소자의 제조방법Manufacturing method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2(a)-(b)도는 본 발명의 일실시예에 따른 제조공정도.2 (a)-(b) is a manufacturing process diagram according to an embodiment of the present invention.

Claims (7)

반도체 소자의 제조방법에 있어서, 반도체 기판상에 소정의 두께로 층간절연막과 금속막을 차례로 형성하고 상기 금속막 상부에 포토레지스터 패턴을 형성하는 제1공정과, 상기 포토레이스터 패턴을 사용하는 상기 금속막을 소정의 두께로 등방성 식각하는 제2공정과, 상기 포토레이스터 패턴은 그대로 사용하여 이방성 시각을 하여 층간절연막을 노출시키는 제3공정과, 상기 반도체 기판 전면에 걸쳐 보호막을 형성하는 제4공정이 연속적으로 이루어짐을 특징으로 하는 반도체 소자의 제조방법.1. A method of manufacturing a semiconductor device, comprising: a first step of sequentially forming an interlayer insulating film and a metal film on a semiconductor substrate at a predetermined thickness, and forming a photoresist pattern on the metal film; and the metal using the photoraster pattern A second step of isotropically etching the film to a predetermined thickness, a third step of exposing the interlayer insulating film by anisotropic viewing using the photoraster pattern as it is, and a fourth step of forming a protective film over the entire surface of the semiconductor substrate. A method for manufacturing a semiconductor device, characterized in that it is made continuously. 제1항에 있어서, 상기 금속막이 하나의 층 또는 둘 이상의 층으로 됨을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the metal film is formed of one layer or two or more layers. 제1항에 있어서, 상기 보호막이 하나의 층 또는 둘 이상의 층을 형성하는 반도체 소자의 제조방법.The method of claim 1, wherein the passivation layer forms one layer or two or more layers. 제1항에 있어서, 상기 층간절연막과 금속막의 두께가 각각 2000Å-1.0μm와 500Å-1.0μm임을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the thicknesses of the interlayer insulating film and the metal film are 2000 k? -1.0 [mu] m and 500 k? -1.0 [mu] m, respectively. 제1항에 있어서, 상기 금속라인 사이의 간격이 1.0μm이하임을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein an interval between the metal lines is 1.0 μm or less. 제1항에 있어서, 상기 등방성 식각을 함에 있어서, 인산(H2PO4)과 질산(HNO3)과 초산(CH3COOH)과 물(H2O)을 각각 16대 1대 1대 2로 혼합하여 6000Å/min의 식각율로 상기 금속막을 2000Å-4000Å정도의 두께로 식각함을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein in the isotropic etching, phosphoric acid (H 2 PO 4 ), nitric acid (HNO 3 ), acetic acid (CH 3 COOH), and water (H 2 O) are 16 to 1 to 1 to 2, respectively. And mixing the metal film to a thickness of about 2000 kPa-4000 kPa with an etching rate of 6000 kV / min. 제1항에 있어서, 상기 이방성 식각을 함에 있어서 150SCCM의 Bcl3가스, 50SCCM cl2가스 그리고 20SCCM의 CHF3가스를 300mT 압력하에서 약 200V의 파워를 사용하여 층간절연막을 노출시킬 때까지 금속막을 1150Å/min의 식각율로 식각함을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein in the anisotropic etching, the metal film is exposed until the interlayer insulating film is exposed using 150 CCM of B c l 3 gas, 50 SCCM cl 2 gas, and 20 SCCM CHF 3 gas at a pressure of about 200 V at 300 mT pressure. A method of manufacturing a semiconductor device, characterized by etching at an etching rate of 1150 Å / min. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900017987A 1990-11-07 1990-11-07 Manufacturing method of semiconductor device Abandoned KR920010764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900017987A KR920010764A (en) 1990-11-07 1990-11-07 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900017987A KR920010764A (en) 1990-11-07 1990-11-07 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
KR920010764A true KR920010764A (en) 1992-06-27

Family

ID=67738905

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900017987A Abandoned KR920010764A (en) 1990-11-07 1990-11-07 Manufacturing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR920010764A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100455723B1 (en) * 2001-09-13 2004-11-12 주식회사 하이닉스반도체 mehtod for manufacturing bit line

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100455723B1 (en) * 2001-09-13 2004-11-12 주식회사 하이닉스반도체 mehtod for manufacturing bit line

Similar Documents

Publication Publication Date Title
JPS57176746A (en) Semiconductor integrated circuit and manufacture thereof
JPS63304644A (en) Method of forming via-hole
KR920010764A (en) Manufacturing method of semiconductor device
KR19990063182A (en) Etching method
JPS5569264A (en) Etching method
JPS5495185A (en) Production of semiconductor device
KR960026585A (en) Method for manufacturing device isolation oxide film of semiconductor device
JP3225676B2 (en) Method for manufacturing semiconductor device
KR100259071B1 (en) Etching methods for semiconductor material
KR970023732A (en) Method for forming contact hole in semiconductor device
JP2760426B2 (en) Dry etching method for resist film
KR950021107A (en) How to Form Contact Holes
JPS57176742A (en) Semiconductor device and manufacture thereof
JP3143949B2 (en) Dry etching method
JP2872298B2 (en) Method for manufacturing semiconductor device
KR960019488A (en) Wiring pattern formation method of semiconductor device
JP2983543B2 (en) Electrode formation method
JP2994644B2 (en) Electrode formation method
JP2907599B2 (en) Method of forming wiring layer
KR940003565B1 (en) Metal wiring method for semiconductor device
JPS55130140A (en) Fabricating method of semiconductor device
KR970053409A (en) Device Separation Method of Semiconductor Device
KR970018200A (en) Interlayer insulating layer planarization method
JPS57106151A (en) Semiconductor device
KR940016878A (en) Method for forming self-aligned contact of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19901107

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19901107

Comment text: Request for Examination of Application

PG1501 Laying open of application
PC1902 Submission of document of abandonment before decision of registration
SUBM Surrender of laid-open application requested