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KR920013476A - 반도체 집적회로 - Google Patents

반도체 집적회로 Download PDF

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Publication number
KR920013476A
KR920013476A KR1019910023915A KR910023915A KR920013476A KR 920013476 A KR920013476 A KR 920013476A KR 1019910023915 A KR1019910023915 A KR 1019910023915A KR 910023915 A KR910023915 A KR 910023915A KR 920013476 A KR920013476 A KR 920013476A
Authority
KR
South Korea
Prior art keywords
address
memory block
scan signal
semiconductor integrated
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
KR1019910023915A
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English (en)
Other versions
KR960000346B1 (ko
Inventor
가즈타카 노가미
츠카사 시로토리
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로 일렉트로닉스 가부시키가이샤
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Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로 일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR920013476A publication Critical patent/KR920013476A/ko
Application granted granted Critical
Publication of KR960000346B1 publication Critical patent/KR960000346B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

내용 없음

Description

반도체 직접회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 반도체 집적회로의 일부를 나타낸 블럭도, 제2도는 제1도에 나타낸 반도체 직접회로에 대한 테스트 모드시에서의 메모리 블록의 어드레스신호와 셀블록선택과의 관계를 나타낸 도면.

Claims (6)

  1. 제1어드레스공간을 갖는 기록/독출이 가능한 제1메모리 블록(B)와, 상기 제1어드레스공간의 폭보다 작은 어드레스공간을 가지고, 적어도 테스트모드시에 상기 제1메모리 블록(B)과 어드레스의 일부를 공유하는 기록/독출이 가능한 적어도 1개의 제2메모리 블록(A), 상기 메모리 블록(A,B)의 어드레스 선택을 행하는 어드레스 디코더(11~13,31,32)및, 상기 테스트 모드시에 상기 각 메모리 블록(A,B)의 어드레스 스캔을 공통으로 행하는 어드레스 스캔신호가 상기 제2메모리 블록(A)의 어드레스폭을 넘는 동안에는 상기 제2메모리 블록(A)의 기록을 금지하는 제어회로(16)을 구비하여, 복수개의 메모리 블록을 동시에 테스트할 수 있도록 되어 있는 것을 특징으로 하는 반도체 집적회로.
  2. 제1항에 있어서, 상기 제어회로(16)는 상기 어드레스 스캔신호의 일부를 디코드함에 의해 상기 어드레스 스캔신호가 상기 제2메모리 블록(A)의 어드레스폭을 넘는 기간을 검지하여 기록금지제어를 행하도록 되어 있는 것을 특징으로 하는 반도체 집적회로.
  3. 제1항에 있어서, 로직회로가 내장되어 있는 것을 특징으로 하는 반도체 집적회로.
  4. 제1항 내지 제3항중 어느 한 항에 있어서, 상기 제1메모리 블록(B)및 제2메모리 블록(A)이 통상동작시에도 어드레스의 일부를 공유하는 캐시 메모리인 것을 특징으로 하는 반도체 집적회로.
  5. 제1항 내지 제3항중 어느 한 항에 있어서, 상기 제1메모리 블록(B) 및 제2메모리 블록(A)이 통상동작 모드시에는 각각 다른 어드레스신호에 의해 어드레스선택되고, 테스트 모드시에는 제1메모리 블록(B)의 어드레스 스캔을 행하는 어드레스 스캔신호의 일부를 선택하여 상기 제2메모리 블록(A)용 어드레스 디코더에 입력하는 어드레스 선택회로(41)를 구비하는 것을 특징으로 하는 반도체 집적회로.
  6. 제1항 내지 제3항중 어느 한 항에 있어서, 테스트 모드시에 어드레스 스캔신호를 발생시키는 자기테스트어드레스 발생회로(50)와, 테스트 모드시에 상기 어드레스 스캔신호를 선택하여 상기 어드레스 디코더에 입력하는 어드레스 선택회로(51,52)를 구비하는 것을 특징으로 하는 반도체 직접회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910023915A 1990-12-27 1991-12-23 반도체 집적회로 Expired - Fee Related KR960000346B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2418754A JPH0770240B2 (ja) 1990-12-27 1990-12-27 半導体集積回路
JP90-418754 1990-12-27

Publications (2)

Publication Number Publication Date
KR920013476A true KR920013476A (ko) 1992-07-29
KR960000346B1 KR960000346B1 (ko) 1996-01-05

Family

ID=18526542

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910023915A Expired - Fee Related KR960000346B1 (ko) 1990-12-27 1991-12-23 반도체 집적회로

Country Status (5)

Country Link
US (1) US5388104A (ko)
EP (1) EP0492624B1 (ko)
JP (1) JPH0770240B2 (ko)
KR (1) KR960000346B1 (ko)
DE (1) DE69124735T2 (ko)

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Also Published As

Publication number Publication date
EP0492624A1 (en) 1992-07-01
US5388104A (en) 1995-02-07
DE69124735T2 (de) 1997-07-03
EP0492624B1 (en) 1997-02-19
JPH04229499A (ja) 1992-08-18
KR960000346B1 (ko) 1996-01-05
DE69124735D1 (de) 1997-03-27
JPH0770240B2 (ja) 1995-07-31

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