KR930001739B1 - Word Line Structure of Semiconductor Memory Array - Google Patents

Abstract

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Description

Word Line Structure of Semiconductor Memory Array

1 is a conventional twisted word line configuration.

2 is a cross-sectional view of the memory cell.

3 is a layout view of a metal and a polysilicon layer by a conventional method.

4 is a layout view of a core and a polysilicon layer according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to word lines in semiconductor memory devices, and more particularly to word line structures that prevent confusion in signal transmission in semiconductor memory arrays of twisted WL structures.

As the semiconductor memory device becomes more integrated and miniaturized, the layout of the layout of the semiconductor memory device becomes increasingly complicated.

In the memory array, as the plurality of bit lines and word lines cross each other, the distance between the lines becomes narrow, so that when the signal is transmitted through one line, the coupling capacity with neighboring liars may be induced. have.

In the case of a word line, as the memory capacity of a general semiconductor memory device increases, the length thereof becomes longer and the pitch is also narrowed.

If the length of the word line is longer, the word line driving time (or access time) for selecting the memory cell is delayed. To compensate for this, the memory device can form a metal layer on polysilicon, which is a word line material, so that high-speed operation is possible. I'm trying to.

However, coating a metal layer (Al, etc.) with a word line electrode results in a larger coupling capacity component that is induced due to a narrower space between word lines.

Noise caused by the capacitive component between such word lines causes instantaneous charge / discharge phenomena due to the capacitive capacitance in neighboring word lines, which causes malfunctions in the memory operation at high speed. There are many possibilities.

Therefore, conventionally, a plurality of word lines arranged in parallel are twisted in a strapping region in the middle of a word line as shown in FIG. 1, that is, they are not adjacent after being twisted with the first adjacent word line. After the word lines WL1 and WL4 are twisted, four word lines are twisted into a pair in a structure located between the word lines WL3 and WL2.

Therefore, the coupling noise induced between the first adjacent word lines is reduced by the distance from each other after twisting.

However, there is another problem that arises here, which is a scrambel problem in address signal transmission because the word line is twisted.

In the memory device, the word line is selected by receiving the output of a word line driver (or a low decoder) that receives a row address signal coming through a row address buffer. And a metal layer is connected on top of the polycrystalline silicon layer to select a corresponding word line.

FIG. 2 is a cross-sectional view of a DRAM cell having a general stacked capacitor structure. In FIG. 2, a polycrystalline silicon layer (GP _o , CP _P , GP _q) forming a gate of a MOS transistor is shown in FIG. ) And metal electrodes (M _o , M _p , M _q ) are formed.

When the word line is formed by the conventional method, the metal lines ME1 to ME4 and the polysilicon lines GP1 to GP4 are twisted together as shown in FIG. 3, and thus the polysilicon lines GP1 are twisted together. -Address signals passing through GP4) can be confused, causing memory chips to be confused when analyzing a defect or selecting an address.

Accordingly, an object of the present invention is to provide a word line structure that can prevent confusion of address selection and determination due to twisting of a word line in a twisted word line structure.

The present invention also provides a structure of a semiconductor memory array capable of preventing confusion of address selection and determination due to twist in a semiconductor memory array having a twist line structure.

In order to achieve the object of the present invention, the present invention provides a semiconductor device comprising a plurality of memory cells including one MOS transistor and one capacitor, and a plurality of bit lines and word lines connected to each of the memory cells. In the memory array, each of the word lines comprises a first layer connected in parallel to the gate of the MOS transistor and a second layer having a low resistance connected to the first layer. The second layer belonging to a first word line is twisted at least once in a predetermined region of the semiconductor memory array and the second layer belonging to a second word line neighboring the first word line.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. 4 shows a word line configuration according to the present invention. As shown in FIG. 4, the polysilicon lines GP1 to GP4 through which the address signal actually passes are sequentially arranged in parallel without twisting, and the polysilicon lines GP1 to CP4 and the memory device Only the metal lines ME1-ME4 connected at the top of the gate region are twisted at each intermediate point of the word lines WL1-WL4.

Each of the polysilicon lines GP1 -CP4 and the metal lines ME1 -ME4 is connected through contact regions C1, C2, C3, and C4 made of materials having low resistance.

Therefore, since the address signals passing through the word lines WL1, WL2, WL3, and WL4 are transmitted through the polysilicon lines GP1-GP4, there is no coupling between metal lines without scramble due to the change of the address selection terminal. You can operate while suppressing noise.

The embodiment of the present invention has been described to prevent the confusion of the address signal and the change of the selection terminal in the case of twisted word lines. However, the present invention can also be applied to various data buses having a multi-layer wiring structure in a semiconductor memory device. will be.

As described above, the present invention twists only the metal layer except the polysilicon layer to which the address signal is actually transmitted in the twisted word line structure, thereby reducing the coupling capacitance component between the metal layers, and causing confusion in address signal transmission and address selection terminals. There is an advantage that can prevent the change.

Claims (7)

In the semiconductor memory array comprising a plurality of memory cells consisting of one MOS transistor and one capacitor, and a plurality of bit lines and word lines connected to each of the memory cells, each of the word lines, A first layer connected in parallel to the gate of the MOS transistor and a second layer having low resistance connected to the first layer, wherein the second layer belonging to the first word line among the word lines And at least one twist in at least one predetermined region of the semiconductor memory array and the second layer belonging to a second word line adjacent to the first word line. The semiconductor memory array of claim 1, wherein the MOS transistor is a gate material of the first layer and polysilicon. The semiconductor memory array of claim 1, wherein the second layer is formed of a low resistance metal material. The semiconductor of claim 1, wherein after the second layer of the first word line is twisted, the semiconductor layer is connected to the first layer of the first word line by a third layer having a low resistance near the second word line. Memory array. The semiconductor memory according to claim 1, wherein the semiconductor memory is connected to a first layer of the first word line by a third layer having a low resistance near the third word line after being twisted with the second layer of the first word line. Array. A semiconductor memory array comprising: a plurality of memory cells comprising one MOS field effect transistor and one capacitor, a signal connected to a gate of the MOS field effect transistor and selecting the memory cell is transmitted, and is transferred onto the semiconductor memory array A plurality of first layers extending in parallel, and a plurality of low resistances electrically connected to each of the first layers and at least one or more connected horizontally and spaced apart from the respective first layers on the semiconductor memory array And a plurality of second layers having low resistances connected to the second layers and the first and second layers in pairs, respectively. 7. The semiconductor memory array of claim 6, wherein a plurality of first layers, second layers, and third layers constitute a word line for selecting the memory cells.

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