KR940009610B1 - Capacitor Manufacturing Method for Highly Integrated Semiconductor Memory Devices - Google Patents

Abstract

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Description

Capacitor Manufacturing Method for Highly Integrated Semiconductor Memory Devices

1 is a simplified layout diagram for manufacturing a capacitor of a semiconductor memory device by a general method.

2A through 2E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor memory device according to a general method obtained by cutting the line AA of FIG. 1.

3 is a layout diagram of one embodiment for manufacturing a capacitor of a highly integrated semiconductor memory device according to the method of the present invention.

4 is a layout diagram of another embodiment for manufacturing a capacitor of a highly integrated semiconductor memory device according to the present invention.

5 is a layout diagram of another embodiment for manufacturing a capacitor of a highly integrated semiconductor memory device according to the present invention.

6A to 6G are cross-sectional views illustrating a method of manufacturing a capacitor of a highly integrated semiconductor memory device according to the method of the present invention, taken along lines AA of FIGS. 3, 4, and 5;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a capacitor of a highly integrated semiconductor memory device, which improves a cell capacitance by improving a conventional capacitor manufacturing method, which shows a limitation in high integration due to a minimum design roll size. will be.

The decrease in cell capacitance due to the reduction of the unit area of memory cells is a serious obstacle to the increase in the density of DRAM (Dynamic Random Access Memory), which not only reduces the readability of the memory cells and increases the soft error rate, Since the operation is difficult and the power consumption is excessive during operation, it is a problem to be solved for the high integration of the semiconductor memory device.

In general, in a 64Mb DRAM having a memory cell area of about 1.5 μm 2, if a general two-dimensional stacked memory cell is used, it is difficult to obtain sufficient cell capacitance even when a material having a high dielectric constant such as Ta ₂ O ₅ is used. Therefore, the stack capacitor of the three-dimensional structure is proposed to improve the capacitance. The double stack structure, fin structure, cylindrical structure, spread stack structure, and box structure are the three-dimensional structures proposed to increase the cell capacitance of memory cells. Storage electrodes.

In the three-dimensional stack type cell capacitor structure, especially the box structure capacitor can be used as an effective capacitor area not only on the outer surface of the box but also on the inner surface, and thus it is adopted in a structure suitable for 64 Mb-class memory or higher-density memory cells. A method of manufacturing a general box structure capacitor and a problem thereof will be described with reference to a paper published in SSDM in 1989 by Toshiba, Japan, "A New Stacked Capacitor Cell With Thin Box Structured Storge Node."

FIG. 1 is a simplified layout diagram for manufacturing a capacitor of a semiconductor memory device according to a general method, wherein a region formed in a horizontal rectangular shape at a center portion and defined by a dashed line is a field for dividing a semiconductor substrate into an active region and an inactive region. A mask pattern P1 for forming an oxide film, and a region symmetrically centered and formed in a rectangular shape vertically long and defined by a solid line is a mask pattern P2 for forming a gate electrode, and is located in the center and crossed diagonally therein. The region, which is formed in a square shape and is defined by a solid line, is a mask pattern P3 for bit line contact, and is symmetrically left and right around a center portion and is formed in a rectangular shape, and the region defined by a long plate line forms a first storage electrode pattern. Mask pattern P4 for Includes a rectangular shape and a limited area in a short broken line is a mask pattern (P5) for forming a second storage electrode.

2A through 2E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor memory device according to a general method obtained by cutting the line AA of FIG. 1.

In the active region of the semiconductor substrate divided into the active region and the inactive region by the field oxide film 12, one drain region 16 and one bit line 22 are shared with each other, each of which has one source region ( 14) and after forming two transistors having a gate electrode, an insulating material is applied to the entire surface of the substrate on which the transistor is formed to form an interlayer insulating layer 20 for insulating the transistors (FIG. 2A). ). Subsequently, a silicon oxide film (SiO ₂ ) is used as the planarization layer 30, a silicon nitride film (Si ₃ N ₄ ) is used as the etch stop layer 32, and the silicon oxide film is stacked as a spacer layer 34. The spacer layer, the etch stop layer, the planarization layer, and the interlayer insulating layer are sequentially etched using a mask pattern for forming holes (not shown in FIG. 1 but similar to the mask pattern P5). The hole 9 is formed (FIG. 2B). The first polycrystalline silicon 100a doped with impurities in the form of filling the contact hole 9 is deposited on the entire surface of the resultant hole in which the contact hole is formed by the above-described process. After the first silicon oxide film 36, the second polycrystalline silicon layer 100b doped with impurities and the second silicon oxide film 38 are stacked on the first polycrystalline silicon, the first storage electrode mask pattern P4 is stacked. The second silicon oxide film, the second polycrystalline silicon layer, and the first silicon oxide film are sequentially etched using the same to form a first storage electrode pattern defined for each cell. After depositing a third polysilicon layer doped with impurities on the entire surface of the semiconductor substrate on which the first storage electrode pattern is formed by the etching process, the entire surface of the third polycrystalline silicon layer is exposed to the anisotropic etching process. A spacer 100c including a third polysilicon layer is formed on the sidewall of the electrode pattern, and the first polycrystalline silicon layer is etched so as to be limited to each cell unit using the spacer as an etching mask (FIG. 2C). Subsequently, by using the second storage electrode mask pattern P5, materials stacked on the first polysilicon layer 100a defined in each cell unit are etched to remove part of the lid (window). A storage electrode 100 having a box structure in which all surfaces except for the above are closed is completed (FIG. 2D). Subsequently, a dielectric material is formed on the entire surface of the semiconductor substrate on which the storage electrode is formed to form the dielectric film 110, and then a conductive material is deposited on the entire surface of the dielectric film to form the plate electrode 120. A general box structure capacitor composed of the electrode 100, the dielectric film 110 and the plate electrode 120 is knitted (FIG. 2E).

According to the capacitor of the semiconductor memory device according to the general method described above, since both the outer surface and the inner surface of the box structure storage electrode can be used as an effective capacitor area for securing cell capacitance, it is advantageous to secure sufficient cell capacitance due to high integration. However, in the process of forming a window on the first storage electrode pattern after etching the third polycrystalline silicon to form the spacer 100, if the size of the first storage electrode pattern is large, there is no misalignment. The window can be easily formed, but otherwise (horizontal / vertical = 1.0 / 0.4), the window is not easily formed because there is no alignment margin at all on the vertical axis. In addition, since a contact hole is formed after stacking a plurality of materials such as a planarization layer, a vision blocking layer, and a spacer layer, it is not easy to form a self-aligning contact hole generally used to form a high density memory cell.

An object of the present invention is a method of manufacturing a capacitor of a highly integrated semiconductor memory device, which is not limited by the size of the minimum design rule and can increase the actual capacitance.

The object of the present invention is to provide a semiconductor substrate in a matrix shape with memory cells consisting of one transistor and one capacitor. In a capacitor manufacturing method of a highly integrated semiconductor memory device, a transistor is formed on a semiconductor substrate. Forming a contact hole so that the source region is exposed; Forming a first conductive layer on the entire surface of the semiconductor substrate where the contact hole is formed; forming a first material layer on the entire surface of the first conductive layer; Forming a second conductive layer over the entire first material layer; Forming a second material layer on the entire surface of the second conductive layer; Applying a photoresist to the entire surface of the second material, and then forming a first photoresist pattern using a first storage electrode mask pattern; Forming a first storage electrode pattern patterned in any shape and formed of the material layers by sequentially etching the material layers stacked on the first conductive layer using the first photoresist pattern as an etching mask; Forming a third conductive layer on the entire surface of the resultant; Forming a second storage electrode by partially removing the material layers and the third conductive layer by applying a second storage electrode mask pattern to the resultant material on which the third conductive layer is stacked; Wet etching the first and second material layers exposed to the surface by the process for forming a second storage electrode pattern; Applying a third storage electrode mask pattern to the resultant from which the first and second materials have been removed to partially etch the stacked materials, thereby completing a storage electrode that is limited to each cell and contacts the source region; Forming a dielectric film on an entire surface of the semiconductor substrate on which the storage electrode is formed; And stacking a fourth conductive layer on the entire surface of the resultant material on which the dielectric film is formed, thereby forming a plate electrode.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

3, 4 and 5 are layout diagrams of an embodiment for manufacturing a capacitor of a highly integrated semiconductor memory device according to the method of the present invention, wherein the region formed in a horizontally long rectangular shape at the center and defined by a dashed line is A mask pattern P1 for forming a field oxide film for dividing a semiconductor substrate into an active region and an inactive region. The mask pattern P1 is formed to have a rectangular shape symmetrically from side to side and long and vertically centered around a central portion. It is a mask pattern (P2), and is formed in a square shape with a diagonal line located inside the center portion, and the area defined by the solid line is a mask pattern (P3) for bit line contact, and an inclined diagonal line to the left is drawn therein. The region defined by the two-dot chain line has a mask pattern P4 for forming the first storage electrode pattern. A region inclined to the right and defined by a short broken line is a mask pattern P5 for forming a second storage electrode pattern, and a region symmetrically to the left and defined by a long broken line is a third storage electrode pattern. Mask pattern P6 for forming a pattern.

In the drawings, it can be seen that the first and second storage electrode patterns of the drawings are formed differently. In FIG. 3, the two patterns are formed in a long line across the entire surface of the semiconductor substrate. The first storage electrode pattern is limited to each cell unit, while the second storage electrode pattern is formed to be elongated over the entire surface of the semiconductor substrate. In FIG. 5, both patterns are formed to be limited to each cell unit. According to the other arrangement of the two patterns as described above, the final cell capacitance and the structure of the cell capacitor are slightly different. According to the pattern arrangement of FIG. 3, a capacitor structure having an inverted pin structure opened to the front and back sides is formed. According to the pattern arrangement of FIG. 4, the double box structure is formed in a closed shape except for the center portion where the long groove is dug by the second storage electrode pattern. Then, the pattern arrangement of FIG. 5 is formed in a double box structure in a shape similar to that of the general box structure.

6A to 6G are cross-sectional views illustrating a method of manufacturing a capacitor of the highly integrated semiconductor memory device according to the present invention, taken along lines AA of FIGS. 3, 4, and 5.

First, referring to FIG. 6A, a process of forming a transistor on a semiconductor substrate is illustrated, wherein one drain region is formed in each of the active regions of the semiconductor substrate divided into an active region and an inactive region by the field oxide film 12. 16 and one bit line 22 are shared with each other, and two transistors each having one source region 14 and a gate electrode 18 are formed, and then the front surface of the substrate on which the transistor is formed is formed. An insulating material is applied to form an interlayer insulating layer 20 to insulate the transistor.

Referring to FIG. 6B, a process of forming a contact hole and a process of adapting respective material layers partially removes the interlayer insulating layer 20 formed on a source region of a transistor. Forming a contact hole for contacting an electrode with the source region, wherein the contact hole may be formed by a conventional photo / etch process using a mask pattern (not shown) for forming the contact hole, It can also be formed by a coherent method (a mask pattern must also be used, but the margin for the process is large), since only the interlayer insulating layer 20 is stacked in the region where the contact hole is to be formed. It is easy to apply the method of forming a contact hole by the self-aligning method which enables the formation of a contact hole of large and fine size. This enables the formation of self-aligned contact holes by the multi-layered material layer as described in the general box structure storage electrode forming method can overcome the difficulty, thereby miniaturizing the cell by high integration.

Subsequently, the first conductive layer 40, the second material layer 42, the second conductive layer 44, and the second material layer 46 are sequentially stacked on the entire surface of the semiconductor substrate where the contact hole is formed. In this case, the conductive layer and the material layers may be formed of a material having a different etching rate with respect to wet etching, for example, polycrystalline silicon doped with impurities in the conductive layer and an insulating material in the material layer. In addition, a storage electrode is further stacked on the stacked conductive layer and the material layer by stacking a plurality of layers of a pair of a conductive layer made of the same material as the second conductive layer and a material layer made of the same material as the second material layer. It is apparent to those skilled in the art that the number of layers can be adjusted.

Referring to FIG. 6C, a process of forming a first storage electrode pattern is illustrated in which a semiconductor substrate on which the layers, that is, the first conductive layer, the first material layer, the second conductive layer, and the second material layer are stacked is formed. After the photoresist is coated on the entire surface and softbaked, the mask pattern P4 for forming the first storage electrode pattern is applied to form the first photoresist pattern 72 for forming the first storage electrode pattern. Subsequently, the first photoresist pattern is used as an etching mask, and the remaining layers except for the first conductive layer, that is, the first material layer 42, the second conductive layer 44, and the second material layer 46 are subjected to dry etching. Removal to form a first storage electrode pattern. At this time, it is apparent to those skilled in the art that the shape of the first storage electrode pattern is different according to the mask patterns P4 of FIGS. 3, 4, and 5. Do. According to the mask pattern P4 of FIG. 3, the first storage electrode pattern is formed to include a source region of each cell and to be elongated in a shape of a stack over the entire semiconductor substrate. According to the mask pattern P4, the first storage electrode pattern is formed in an island shape including a source region of each cell and defined by a cell unit.

Referring to FIG. 6D, a process of forming the third conductive layer 48 is illustrated. A polysilicon doped with, for example, impurities is deposited on the entire surface of the semiconductor substrate on which the first story electrode pattern is formed. Therefore, the third conductive layer 48 is formed. In this case, the third conductive layer may have the same etching rate as that of other layers for dry etching, and a material having an etching rate different from that of the first material layer and the second material layer for wet etching.

Referring to FIG. 6E, it illustrates a process of forming the second storage electrode pattern, which is formed in the shape of a stack by the mask pattern P4 of FIG. 3 or by the mask pattern P4 of FIGS. 4 and 5. A second storage electrode pattern is formed by applying a mask pattern P5 for forming a second storage electrode pattern to the first storage electrode pattern formed in an island shape, wherein the mask pattern P5 has the first storage in a horizontal length. It is formed in the shape included in the electrode pattern, and in the vertical length is formed in the shape of a long line throughout the substrate as shown in Figures 3 and 4, it is necessary to take into account the vertical line alignment margin that has been a problem in the general box structure capacitor There will be no. At this time, the mask pattern P5 of FIG. 5 is applied when the size of the first storage electrode pattern is large enough not to consider the alignment margin of the vertical length, and is similar to the shape of the general box structure capacitor.

The second storage electrode pattern may be formed in two ways. One method includes first transferring a second storage electrode pattern to the third conductive layer by a photo / visual process, and then repeating wet / dry / wet etching. The second storage electrode pattern is transferred to other layers, and another method includes first and second layers remaining in wet etching after partially removing other layers except the first conductive layer in one dry etching process. It is a method of removing the material layer. It is desirable to properly adjust the materials to be laminated according to each method.

Referring to FIG. 6F, a process of forming a third storage electrode pattern for defining a storage electrode in each cell unit is performed. After forming the photoresist pattern 74 by applying the mask pattern P6, By partially etching the stacked materials using the pattern 74 as an etching mask, the storage electrode 100 defined in each cell unit is completed. At this time, it is apparent to those skilled in the art that the final shape of the storage electrode depends on the arrangement and shape of the mask patterns shown in FIGS. 3, 4, and 5.

Referring to FIG. 6G, the process of forming the dielectric film 110 and the plate electrode 120 is shown as a high dielectric material on the entire surface of the semiconductor substrate on which the storage electrode 100 is formed, for example, Ta ₂ O. After forming the dielectric film 110 by applying a material such as ₅ , the plate electrode 120 is completed by depositing a fourth conductive layer on the entire surface of the dielectric film.

Therefore, the capacitor of the semiconductor memory device can be easily formed, the alignment margin is large according to the minimum design size, and the cell capacitance can be easily secured.

It is apparent that the present invention is not limited to the above embodiments, and many modifications may be made by those skilled in the art within the technical spirit of the present invention.

Claims (16)

A first process of sequentially stacking a first conductive layer, a first material layer, a second conductive layer, and a second material layer on a semiconductor substrate, and a second process of forming a first storage electrode pattern on the second material layer. A third process of partially etching the second material layer, the second conductive layer, and the first material layer sequentially using the first storage electrode pattern as an etching mask; and forming a third conductive layer on the entire surface of the resultant And a fifth step of forming a second storage electrode pattern on the resultant layer in which the third conductive layer, the second material layer, the second conductive layer, the first material layer, and the first conductive layer are sequentially stacked. A sixth process of partially etching the materials stacked on the first conductive layer sequentially using the storage electrode pattern as an etching mask, and forming a third storage electrode pattern having a shape defined in each cell unit on the resultant Step 7 and etching the third storage electrode pattern Capacitor manufacturing method of a highly integrated semiconductor memory device characterized in that it comprises a step of forming a storage electrode 8 by performing the etching process. The method of claim 1, wherein in the first step, a plurality of layers are formed on the second material layer by pairing a conductive layer made of the same material as the second conductive layer and a material layer made of the same material as the second material layer. A method for manufacturing a capacitor of a highly integrated semiconductor memory device, characterized in that further stacked. The semiconductor device of claim 1, wherein the first, second, and third conductive layers are formed of a material having an etch rate different from that of the first and second material layers in wet etching. Capacitor manufacturing method. 2. The method of claim 1, wherein the first storage electrode pattern is formed to be long and arranged in a row overlapping the entire cell array. The method of claim 4, wherein the second storage electrode pattern is included in the first storage electrode pattern, and the second storage electrode pattern is long along the first storage electrode pattern. 5. The method of claim 4, wherein the second storage electrode pattern has a shape included in the first and third storage electrode patterns. 6. The method of claim 1, wherein the first storage electrode pattern has a shape included in the third storage electrode pattern. The semiconductor device of claim 7, wherein the second storage electrode pattern is included in the first storage electrode pattern in one direction and is not included in the first storage electrode pattern in the other direction. Method of manufacturing capacitor of memory device. 8. The method of claim 7, wherein the second storage electrode pattern has a shape included in the first and third storage electrode patterns. 9. The method of claim 1, wherein the sixth step comprises: etching the third conductive layer using the second storage electrode pattern as an etching mask; removing the second material layer exposed to the surface by wet etching; 2. The method of manufacturing a capacitor of a high density semiconductor memory device, comprising: etching the second conductive layer using the storage electrode pattern as an etching mask; and removing the first material layer by wet etching. The semiconductor device of claim 10, wherein the first, second, and third conductive layers are formed of a material having a different etching rate from that of the first and second material layers in wet etching. Capacitor manufacturing method. The method of claim 1, wherein the sixth step comprises partially etching the third conductive layer, the second material layer, the second conductive layer, and the first material layer by using the second storage electrode pattern as an etching mask. And proceeding to remove the second material layer and the first material layer. The semiconductor memory device of claim 13, wherein the first, second, and third conductive layers are formed of a material having a different etching rate from that of the first and second material layers in wet etching. Capacitor manufacturing method. 15. The method of claim 14, wherein the first and second material layers are formed of a material having a similar etch rate in the wet etching. The method of claim 1, wherein the materials stacked on the first conductive layer are formed of a material having a similar etching rate in dry etching. The method of claim 13, wherein the dry etching is performed using different etching sources for different material layers.