[go: up one dir, main page]

KR940002738B1 - Surface cleaning method of semiconductor substrate - Google Patents

Surface cleaning method of semiconductor substrate Download PDF

Info

Publication number
KR940002738B1
KR940002738B1 KR1019910011611A KR910011611A KR940002738B1 KR 940002738 B1 KR940002738 B1 KR 940002738B1 KR 1019910011611 A KR1019910011611 A KR 1019910011611A KR 910011611 A KR910011611 A KR 910011611A KR 940002738 B1 KR940002738 B1 KR 940002738B1
Authority
KR
South Korea
Prior art keywords
semiconductor substrate
oxide film
cleaning
chemical treatment
treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019910011611A
Other languages
Korean (ko)
Other versions
KR930003274A (en
Inventor
고용선
안성규
Original Assignee
삼성전자 주식회사
김광호
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사, 김광호 filed Critical 삼성전자 주식회사
Priority to KR1019910011611A priority Critical patent/KR940002738B1/en
Publication of KR930003274A publication Critical patent/KR930003274A/en
Application granted granted Critical
Publication of KR940002738B1 publication Critical patent/KR940002738B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

내용 없음.No content.

Description

반도체기판의 표면세정방법Surface cleaning method of semiconductor substrate

제1도는 종래 방법에 의한 반도체기판의 표면세정방법을 공정순서에 따라 도시한 흐름도.1 is a flowchart showing a surface cleaning method of a semiconductor substrate according to a conventional method according to a process sequence.

제2도는 본 발명에 의한 반도체기판의 표면세정방법을 공정순서에 따라 도시한 흐름도.2 is a flowchart showing a surface cleaning method of a semiconductor substrate according to the present invention according to a process sequence.

본 발명은 반도체기판의 표면세정방법에 관한 것으로, 특히 세정공정 후의 건조시에 발생할 수 있는 물반점(Watermark)의 생성을 억제할 수 있는 반도체기판의 표면세정방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface cleaning method of a semiconductor substrate, and more particularly, to a surface cleaning method of a semiconductor substrate capable of suppressing the generation of water marks that may occur during drying after a cleaning process.

상기의 세정공정중 반도체기판의 Si 표면이 노출되는 부분의 친수성 표면과 소수성 표면이 함께 존재하는 경우에, 스핀드라인(Spin dry)를 이용한 건조시 대기중으로부터 유입된 공기중의 O2가 Si 표면에 있는 물기와 반응하여 SiOx를 형성하게 된다. 이때 생성된 SiOx는 스핀드라이를 위한 회전시 친수성 표면인 SiO2와 소수성 표면인 Si 경계면에 모이게 되고, 이것이 적층되어 물반점(Watermark)이 형성되게 된다. 이러한 물반점은 일정한 두께를 갖는 산화층이 되므로 배선의 콘택불량등 생성장소에 따라 여러가지 장애를 초래하는데, 특히 반도체 디바이스의 미세화에 따른 얇은 산화막의 형성에 있어서 큰 영향을 미치므로 반도체 디바이스의 특성을 저하시킬 수 있다. 이러한 문제점을 개선하기 위하여 설비적으로는 IPA 드라이(Isopropylalcohol dry), H2 드라이 등의 방법을 사용하여 해결하고 있으며, 공정면으로는 H2O2중화처리 및 SC-1(NH4OH+H2O2+H2O), SC-2(HCl+H2O2+H2O) 처리를 행하여 물반점의 생성을 억제하고 있다.In the case where the hydrophilic surface and the hydrophobic surface of the part where the Si surface of the semiconductor substrate is exposed during the cleaning process are present together, the O 2 in the air introduced from the air during drying using spin dry is reduced to Si. It reacts with water on the surface to form SiO x . At this time, the generated SiO x is collected on the hydrophilic surface of SiO 2 and the hydrophobic surface of Si interface at the time of rotation for spin dry, and are stacked to form water marks. These water spots become oxide layers having a constant thickness, which causes various obstacles depending on the place of wiring, such as poor contact of wiring. In particular, the formation of a thin oxide film due to the miniaturization of semiconductor devices greatly affects the characteristics of semiconductor devices. You can. In order to improve this problem, the solution is solved by using a method such as IPA dry (Isopropylalcohol dry), H2 dry, etc., the process surface H 2 O 2 neutralization treatment and SC-1 (NH 4 OH + H 2 O 2 + H 2 O) and SC-2 (HCl + H 2 O 2 + H 2 O) treatment are performed to suppress the formation of water spots.

상기 종래의 세정공정을 제1도의 흐름도를 참조하여 설명하면 다음과 같다.The conventional cleaning process will be described below with reference to the flowchart of FIG. 1.

일반적으로 반도체기판 상에 소자분리를 위한 필드산화막을 형성한 후 희생산화막을 형성한 다음부터 세정공정이 진행되는바, 먼저 게이트산화막을 형성하기 위해 액티브영역 상에 형성된 희생산화막을 통상적으로 BOE(Buffered Oxide Etchant)를 사용하여 식각하게 된다(A). 이때, 소수성의 반도체기판과 친수성의 필드산화막의 경계면에 물반점이 생길 위험이 있어 반도체기판 표면을 모두 친수성으로 만들기 위한 화학처리, 예컨대 H2O2처리를 행하게 된다(B).In general, after the field oxide film for device isolation is formed on the semiconductor substrate and the sacrificial oxide film is formed, the cleaning process is performed. First, a sacrificial oxide film formed on the active region is typically buffered to form a gate oxide film. Oxide Etchant) is used for etching (A). At this time, there is a risk of water spots on the interface between the hydrophobic semiconductor substrate and the hydrophilic field oxide film, and chemical treatment such as H 2 O 2 treatment is performed to make both surfaces of the semiconductor substrate hydrophilic (B).

이어서, 게이트산화막을 형성하기 위하여 확산전처리 세정을 행하게 되는데, 양질의 산화막이 형성되도록 액티브영역 상의 자연산화막을 제거하는 공정이 필요하게 된다. 일반적으로, 확산전처리 세정은 자연산화막의 유기성분을 제거하기 위해 H2SO4보일(Boil)처리 또는 SC-1 처리를 한 후(C), 자연산화막의 제거 및 금속부룬물의 제거를 위해 HF 처리를 행하는 것이다(D). 이때, Si 표면이 노출되어 스핀건조시에 다시 물반점이 생길 위험이 있다. 따라서, 최종 세정처리는 반도체기판 표면을 친수성으로 만드는 화학물질을 사용하게 되는데(E), 이 경우 화학물질 자체에 포함되어 있는 불순물들이 반도체기판에 흡착되어 상기 기판을 오염시키게 된다. 또한, 상기 화학처리에 의해 반도체기판 상에 화학적으로 산화막이 생성되기 때문에, 상기 산화막으로 인하여 게이트산화막 형성시 불균일한 성장을 유발하여 디바이스의 특성을 열화시키게 된다.Subsequently, diffusion pretreatment cleaning is performed to form a gate oxide film, but a process of removing the native oxide film on the active region is required to form a high quality oxide film. In general, pre-diffusion cleaning is H 2 SO 4 Boil treatment or SC-1 treatment to remove the organic components of the natural oxide film (C), HF treatment to remove the natural oxide film and metal bubbling (D). At this time, the Si surface is exposed, there is a risk that water spots again occur during spin drying. Therefore, the final cleaning process uses chemicals that make the surface of the semiconductor substrate hydrophilic (E), in which case impurities contained in the chemical itself are adsorbed onto the semiconductor substrate and contaminate the substrate. In addition, since the oxide film is chemically formed on the semiconductor substrate by the chemical treatment, the oxide film causes uneven growth when the gate oxide film is formed, thereby deteriorating device characteristics.

본 발명은 상술한 문제점을 해결하기 위한 것으로, 반도체기판 세정시에 물반점의 생성을 방지할 수 있는 반도체기판의 표면세정방법을 제공하는데에 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object thereof is to provide a method for cleaning a surface of a semiconductor substrate which can prevent generation of water spots upon cleaning the semiconductor substrate.

상기 목적을 달성하기 위하여 본 발명의 방법은, 반도체 디바이스 제조시의 게이트산화막을 형성하기 전의 세정방법에 있어서, 반도체기판 액티브영역 상의 희생산화막을 식각하는 제1단계 공정과, 반도체기판 전면을 친수성으로 만들기 위해 화학처리를 행하는 제2단계 공정, 상기 화학처리시에 반도체기판상에 생성된 산화막을 제거하는 제3단계 공정, 반도체기판 상의 유기성분을 제거하는 제4단계 공정, 및 상기 유기성분 제거시에 화학적으로 반도체기판 상에 생성된 산화막을 식각함과 동시에 반도체기판 상의 금속불순물을 제거하는 제5단계 공정으로 구성된 것을 특징으로 한다.In order to achieve the above object, the method of the present invention includes a first step of etching a sacrificial oxide film on a semiconductor substrate active region in a cleaning method before forming a gate oxide film in manufacturing a semiconductor device, and the entire surface of the semiconductor substrate as hydrophilic. A second step of performing a chemical treatment to make a process, a third step of removing an oxide film formed on a semiconductor substrate during the chemical treatment, a fourth step of removing an organic component on the semiconductor substrate, and a process of removing the organic component. And a fifth step of chemically etching the oxide film formed on the semiconductor substrate and removing metal impurities on the semiconductor substrate.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제2도는 본 발명에 따른 반도체기판의 표면세정방법을 공정순서에 따라 나타낸 흐름도이다.2 is a flowchart showing a surface cleaning method of a semiconductor substrate according to the present invention in accordance with a process sequence.

먼저, 상기 종래예에서와 마찬가지로 게이트산화막을 형성하기 위해 액티브영역 상에 형성된 희생산화막을, 예컨대 BOE를 사용하여 식각한 다음(A), 소수성의 반도체기판과 친수성의 필드산화막의 경계면에 물반점이 생길 수 있는 위험을 제거하기위해 반도체기판의 표면을 전부 친수성으로 만드는 화학처리, 예컨대 H2O2처리를 행한다(B).First, the sacrificial oxide film formed on the active region is etched using BOE, for example, to form a gate oxide film as in the conventional example (A), and then water spots are formed on the interface between the hydrophobic semiconductor substrate and the hydrophilic field oxide film. In order to eliminate the danger that may occur, a chemical treatment such as H 2 O 2 treatment is performed to make the surface of the semiconductor substrate all hydrophilic (B).

이어서 확산전처리 세정으로서, 상기 화학처리, 예컨대 H2O2처리시에 생성된 산화막을 HF를 사용하여 완전히 제거한 후(C), 유기성분을 제거하기 위한 화학처리, 예컨대 H2SO4보일처리 또는 SC-1 처리를 진행한다(D).Subsequently, as a pre-diffusion cleaning, the oxide film generated during the chemical treatment such as H 2 O 2 treatment is completely removed using HF (C), followed by a chemical treatment such as H 2 SO 4 to remove organic components or SC-1 processing is performed (D).

다음에, 500 : 1~1,000 : 1의 비율로 희석된 HF를 사용하여 상기 유기성분 제거를 위한 화학처리시 반도체기판 상에 화학적으로 생성된 산화막을 식각함과 동시에, 반도체기판에 흡착된 금속불순물을 제거한다(E).Next, by using HF diluted in a ratio of 500: 1 to 1,000: 1, the chemically generated oxide film is etched on the semiconductor substrate during the chemical treatment for removing the organic components, and the metal impurities adsorbed on the semiconductor substrate are etched. Remove (E).

본 발명은 상기 E공정, 예컨대 희석 HF를 사용한 전처리 세정공정에 의하여 종래예에서 최종 세정공정시 문제시되던 산화막 생성 및 불순물 흡착을 제거함으로써, 물반점의 생성을 억제하여 안정된 게이트산화막을 형성할 수 있게 한다.The present invention removes oxide film formation and impurity adsorption, which are a problem in the final cleaning process in the conventional example, by the pretreatment cleaning process using the above-described E process, for example, dilute HF, thereby suppressing the formation of water spots to form a stable gate oxide film. do.

실제로 종래의 세정방법과 본 발명에 따른 세정방법에 의해 반도체기판 표면을 세정처리한 후 각각 디바이스를 제작하여 그 전기적 특성을 비교하였는 바, 그 결과를 표 1에 나타내었다. 전기적 특성은 6MV와 8MV에서의 브레이크다운 축적손상(Breakdown Cumnlative failure) 및 결함밀도(Defect density)로 평가하였다.In fact, after cleaning the surface of the semiconductor substrate by the conventional cleaning method and the cleaning method according to the present invention, each device was fabricated and the electrical characteristics thereof were compared. Table 1 shows the results. The electrical properties were evaluated by breakdown cumnlative failure and defect density at 6MV and 8MV.

[표 1]TABLE 1

상기 전기적 특성의 비교결과로부터 본 발명에 의한 세정방법의 세정교화가 더욱 우수함을 알 수 있다.It can be seen from the comparison result of the electrical characteristics that the cleaning method of the cleaning method according to the present invention is more excellent.

이상, 상술한 바와 같이 본 발명에 의한 반도체기판의 표면세정방법에 의하면, 반도체기판이 노출된 부분에서의 생성을 억제할 수 있다. 또한, 디바이스의 신뢰성을 좌우하는 게이트산화막의 형성시 전처리 세정효과를 통해 안정된 산화막의 형성을 도모할 수 있으므로, 반도체 디바이스의 신뢰성을 향상시킬 수 있다.As described above, according to the method for cleaning the surface of the semiconductor substrate according to the present invention, generation of the exposed portion of the semiconductor substrate can be suppressed. In addition, since the formation of a stable oxide film can be achieved through the pretreatment cleaning effect when forming the gate oxide film that influences the reliability of the device, the reliability of the semiconductor device can be improved.

Claims (6)

반도체 디바이스 제조시의 게이트산화막을 형성하기 전의 전처리 세정공정에 있어서, 반도체기판 액티브영역 상의 희생산화막을 식각하는 제1단계 공정과, 반도체기판 전면을 친수성으로 만들기 위해 화학처리를 행하는 제2단계 공정, 상기 화학처리시에 반도체기판 상에 생성된 산화막을 제거하는 제3단계 공정, 반도체기판 상의 유기성분을 제거하는 제4단계 공정 및 상기 유기성분 제거시에 화학적으로 반도체기판 상에 생성된 산화막을 식각함과 동싱 반도체기판 상의 금속불순물을 제거하는 제5단계 공정으로 구성된 것을 특징으로 하는 반도체기판의 표면세정방법.In the pretreatment cleaning process before forming the gate oxide film in the manufacture of a semiconductor device, a first step of etching the sacrificial oxide film on the semiconductor substrate active region, a second step of performing a chemical treatment to make the entire surface of the semiconductor substrate hydrophilic, A third step of removing the oxide film formed on the semiconductor substrate during the chemical treatment, a fourth step of removing the organic component on the semiconductor substrate, and etching the oxide film chemically formed on the semiconductor substrate upon the removal of the organic component And a fifth step of removing metal impurities on the copper semiconductor substrate. 제1항에 있어서, 상기 반도체기판 액티브영역 상의 희생산화막을 식각하는 공정은 BOE를 사용하여 행하는 것을 특징으로 하는 반도체기판의 표면세정방법.The method of claim 1, wherein the sacrificial oxide film on the semiconductor substrate active region is etched using BOE. 제1항에 있어서, 상기 반도체기판 전면을 친수성으로 만들기 위한 화학처리공정은 H2O2처리인 것을 특징으로 하는 반도체기판의 표면세정방법.The method of claim 1, wherein the chemical treatment for making the entire surface of the semiconductor substrate hydrophilic is H 2 O 2 . 제1항에 있어서, 상기 반도체기판을 친수성으로 만들기 위한 화학처리시에 생성된 산화막을 제거하는 공정은 HF를 사용하여 행하는 것을 특징으로 하는 반도체기판의 표면세정방법.The method of cleaning a surface of a semiconductor substrate according to claim 1, wherein the step of removing the oxide film generated during the chemical treatment for making the semiconductor substrate hydrophilic is performed using HF. 제1항에 있어서, 상기 반도체기판 상의 유기성분을 제거하는 공정은 H2SO4보일처리 또는 SC-1 처리를 행하는 것을 특징으로 하는 반도체기판의 표면세정방법.The method of claim 1, wherein the removing of the organic component on the semiconductor substrate is performed by H 2 SO 4 void treatment or SC-1 treatment. 제1항에 있어서, 상기 반도체기판 상의 유기성분 제거시에 화학적으로 생성된 산화막을 식각함과 동시에 반도체기판 상의 금속불순물을 제거하는 공정은 500 : 1~1000 : 1로 희석된 HF를 사용하여 행하는 것을 특징으로 하는 반도체기판의 표면세정방법.The method of claim 1, wherein the step of etching the chemically generated oxide film while removing the organic component on the semiconductor substrate and removing the metal impurities on the semiconductor substrate is performed using HF diluted to 500: 1 to 1000: 1. Surface cleaning method of a semiconductor substrate, characterized in that.
KR1019910011611A 1991-07-09 1991-07-09 Surface cleaning method of semiconductor substrate Expired - Fee Related KR940002738B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910011611A KR940002738B1 (en) 1991-07-09 1991-07-09 Surface cleaning method of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910011611A KR940002738B1 (en) 1991-07-09 1991-07-09 Surface cleaning method of semiconductor substrate

Publications (2)

Publication Number Publication Date
KR930003274A KR930003274A (en) 1993-02-24
KR940002738B1 true KR940002738B1 (en) 1994-03-31

Family

ID=19316973

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910011611A Expired - Fee Related KR940002738B1 (en) 1991-07-09 1991-07-09 Surface cleaning method of semiconductor substrate

Country Status (1)

Country Link
KR (1) KR940002738B1 (en)

Also Published As

Publication number Publication date
KR930003274A (en) 1993-02-24

Similar Documents

Publication Publication Date Title
US6129091A (en) Method for cleaning silicon wafers with deep trenches
KR900004055B1 (en) Method for stripping a photoresist
US5803980A (en) De-ionized water/ozone rinse post-hydrofluoric processing for the prevention of silicic acid residue
US6444582B1 (en) Methods for removing silicon-oxy-nitride layer and wafer surface cleaning
JP3492196B2 (en) Method for manufacturing semiconductor device
CN101213644A (en) Methods of etching oxide, reducing roughness, and forming capacitor structures
KR940002738B1 (en) Surface cleaning method of semiconductor substrate
US5538921A (en) Integrated circuit fabrication
US6077776A (en) Polysilicon residue free process by thermal treatment
US6573141B1 (en) In-situ etch and pre-clean for high quality thin oxides
KR960012625B1 (en) Wet cleaning process of semiconductor device
US6423646B1 (en) Method for removing etch-induced polymer film and damaged silicon layer from a silicon surface
KR100196420B1 (en) Method for forimg isolation region in semiconductor device
KR100247930B1 (en) Cleaning solution and cleaning method using the same
EP0767487A1 (en) Improvements in or relating to semiconductor device fabrication
CN1197132C (en) Wet chemical removal of silicon oxynitride material after gate etch process
KR100219071B1 (en) Semiconductor Wafer Cleaning Method
KR100622809B1 (en) Method of Cleaning Semiconductor Devices
JPH1168061A (en) Method for forming roughened conductive film and semiconductor device
KR0168208B1 (en) How to remove polypolymer
JP3346817B2 (en) Method for manufacturing semiconductor device
KR930011114B1 (en) Surface cleaning method of semiconductor substrate
KR100570203B1 (en) Gate electrode formation method
KR0165448B1 (en) Method of silicon processing monitoring
KR100244924B1 (en) Capacitor Manufacturing Method of Semiconductor Device

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

G160 Decision to publish patent application
PG1605 Publication of application before grant of patent

St.27 status event code: A-2-2-Q10-Q13-nap-PG1605

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

L13-X000 Limitation or reissue of ip right requested

St.27 status event code: A-2-3-L10-L13-lim-X000

U15-X000 Partial renewal or maintenance fee paid modifying the ip right scope

St.27 status event code: A-4-4-U10-U15-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 13

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 14

FPAY Annual fee payment

Payment date: 20080303

Year of fee payment: 15

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 15

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20090401

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20090401

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000