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KR950007098A - DRAM cell manufacturing method - Google Patents

DRAM cell manufacturing method Download PDF

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Publication number
KR950007098A
KR950007098A KR1019930015934A KR930015934A KR950007098A KR 950007098 A KR950007098 A KR 950007098A KR 1019930015934 A KR1019930015934 A KR 1019930015934A KR 930015934 A KR930015934 A KR 930015934A KR 950007098 A KR950007098 A KR 950007098A
Authority
KR
South Korea
Prior art keywords
storage electrode
layer
forming
pattern
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019930015934A
Other languages
Korean (ko)
Inventor
유의규
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930015934A priority Critical patent/KR950007098A/en
Priority to US08/273,904 priority patent/US5468670A/en
Priority to DE4424933A priority patent/DE4424933C2/en
Priority to JP6162482A priority patent/JP2637045B2/en
Publication of KR950007098A publication Critical patent/KR950007098A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 고집적반도체 소자의 제조방법에 관한 것으로, 특히 디램셀의 면적을 최소화시키면서 캐패시터 용량을 증대시키기 위하여 저장전극의 구조를 2중 원통형으로 제조하는 디램셀의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a method for manufacturing a DRAM cell in which the structure of a storage electrode is manufactured in a double cylindrical shape in order to increase the capacitor capacity while minimizing the area of the DRAM cell.

Description

디램셀 제조방법DRAM cell manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도A는 내지 제2E도는 본 발명에 의해 디램셀을 제조하는 공정단계를 도시한 단면도.2A to 2E are sectional views showing the process steps of manufacturing a DRAM cell according to the present invention.

Claims (3)

반도체기판에 MOS트랜지스터가 형성되고 그상부에 캐패시터가 형성되되 MOS트랜지스터에 접속되는 디램셀 제조방법에 있어서, MOS트랜지스터를 포함하는 반도체기판 상부에 평탄화용절연막을 형성하고 그상부에 식각베리어층과 폴리실리콘층을 적층한다음 저장전극 콘택마스크를 이용하여 콘택영역의 폴리실리콘층을 식각하여 폴리실리콘패턴을 형성하는 단계와, 상기 폴리실리콘패턴의 측벽에 폴리실리콘스페이서를 형성한 다음 폴리실리콘패턴과 폴리실리콘스페이스를 마스크로 이용하여 콘택영역의 식각베리어층과 그하부의 평탄화용절연막을 식각하여 반도체기판이 노출된 콘택홀을 형성하는 단계와, 제1저장전극용폴리실리콘층과 제1산화막을 적층하고, 저장전극콘택영역에만 감광막패턴을 형성하고 노출된 제1산화막 상부에 제2산화막을 형성하는 단계와, 상기 감광막패턴을 제거하고 다시 저장전극마스크용감광막패턴을 형성한다음, 노출된영역의 제2산화막, 제1산화막, 제1저장전극용폴리실리콘층, 폴리실리콘패턴을 제거하여 1차로 저장전극패턴을 형성하는 단계와, 상기 저장전극용감광막패턴을 제거한 후 제2저장전극용폴리실리콘 층을 형성한후, 그 측벽에 제3산화막스페이서를 형성하는 단계와, 제2저장전극용폴리실리콘층을 제2산화막과 식각베리어층이 노출되기 까지 식각하여 2중원통구조의 저장전극패턴을 형성하는 단계와, 남아있는 제3산화막스페이서, 제2산화막, 제1산화막을 제거하고, 저장전극패턴 표면에 캐패시터유전체막을 형성하고 그 상부에 플레이트전극을 형성하는 단계를 포함하는 디램셀 제조방법.In the method of manufacturing a DRAM cell in which a MOS transistor is formed on a semiconductor substrate and a capacitor is formed thereon, and is connected to the MOS transistor. Stacking a silicon layer to form a polysilicon pattern by etching the polysilicon layer in the contact region using a storage electrode contact mask, forming a polysilicon spacer on the sidewalls of the polysilicon pattern, and then forming the polysilicon pattern and the poly Etching the etch barrier layer of the contact region and the planarization insulating layer under the silicon layer as a mask to form a contact hole exposing the semiconductor substrate, and stacking the polysilicon layer for the first storage electrode and the first oxide layer A photoresist pattern is formed only on the storage electrode contact region, and a second oxide film is formed on the exposed first oxide film. Forming a photoresist pattern for the storage electrode mask and removing the second oxide film, the first oxide film, the polysilicon layer for the first storage electrode, and the polysilicon pattern. Forming a first storage electrode pattern, removing the photoresist pattern for the storage electrode, forming a second polysilicon layer for the storage electrode, and forming a third oxide spacer on the sidewall of the second storage electrode; Etching the molten polysilicon layer until the second oxide layer and the etch barrier layer are exposed to form a double-cylindrical storage electrode pattern, and removing the remaining third oxide spacer, second oxide layer and first oxide layer, Forming a capacitor dielectric film on a surface of the storage electrode pattern and forming a plate electrode thereon. 제1항에 있어서, 제3산화막스페이서를 형성하지 않은 상태에서 제2저장전극용실리콘층을 식각하여 2중 원통구조의 저장전극패턴을 형성하는 것을 특징으로 하는 디램셀 제조방법.The method of claim 1, wherein the silicon layer for the second storage electrode is etched without forming the third oxide film spacer, thereby forming a storage electrode pattern having a double cylindrical structure. 제1항에 있어서, 상기 제3산화막스페이서, 제2산화막, 제1산화막을 제거한후에, 저장전극패턴 저부에 있는 식각베리어층을 제거하는 것을 특징으로 하는 디램셀 제조방법.The method of claim 1, wherein after removing the third oxide film spacer, the second oxide film, and the first oxide film, the etching barrier layer on the bottom of the storage electrode pattern is removed. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930015934A 1993-07-14 1993-08-17 DRAM cell manufacturing method Withdrawn KR950007098A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019930015934A KR950007098A (en) 1993-08-17 1993-08-17 DRAM cell manufacturing method
US08/273,904 US5468670A (en) 1993-07-14 1994-07-12 Method for fabricating a semiconductor memory device having a stacked capacitor cell
DE4424933A DE4424933C2 (en) 1993-07-14 1994-07-14 Method for producing a dynamic memory cell
JP6162482A JP2637045B2 (en) 1993-07-14 1994-07-14 Method of manufacturing semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930015934A KR950007098A (en) 1993-08-17 1993-08-17 DRAM cell manufacturing method

Publications (1)

Publication Number Publication Date
KR950007098A true KR950007098A (en) 1995-03-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930015934A Withdrawn KR950007098A (en) 1993-07-14 1993-08-17 DRAM cell manufacturing method

Country Status (1)

Country Link
KR (1) KR950007098A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990073204A (en) * 1999-06-21 1999-10-05 강희준 The composition of base for a hydrated plaster
US6582724B2 (en) 1999-12-16 2003-06-24 Dermatrends, Inc. Dual enhancer composition for topical and transdermal drug delivery
US6586000B2 (en) 1999-12-16 2003-07-01 Dermatrends, Inc. Hydroxide-releasing agents as skin permeation enhancers
US6673363B2 (en) 1999-12-16 2004-01-06 Dermatrends, Inc. Transdermal and topical administration of local anesthetic agents using basic enhancers

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990073204A (en) * 1999-06-21 1999-10-05 강희준 The composition of base for a hydrated plaster
US6582724B2 (en) 1999-12-16 2003-06-24 Dermatrends, Inc. Dual enhancer composition for topical and transdermal drug delivery
US6586000B2 (en) 1999-12-16 2003-07-01 Dermatrends, Inc. Hydroxide-releasing agents as skin permeation enhancers
US6673363B2 (en) 1999-12-16 2004-01-06 Dermatrends, Inc. Transdermal and topical administration of local anesthetic agents using basic enhancers
US6835392B2 (en) 1999-12-16 2004-12-28 Dermatrends, Inc. Dual enhancer composition for topical and transdermal drug delivery

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Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19930817

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid