KR950013384B1 - Semiconductor memory device with trench capacitor - Google Patents

Abstract

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Description

Semiconductor memory device with trench capacitor

1 is a conventional perspective view.

2 is a conventional manufacturing process diagram.

3 is a manufacturing process diagram according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to a dynamic random access memory cell (DRAM) having a trench capacitor.

In general, a DRAM cell includes one transistor and one capacitor, and an operating characteristic of the cell depends on the storage capacity of the capacitor. Therefore, a method for increasing the accumulation capacity in the manufacturing process of high density DRAM cells has emerged as one of the most important problems. Stacked-capacitor cells and trench-capacitor cells have been proposed in order to obtain the maximum storage capacity within a narrowing cell area. Among them, the trench capacitor cell is more advantageous for increasing the capacity of the capacitor. However, the trench capacitor cell is directly affected by the electrical phenomenon in the substrate because the storage electrode of the capacitor is located in the substrate. This results in current leakage between the trenches and immunity problems with the α particles. In order to solve the above problem, a trench capacitor cell named HVSPC cell (Half-Vcc Sheath-Plate Capacitor Cell) has been proposed by Hitachi. Such cells are disclosed in the 1987 International Electron Devices Meeting (PP 332-335).

1 is a perspective view of a conventional HVSPC cell.

In the figure, a sheath-shaped plate electrode 15 having an oxide film 11 formed on an outer sidewall and having a buried diffusion layer 21 connected thereto, and a dielectric film adjacent to an inner wall of the plate electrode 15. An improved trench capacitor cell composed of the storage electrode 33 having the interlayer 23 as an intermediate layer is shown.

The diffusion layers connected to the respective plate electrodes are connected to each other in the substrate. 2a-e is a manufacturing process diagram of a conventional HVSPC cell (a)-(e) is a manufacturing process diagram of a trench capacitor, (a ')-(e') is a plate electrode It is a manufacturing process drawing which forms the terminal for applying. It should be noted that the same numbers are used for the first names and the same names. In FIG. 2 (a) and (a '), the oxide film 5 and the nitride film 7 are sequentially formed on the upper surface of the P-type semiconductor substrate 1 on which the field oxide film 3 is formed. Next, after forming a pattern for trench etching, an etching process is performed to form a trench 9a having a depth of 30 μm at the boundary portion of the field oxide layer 3. Then, an oxide film 11 is formed on the surface of the substrate 1, and then a reactive ion etching process is performed to leave the oxide film on the trench side wall. The remaining oxide film 11 is used as a sheath-like sheath to electrically insulate the plate electrode from the substrate. A trench for forming a capacitor is formed in FIG. 2a and at the same time a plate electrode is formed in FIG. A trench 9a is formed to apply a. The trench 9b is connected to a diffusion region formed by being buried in the substrate below. In Figures 2b and b 'above, The oxide film shell of the region where the voltage terminal is to be formed is removed. In this case, the first photoresist mask 13 is formed in the capacitor region. After the photoresist 13 is removed in FIGS. 2C and c ', the first polycrystalline silicon layer 15 and the oxide layer 17 having a predetermined thickness are formed. The trench is then filled with a second photoresist 19. Thereafter, a vapor phase diffusion process is performed to dope the first polysilicon layer with Phosphorus. The plate electrode is formed by the above process, and an n + diffusion region 21 for connecting the plate electrodes is formed on the bottom surface thereof. After the second photoresist 19 and the oxide layer 17 are removed in FIGS. 2D and d ', the second polysilicon layer 25 to be the dielectric layer 23 and the storage electrode is formed. Next, a mask pattern made of a predetermined third photoresist 27 is formed on the upper surface of the substrate 1 to remove the oxide film shell in the region where the diffusion region 29 and the second polysilicon layer 25 of the transistor contact each other. do. Next, after the third photoresist 27 is removed in FIGS. 2E and e ', a third polysilicon layer 31 is formed to form a storage electrode 33 in contact with the diffusion region of the transistor. Then, the field oxide film 35 is formed by a conventional selective oxidation method. After that, a transistor is formed by a normal MOS process to complete the DRAM cell.

As can be seen from the above description, the sheath-shaped plate electrode is surrounded by the oxide film shell and has a structure in contact with the buried diffusion region on the lower surface thereof. Therefore, the storage electrode is completely electrically insulated from the substrate, thereby eliminating the problem of the conventional trench capacitor. However, in order to form a voltage terminal for applying a predetermined voltage to the plate electrode, there is a problem in that a process of separately forming trenches is required, as shown in FIGS. Accordingly, an object of the present invention is to provide a semiconductor memory device capable of forming voltage terminals for plate electrodes in a semiconductor memory device having an HVSPC cell without forming a separate trench. Another object of the present invention is to provide a semiconductor memory device capable of manufacturing a capacitor having an increased capacitance in an easier process in a semiconductor memory device having an HVSPC cell. In order to achieve the object of the present invention as described above, a trench is formed in the well of the second conductivity type formed in the semiconductor substrate of the first conductivity type, and the voltage terminal for the plate electrode is formed on the upper surface of the well of the second conductivity type. It is characterized by. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3a-e is a manufacturing process diagram of a DRAM cell composed of an HVSPC cell according to the present invention, in particular showing a manufacturing process of a capacitor. In FIG. 3A, an oxide film 47 and a nitride film 49 are formed on the P-type semiconductor substrate 41 on which the P well 43 and the n well 45 are formed. In FIG. 3B, a photolithography process is performed to form a predetermined mask pattern, and then a trench 51 extending through the P well 43 region to the n well 45 is formed. P-type impurities are then implanted into the trench 51 to electrically insulate the trenches. As a result, a channel stop region 53 is formed in the P well region adjacent to the trench outer wall. In FIG. 3C, an oxide film is formed on the entire surface of the substrate to a thickness of about 300-100 kPa and then etched back. Thus, the oxide film 55 remains only on the sidewalls of the trench. In FIG. 3D, a first polycrystalline silicon layer is formed on the surface of the substrate, followed by an etching process, to form the plate electrode 57 by leaving the first polycrystalline silicon layer only on a side surface adjacent to the oxide film. Next, n-type impurities are implanted from the upper portion of the substrate to form an n + diffusion layer 59 in an n well region adjacent to the lower surface of the trench. The n + (59) diffusion layer serves to reduce the contact resistance between the plate electrode 57 and the substrate. When the first polysilicon is etched, an over-etching may occur and the substrate on the lower surface of the trench may be etched to a predetermined thickness. In FIG. 3E, a capacitor is completed by forming a dielectric film 61 made of Oxide-Nifride-Oxide (ONO) for a capacitor and a second polysilicon layer 63 serving as a storage electrode on the upper surface of the substrate. Here, the contact window is formed on the upper surface of the n well region, and then the patterned metal layer 70 is formed to form the voltage terminal of the plate electrode.

In an embodiment of the present invention, the first polysilicon layer is left only on the sidewalls of the trench when the first polysilicon layer is etched. However, in another embodiment of the present invention, an etching process is performed after forming a mask to fill the trench. The first polysilicon layer may be left on the sidewalls and the bottom surface of the trench. As described above, in the semiconductor memory device including the trench capacitor, the connection between the plate electrodes of the trench capacitor is implemented by using a well region in the semiconductor substrate. Accordingly, in the conventional HVSPC cell, a process of forming a trench is necessary to form a voltage terminal for the plate electrode. However, in the present invention, the plate voltage terminal can be formed in a much easier process by forming a contact window on the upper surface of the well region. Can be. As a result, there is an effect that can easily implement a high-density large capacity DRAM cell.

Claims (5)

10. A semiconductor memory device having a trench capacitor, the semiconductor memory device comprising: a first conductive type well and a first conductive type semiconductor substrate formed around the well and having a second conductive type type well opposite to the first conductive type type; A plurality of trenches deeper than the wells of the first conductivity type and shallower than the wells of the second conductivity type, an insulating film formed on the sidewalls of the trenches, and a second region in a predetermined region adjacent to the insulating film and adjacent to the insulating film. 12. A semiconductor memory device comprising a trench capacitor comprising a plate electrode in contact with a substrate corresponding to a conductive well and a voltage terminal formed in contact with an upper surface of the well of the second conductivity type. 2. The semiconductor memory device of claim 1, wherein the plate electrode is tubular. The semiconductor memory device of claim 1, wherein the plate electrodes are adjacent to each other at the bottom surface of the trench. 2. The trench capacitor of claim 1, further comprising a second conductive diffusion region doped at a higher concentration than the second conductive well concentration in a second conductivity type well region adjacent to the trench bottom surface. A semiconductor memory device. 2. The semiconductor memory device of claim 1, further comprising a first conductivity type diffusion region adjacent to the trench outer wall and having a higher concentration than the well concentration of the first conductivity type.