[go: up one dir, main page]

KR950021587A - DRAM device manufacturing method - Google Patents

DRAM device manufacturing method Download PDF

Info

Publication number
KR950021587A
KR950021587A KR1019930031849A KR930031849A KR950021587A KR 950021587 A KR950021587 A KR 950021587A KR 1019930031849 A KR1019930031849 A KR 1019930031849A KR 930031849 A KR930031849 A KR 930031849A KR 950021587 A KR950021587 A KR 950021587A
Authority
KR
South Korea
Prior art keywords
dram device
peripheral circuit
circuit region
forming
increase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019930031849A
Other languages
Korean (ko)
Inventor
황준
박상훈
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930031849A priority Critical patent/KR950021587A/en
Publication of KR950021587A publication Critical patent/KR950021587A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 디램소자의 제조방법에 관한 것으로서, 플레이트 전극형성을 위한 폴리실리콘층 패턴잉 후, 노출되는 주변회로 영역상의 산화막을 식각하지 않고 후속공정을 진행하여 디램소자의 셀영역과 주변회로 영역간의 단차증가를 방지하여, 공정여유도를 증가시키고, 후속 적층막들의 단차피복성을 향상시켜 공정수율 및 소자의 신뢰성이 증가된다.The present invention relates to a method of manufacturing a DRAM device, and after patterning a polysilicon layer for forming a plate electrode, a subsequent process is performed without etching an oxide film on an exposed peripheral circuit region, thereby forming a gap between a cell region and a peripheral circuit region of the DRAM element. By preventing the step increase, the process margin is increased, and the step coverage of the subsequent laminated films is improved to increase the process yield and the reliability of the device.

Description

디램소자 제조방법DRAM device manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

Claims (1)

디램소자의 플레이트 전극 형성을 위한 폴리실리콘 식각 공정 후, 디램소자의 주변회로 영역상의 산화막 식각공정을 건너뛰어 셀영역과 주변회로 영역간의 단차 증가를 방지할 수 있는 디램소자의 제조방법.A method of manufacturing a DRAM device, after the polysilicon etching process for forming a plate electrode of a DRAM device, to prevent an increase in a step difference between a cell region and a peripheral circuit region by skipping an oxide etching process on a peripheral circuit region of the DRAM device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930031849A 1993-12-31 1993-12-31 DRAM device manufacturing method Withdrawn KR950021587A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930031849A KR950021587A (en) 1993-12-31 1993-12-31 DRAM device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930031849A KR950021587A (en) 1993-12-31 1993-12-31 DRAM device manufacturing method

Publications (1)

Publication Number Publication Date
KR950021587A true KR950021587A (en) 1995-07-26

Family

ID=66853187

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930031849A Withdrawn KR950021587A (en) 1993-12-31 1993-12-31 DRAM device manufacturing method

Country Status (1)

Country Link
KR (1) KR950021587A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100419748B1 (en) * 1996-09-06 2004-06-04 주식회사 하이닉스반도체 Method of manufacturing semiconductor device
KR100810060B1 (en) * 2006-04-14 2008-03-05 주식회사 하이닉스반도체 Semiconductor memory device and driving method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100419748B1 (en) * 1996-09-06 2004-06-04 주식회사 하이닉스반도체 Method of manufacturing semiconductor device
KR100810060B1 (en) * 2006-04-14 2008-03-05 주식회사 하이닉스반도체 Semiconductor memory device and driving method thereof
US7710809B2 (en) 2006-04-14 2010-05-04 Hynix Semiconductor Inc. Self refresh operation of semiconductor memory device
US8000164B2 (en) 2006-04-14 2011-08-16 Hynix Semiconductor Inc. Self refresh operation of semiconductor memory device
US8000163B2 (en) 2006-04-14 2011-08-16 Hynix Semiconductor Inc. Self refresh operation of semiconductor memory device

Similar Documents

Publication Publication Date Title
KR890008987A (en) Layer Structure of Memory Cell for Dynamic Random Access Memory Device and Manufacturing Method Thereof
KR920008929A (en) Semiconductor Memory and Manufacturing Method
KR980005441A (en) Manufacturing Method of Semiconductor Device
KR910007159A (en) MOS semiconductor device
KR950021587A (en) DRAM device manufacturing method
KR960005941A (en) Semiconductor device
KR950025874A (en) Method for manufacturing gate electrode of semiconductor device
KR980005304A (en) Method for Forming Photosensitive Film of Semiconductor Device
KR960019576A (en) Method of forming gate insulating film of ROM
KR970030343A (en) Electrode of semiconductor memory device and method of forming same
KR960002825A (en) Capacitor Manufacturing Method of Semiconductor Device
KR940016735A (en) Method for manufacturing metal wiring of semiconductor device
KR960002849A (en) Capacitor Manufacturing Method of Semiconductor Device
KR970054517A (en) Manufacturing Method of Thin Film Transistor
KR960043176A (en) Capacitor Manufacturing Method
KR910020902A (en) DRAM Cell Manufacturing Method
KR950025999A (en) Capacitor Manufacturing Method
KR940001444A (en) Stacked Gate Cell Manufacturing Method
KR970053985A (en) Capacitor Manufacturing Method of Semiconductor Device
KR960026177A (en) Semiconductor device manufacturing method
KR970054151A (en) Capacitor Manufacturing Method of Semiconductor Device
KR940003034A (en) Semiconductor Capacitor Manufacturing Method
KR950034778A (en) Semiconductor device and manufacturing method
KR920015545A (en) Stack Capacitor Cell Manufacturing Method
KR960036142A (en) Thin film transistor structure and manufacturing method

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19931231

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid