KR950033862A - Interface method and device with RAM - Google Patents
Interface method and device with RAM Download PDFInfo
- Publication number
- KR950033862A KR950033862A KR1019950006173A KR19950006173A KR950033862A KR 950033862 A KR950033862 A KR 950033862A KR 1019950006173 A KR1019950006173 A KR 1019950006173A KR 19950006173 A KR19950006173 A KR 19950006173A KR 950033862 A KR950033862 A KR 950033862A
- Authority
- KR
- South Korea
- Prior art keywords
- ram
- cell
- data
- address
- words
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/04—Addressing variable-length words or parts of words
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0607—Interleaved addressing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4494—Execution paradigms, e.g. implementations of programming paradigms data driven
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/13—Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
- H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Mathematical Physics (AREA)
- Memory System (AREA)
- Dram (AREA)
- Television Signal Processing For Recording (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
본 발명은 RAM으로부터 RAM의 소정의 고정 버스트 길이 N보다 M개의 워드를 억세스하는 것을 포함하여 메모리의 어드레싱 및 엑세싱하는 많은 기술들에 관한 것이다. 또한 2차원 영상과 관련된 데이타 워드를 저장 및 검색하기 위하여 동적 랜덤 억세스 메모리(DRAM)를 억세스하는 방법 및 가변 폭 데이타를 어드레싱하는데 사용되는 고정 비트 수를 가지며 폭 정의 필드 및 어드레스 필드를 갖는 고정 폭을 갖는 워드를 제공하는 과정도 또한 개시되어 있다. 또한 프레임 또는 필드로 구성된 인코드된 비디오 데이타의 버퍼링을 제어하는 방법도 개시되어 있다. 이 방법은 입력하는 디코드된 프레임 각각의 화상 번호를 결정하는 단계, 임의의 시간에 예기된 화상 번호를 결정하는 단계 및 그 화상 번호가 프레젠테이션번호상에 또는 그 이후에 있는 경우 버퍼를 준비가 되었다고 표시하는 단계를 포함하고 있다. 마지막으로, 별도의 어드레스 발생기가 RAM인터페이스가 RAM을 어드레스하는데 필요로 하는 어드레스를 발생하는 버스를 RAM에 접속하는 RAM인터페이스를 개시하고 있다. 어드레스 발생기는 2선식 인터페이스를 통하여 RAM인터페이스와 통신한다.The present invention is directed to a number of techniques for addressing and accessing memory, including accessing M words from RAM, rather than a predetermined fixed burst length N of RAM. In addition, a method of accessing a dynamic random access memory (DRAM) for storing and retrieving data words associated with a 2D image, and a fixed width having a fixed width number and an address field with a fixed number of bits used to address variable width data. The process of providing a word having is also disclosed. Also disclosed is a method of controlling the buffering of encoded video data consisting of frames or fields. The method determines the picture number of each of the input decoded frames, determines the expected picture number at any time, and indicates that the buffer is ready if the picture number is on or after the presentation number. It includes the steps. Finally, a separate address generator discloses a RAM interface that connects a bus to RAM that generates an address that the RAM interface needs to address the RAM. The address generator communicates with the RAM interface via a two-wire interface.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명의 싱크로너스 DRAM 억세스 방법을 사용한 장치의 시스템 블럭선도, 제2도는 제1도의 상태머신에 의해 수신된 고레벨 명령과, 그에 의해 발생된 저레벨 명령간의 상호관계를 나타낸 도면, 제3도는 제1도의 DRAM의 구성을 도식적으로 표현한 도면.FIG. 1 is a system block diagram of an apparatus using the synchronous DRAM access method of the present invention, FIG. 2 is a diagram showing the correlation between the high level commands received by the state machine of FIG. 1 and the low level commands generated by it, and FIG. A diagrammatic representation of the configuration of the DRAM of FIG.
Claims (28)
Applications Claiming Priority (11)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9405914.4 | 1994-03-24 | ||
| GB9405914A GB9405914D0 (en) | 1994-03-24 | 1994-03-24 | Video decompression |
| GB9415365A GB9415365D0 (en) | 1994-07-29 | 1994-07-29 | Method for accessing ram |
| GB9415387A GB9415387D0 (en) | 1994-07-29 | 1994-07-29 | Method and apparatus for addressing memory |
| GB9415391A GB9415391D0 (en) | 1994-07-29 | 1994-07-29 | Method for accessing banks of dram |
| GB9503964 | 1995-02-28 | ||
| GB9503964A GB2287808B (en) | 1994-03-24 | 1995-02-28 | Method and apparatus for interfacing with ram |
| GB9415365.7 | 1995-02-28 | ||
| GB9503964.0 | 1995-02-28 | ||
| GB9415391.3 | 1995-02-28 | ||
| GB9415387.1 | 1995-02-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950033862A true KR950033862A (en) | 1995-12-26 |
| KR100275427B1 KR100275427B1 (en) | 2000-12-15 |
Family
ID=27517238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950006173A Expired - Lifetime KR100275427B1 (en) | 1994-03-24 | 1995-03-23 | Interface method and device with RAM |
Country Status (2)
| Country | Link |
|---|---|
| JP (6) | JPH0855060A (en) |
| KR (1) | KR100275427B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100447134B1 (en) * | 1996-12-28 | 2006-02-28 | 엘지전자 주식회사 | DRAM controller with adjustable number of access data bits and low power consumption |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100442296B1 (en) * | 2002-03-13 | 2004-07-30 | 주식회사 하이닉스반도체 | Method for Assigning Frame Memory to Compensate Movement of Half-Pel |
| US7469068B2 (en) | 2004-05-27 | 2008-12-23 | Seiko Epson Corporation | Method and apparatus for dimensionally transforming an image without a line buffer |
| US10380029B2 (en) | 2016-11-24 | 2019-08-13 | Samsung Electronics Co., Ltd. | Method and apparatus for managing memory |
-
1995
- 1995-03-23 KR KR1019950006173A patent/KR100275427B1/en not_active Expired - Lifetime
- 1995-03-24 JP JP7090019A patent/JPH0855060A/en active Pending
- 1995-07-18 JP JP7202793A patent/JPH08179984A/en active Pending
- 1995-07-18 JP JP7202752A patent/JPH08241066A/en active Pending
- 1995-07-18 JP JP7202744A patent/JPH08179983A/en active Pending
- 1995-07-18 JP JP20269195A patent/JP3741464B2/en not_active Expired - Lifetime
-
2000
- 2000-09-22 JP JP2000288305A patent/JP2001128108A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100447134B1 (en) * | 1996-12-28 | 2006-02-28 | 엘지전자 주식회사 | DRAM controller with adjustable number of access data bits and low power consumption |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08241066A (en) | 1996-09-17 |
| JPH08179984A (en) | 1996-07-12 |
| JPH08202614A (en) | 1996-08-09 |
| JP3741464B2 (en) | 2006-02-01 |
| JPH08179983A (en) | 1996-07-12 |
| KR100275427B1 (en) | 2000-12-15 |
| JPH0855060A (en) | 1996-02-27 |
| JP2001128108A (en) | 2001-05-11 |
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