[go: up one dir, main page]

KR970000652B1 - EPROM cell and its manufacturing method using trench isolation - Google Patents

EPROM cell and its manufacturing method using trench isolation Download PDF

Info

Publication number
KR970000652B1
KR970000652B1 KR1019880007986A KR880007986A KR970000652B1 KR 970000652 B1 KR970000652 B1 KR 970000652B1 KR 1019880007986 A KR1019880007986 A KR 1019880007986A KR 880007986 A KR880007986 A KR 880007986A KR 970000652 B1 KR970000652 B1 KR 970000652B1
Authority
KR
South Korea
Prior art keywords
region
layer
cell
oxide film
poly
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019880007986A
Other languages
Korean (ko)
Other versions
KR900001023A (en
Inventor
이상수
Original Assignee
엘지반도체 주식회사
문정환
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지반도체 주식회사, 문정환 filed Critical 엘지반도체 주식회사
Priority to KR1019880007986A priority Critical patent/KR970000652B1/en
Priority to NL8901545A priority patent/NL194183C/en
Priority to DE3920451A priority patent/DE3920451C2/en
Priority to FR8908469A priority patent/FR2633777B1/en
Priority to JP1166474A priority patent/JPH02119185A/en
Publication of KR900001023A publication Critical patent/KR900001023A/en
Priority to US07/804,478 priority patent/US5223731A/en
Priority to US08/051,621 priority patent/US5296397A/en
Application granted granted Critical
Publication of KR970000652B1 publication Critical patent/KR970000652B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/686—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection using hot carriers produced by avalanche breakdown of PN junctions, e.g. floating gate avalanche injection MOS [FAMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)

Abstract

내용 없음.No content.

Description

트랜치 분리를 이용한 EPROM 셀 및 이의 제조방법EPROM cell and its manufacturing method using trench isolation

제1도(a),(b)는 종래의 EPROM 셀을 나타내는 단면도.1 (a) and (b) are cross-sectional views showing conventional EPROM cells.

제2도는 종래 EPROM 셀의 평면도.2 is a plan view of a conventional EPROM cell.

제3a도는 본 발명의 EPROM 셀의 횡단면도.3A is a cross sectional view of an EPROM cell of the present invention.

제3b도는 본 발명의 EPROM 셀의 종단면도.3b is a longitudinal sectional view of the EPROM cell of the present invention;

제4도는 본 발명의 EPROM 셀의 평면도.4 is a plan view of the EPROM cell of the present invention.

제5도(a)~(g)는 본 발명에 따른 EPROM 셀의 제조방법을 나타낸 단면도.5 (a) to 5 (g) are cross-sectional views showing a method for manufacturing an EPROM cell according to the present invention.

제6도(a)~(r)은 제5도에 도시된 제조방법을 더욱 상세히 나타낸 사시도이다.6 (a) to 6 (r) are perspective views showing the manufacturing method shown in FIG. 5 in more detail.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

S : 기판 1 : 플로팅 게이트S: Substrate 1: Floating Gate

2,11 : 컨트롤 게이트 3 : 제1게이트 산화막2,11: control gate 3: first gate oxide film

4 : 인터폴리 산화막 5 : 전계 산화막4: interpoly oxide film 5: electric field oxide film

6 : 소스 7 : 드레인6: source 7: drain

10 : 트랜치 격리층 12 : 제1산화막10: trench isolation layer 12: first oxide film

13 : 폴리-I층 20 : 매립 접촉부13: poly-I layer 20: buried contact

21 : 제2산화막 22 : 폴리-II층21: second oxide film 22: poly-II layer

23 : BPSG 산화막 24 : 금속막23 BPSG oxide film 24 Metal film

25 : 패시베이션막 31 : 버퍼 산화막25 passivation film 31 buffer oxide film

32 : 질화층32: nitride layer

본 발명은 트랜치 분리를 사용한 EPROM 셀 및 이의 제조방법에 관한 것으로서, 특히 트랜치 분리를 이용하여 플로팅 게이트로 폴리-I층(polycrystalline-I layer)을, 컨트롤 게이트로 매립 접촉부를 통해 N형 확산영역과 연결된 폴리-II층(polycrystalline-II layer)을 사용하는 EPROM 셀 및 이의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an EPROM cell using a trench isolation and a method of manufacturing the same, and in particular, a polycrystalline I layer as a floating gate using a trench isolation and an N-type diffusion region through a buried contact as a control gate. The present invention relates to an EPROM cell using a connected polycrystalline-II layer and a method of manufacturing the same.

EPROM은 기억소자로 사용할 경우 셀을 프로그램시켜 플로팅 게이트에 전자가 축적된 상태 즉, 오프상태와 상기 셀을 자외선으로 소거하여 플로팅 게이트의 전자가 방출된 상태 즉 온상태인 두 상태를 이용하여 기억소자로 사용된다. 더욱 상세히 설명하면, 메모리소자로 사용된 트랜지스터의 드레인영역에서 발생된 열 전자를 산화막중의 매입된 플로팅 게이트에 주입시켜 상기 트랜지스터를 프로그램하고(이때 기록양은 컨트롤 게이트로서 제어한다), 프로그램한 것을 소거하는 경우에는 패키지 상부에 설치된 창을 통하여 자외선을 조사하여 플로팅 게이트로부터 전자를 방출시켜 행한다.When used as a memory device, an EPROM is a memory device that uses a state in which electrons are accumulated in a floating gate by programming a cell, that is, an off state and an electron is emitted in a floating gate by erasing the cell with ultraviolet rays, that is, an on state. Used as More specifically, the transistors are programmed by injecting hot electrons generated in the drain region of the transistor used as the memory element into the buried floating gate in the oxide film (the write amount is controlled as the control gate), and the programmed one is erased. In this case, ultraviolet rays are irradiated through a window provided on the upper portion of the package to emit electrons from the floating gate.

이와 같이 동작되도록 형성되는 종래 EPROM셀은 제1도(a)에 나타낸 단면도와 같이 2중 구조의 폴리층 (1),(2)을 포함한다. 제2도는 상기 EPROM셀의 레이아웃을 나타낸 도면으로서 제1도(a),(b)와 동일부분은 같은 부호로 표시되어 있다. 또한 제2도에서 a-a'선을 따라 취한 횡단면도는 제1도(a)이며, 동도에서 b-b'선을 따라 취한 종단면도는 제1도(b)이다. 제1도 및 제2도와 같은 구조에 있어서 제1폴리층(1)은 플로팅 게이트로서 사용되고 제2폴리층(2)은 컨트롤 게이트로서 각각 사용되고 있으며, 셀과 셀은 전계 산화막(5)에 의해 분리되어 있다. 또한, 셀의 채널길이 방향에서 본 단면도를 나타낸 제1도(b)에 있어서, 참조번호 6,7,은 각각 셀의 소스와 드레인을 나타낸다. 제1도(a),(b)에 나타낸 구조로 형성된 EPROM 셀에 있어서, 얇게 형성된 제1게이트 산화막(3)과 인터폴리 산화막(4)의 두께 및 품질이 상기 형성된 셀의 신뢰성에 큰 영향을 미치게 된다.The conventional EPROM cell formed to be operated in this way includes a poly-layer (1), (2) having a double structure as shown in the cross-sectional view shown in FIG. 2 is a diagram showing the layout of the EPROM cell, in which the same parts as in FIGS. 1 (a) and (b) are denoted by the same reference numerals. In Fig. 2, the cross-sectional view taken along the line a-a 'is Fig. 1 (a), and the longitudinal cross-sectional view taken along the line b-b' is Fig. 1 (b). In the structure shown in FIGS. 1 and 2, the first poly layer 1 is used as the floating gate and the second poly layer 2 is used as the control gate, respectively. The cell and the cell are separated by the field oxide film 5. It is. In Fig. 1 (b) showing a cross-sectional view of the cell in the channel length direction, reference numerals 6 and 7 denote the source and the drain of the cell, respectively. In the EPROM cell formed with the structures shown in FIGS. 1A and 1B, the thickness and quality of the thinly formed first gate oxide film 3 and the interpoly oxide film 4 have a great influence on the reliability of the formed cell. Go crazy.

셀을 프로그램시키기 전의 문턱전압이 작은 상태와 프로그램시킨 후의 문턱전압이 큰 상태의 2가지 상태를 이용하는 EPROM은 그 셀을 프로그램시키기 위해서 상기 구조에 따라 컨트롤 게이트(2)와 드레인(7)에 높은 전압을 인가하여 셀의 채널 드레인 근처에서 열전자의 애벌란쉬 주입에 의해 플로팅 게이트(1)에 전자를 축적시킨다. 이와 같이 전자가 축적되면 셀을 프로그램되며, 이때의 셀의 문턱전압은 커지게 된다. 따라서 셀이 프로그램되기 전과 후의 문턱전압의 차가 생기며 이 차를 이용하여 기억소자로 사용한다.The EPROM, which uses two states of a low threshold voltage before programming a cell and a high threshold voltage after programming, has a high voltage on the control gate 2 and the drain 7 according to the above structure in order to program the cell. Is applied to accumulate electrons in the floating gate 1 by avalanche injection of hot electrons near the channel drain of the cell. As the electrons accumulate in this way, the cell is programmed, and the threshold voltage of the cell increases. Therefore, there is a difference between the threshold voltage before and after the cell is programmed, and this difference is used as the memory device.

그러나 상기 기술된 종래의 EPROM은 양질의 인터폴리 산화막 성장 및 그 두께 조절이 중요 요소로 작용되어 인터폴리 산화막의 두께는 제1폴리층과 제2폴리층간 형성되는 용량값에 관계되고 인터폴리 산화막을 성장시킬때 제2게이트 산화막이 동시에 성장되므로 그 두께 조절에 어려움이 있으며 또한, 제1폴리층의 가장자리 부분에서 제1폴리층으로 누설전류가 발생하여 제품의 신뢰성을 감소시키는 문제가 있다.However, in the conventional EPROM described above, the quality of interpoly oxide film growth and its thickness control are important factors so that the thickness of the interpoly oxide film is related to the capacitance value formed between the first poly layer and the second poly layer, Since the second gate oxide film is grown at the same time as it grows, it is difficult to control the thickness thereof. In addition, leakage current is generated from the edge of the first poly layer to the first poly layer, thereby reducing the reliability of the product.

본 발명의 목적은 상기 한 문제점을 해결하는 것으로 트랜치 분리기술을 사용하여 고신뢰성을 갖도록 한 EPROM 셀 및 이의 제조방법을 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to provide an EPROM cell and a method of manufacturing the same having high reliability by using a trench isolation technique.

본 발명의 목적에 따라 형성된 본 발명의 EPROM 셀의 단면구조를 제3도(a)와 (b)에 횡단면도와 종단면도로서 나타내었다. 제3도(a),(b)에 나타낸 바와 같이 본 발명은 전계 산화막(5)으로 분리되는 셀을 갖는 EPROM에 관한 것으로, 트랜치 격리층(10)은 분리된 셀영역내의 컨트롤 게이트(11)와, 동시에 형성된 셀의 제1게이트 산화막 및 인터게이트 산화막(12)에 형성된 단일의 폴리-I층의 플로팅 게이트(13)를 포함하여 형성된 것을 특징으로 한다. 즉, 본 발명은 상기 언급한 문제점을 해결하기 위해 트랜치 분리기술을 사용하여 컨트롤 게이트를 플로팅 게이트에서 절연시키는 제1게이트 산화막 및 인터게이트 산화막을 한 공정으로 동시에 성장시키고 폴리-I과 외부 접촉을 위해 형성된 폴리-II 사이를 두꺼운 인터폴리 산화막으로 성장시켜 신뢰성이 높은 EPROM 셀을 제조한 것이다. 제3도와 같은 단면구조로 형성되는 본 발명에 따른 EPROM 셀의 레이아웃을 제4도에 나타내었으며 제4도와 제3도의 동일부호는 동일한 부분을 나타내고 있고, 제4도의 a-a'선을 따라 취한 횡단면도와 b-b'선을 따라 취한 종단면도는 각각 제3도(a)와 (b)이다.The cross-sectional structure of the EPROM cell of the present invention formed in accordance with the object of the present invention is shown in Figures 3 (a) and (b) as a cross sectional view and a longitudinal cross sectional view. As shown in Figs. 3A and 3B, the present invention relates to an EPROM having a cell separated by an electric field oxide film 5, wherein the trench isolation layer 10 comprises a control gate 11 in the separated cell region. And a floating gate 13 of a single poly-I layer formed on the first gate oxide film and the intergate oxide film 12 of the simultaneously formed cell. That is, in order to solve the above-mentioned problems, the present invention simultaneously grows the first gate oxide and the intergate oxide to insulate the poly-I and the external contact by using a trench isolation technique to insulate the control gate from the floating gate. A highly reliable EPROM cell was manufactured by growing a thick interpoly oxide film between poly-II formed. The layout of the EPROM cell according to the present invention, which has a cross-sectional structure as shown in FIG. 3, is shown in FIG. 4, and the same reference numerals in FIG. 4 and FIG. The longitudinal cross-sectional view taken along the cross-sectional view and the b-b 'line is the third view (a) and (b), respectively.

본 발명의 EPROM은 제3도(a)에 나타낸 바와 같이 N형으로 강하게 도핑시킨 실리콘을 컨트롤 게이트(11)로 사용하고 폴리-I층은 플로팅 게이트(13)로 사용하고 트랜치영역을 두꺼운 산화막으로 채워 트랜치 격리층으로 만든뒤 소오스와 드레인영역으로 형성된 셀의 채널부분을 컨트롤 게이트와 완전히 분리시키고 제1게이트 산화막 및 인터게이트 산화막으로서 동시에 사용되는 얇은 산화막(12)을 형성시킨 후 그 위에 폴리 -I층을 형성하여 플로팅 게이트로 사용하고 그 위에 두꺼운 인터폴리 산화막을 형성시킨 후 기억소자에 적용시 필요한 워드라인(word line)을 만들기 위해 컨트롤 게이트 부분에 매립 접촉부(20)을 만든 후 폴리-II층(22)을 적층시켜 셀을 제조하였다.As shown in FIG. 3A, the EPROM of the present invention uses silicon heavily doped with N-type as the control gate 11, the poly-I layer as the floating gate 13, and the trench region as a thick oxide film. Fill the trench isolation layer, and completely separate the channel portion of the cell formed of the source and drain regions from the control gate, and form a thin oxide film 12 used simultaneously as the first gate oxide film and the intergate oxide film. After forming a layer to be used as a floating gate and forming a thick interpoly oxide layer thereon, a buried contact portion 20 is formed in the control gate to form a word line necessary for application to a memory device, and then a poly-II layer. (22) was laminated to prepare a cell.

본 발명의 EPROM 셀의 동작은 셀을 프로그램시키기 위해 매립 접촉부를 통해 N+형 확산영역과 연결된 폴리-II층으로 제조된 컨트롤 게이트(11)에 고전압, 약 12V정도를 인가하고 제3도(b)에 나타낸 드레인(7)에 고전압을 인가하여 셀의 드레인과 소오스간의 채널로부터 열전자의 애벌란쉬 주입에 의한 방법으로 전자를 플로팅 게이트(13)에 축적시킨다. 이와 같이 프로그램된 셀의 높은 문턱전압과 프로그램되지 않은 셀의 낮은 문턱전압의 2가지 상태를 이용하여 기억소자로서 사용할 수 있다.The operation of the EPROM cell of the present invention applies a high voltage, about 12 V, to a control gate 11 made of a poly-II layer connected to an N + type diffusion region through a buried contact to program the cell and FIG. A high voltage is applied to the drain 7 shown in Fig. 6) to accumulate electrons in the floating gate 13 by avalanche injection of hot electrons from the channel between the drain and the source of the cell. The two states of the high threshold voltage of the programmed cell and the low threshold voltage of the unprogrammed cell can be used as the memory device.

상기와 같이 본 발명에 따른 EPROM 셀은 폴리-I층과 폴리-II층 상이의 산화막 두께를 제2산화막의 두께에 관계없이 독립적으로 두껍게 성장시킬 수 있으므로 종래의 셀에서 나타나는 제1폴리층의 가장자리 부분에서 제2폴리층 부분으로의 누설전류에 의한 취약성을 완전히 제거하여 고신뢰성을 갖는 EPROM 셀을 제조할 수 있으며, 또한 이를 사용하여 고신뢰성 EPROM 기억소자 및 논리소자를 제조할 수 있는 효과가 있다. 제5도(a)~(g)는 본 발명의 EPROM 셀의 제조방법을 단계적으로 나타낸 단면도로서, 통상적인 방법에 의해 셀의 제조를 위해 전계 산화막으로 분리된 셀영역을 갖는 기판(S)상에 버퍼 산화막(31)과 질화층(32)을 적층하고(제5도(a)) 트랜치 마스크를 사용한 트랜치 에칭을 행하여 제5도(b)와 같은 구조를 얻는다.As described above, the EPROM cell according to the present invention can grow independently the thickness of the oxide film between the poly-I layer and the poly-II layer independently of the thickness of the second oxide film. It is possible to manufacture a highly reliable EPROM cell by completely eliminating the vulnerability due to leakage current from the portion to the second poly layer portion, and also has the effect of manufacturing a highly reliable EPROM memory device and a logic device using the same. . 5A to 5G are cross-sectional views showing a method of manufacturing an EPROM cell of the present invention in a stepwise manner, on a substrate S having a cell region separated by an electric field oxide film for manufacturing the cell by a conventional method. The buffer oxide film 31 and the nitride layer 32 are stacked in (Fig. 5 (a)) and trench etching using a trench mask is performed to obtain a structure as in Fig. 5 (b).

트랜치영역에 산화막을 채우고 제5도(b)의 질화층의 최종점(end point)(P)으로 에칭하고 버퍼 산화막(31)능 고립되게 한 후에 질화층을 스트립하여 제거한다(제5도(c)). 계속해서 셀 마스크를 사용하여 셀의 컨트롤 게이트 부분을 N형으로 강하게 도핑하여 제5도(d)와 같은 구조를 얻는다. 이어서 버퍼 산화막(buffer oxide)을 제거하고, 게이트 산화막(12)을 증착하고(제5도(e),(f)) 폴리-I층(13)을 증착하고, 이어서 폴리-I층을 마스킹하여 폴리-I층의 영역을 형성하고 폴리층간 누설전류에 의한 신뢰성 문제를 해결하기 위해 폴리-I층상에 두꺼운 산화막을 성장시켜 인터폴리 산화막(21)을 형성한다.The trench region is filled with an oxide film, etched to the end point P of the nitride layer of FIG. 5 (b), so that the buffer oxide film 31 is isolated, and the nitride layer is stripped and removed. c)). Subsequently, the control gate portion of the cell is strongly doped to N type using a cell mask to obtain a structure as shown in FIG. The buffer oxide is then removed, the gate oxide 12 is deposited (FIGS. 5 (e), (f)) and the poly-I layer 13 is deposited, followed by masking the poly-I layer. In order to form the region of the poly-I layer and to solve the reliability problem caused by the leakage current between the poly-layers, an interpoly oxide film 21 is formed by growing a thick oxide film on the poly-I layer.

그 다음 매립접촉부(20)를 만들고 폴리-II층을 증착하고 마스킹하여 기억소자의 워드라인용 컨트롤 게이트(11) 부분을 정의한다. 이어 종래의 방법과 같이 N+마스크를 사용한 N+이온주입을 하여 제3b도에서 도시되어 각각 6과 7로 나타낸 N형으로 도핑된 소오스/드레인을 형성한다. BPSG 산화막(23)을 형성되고, 접촉 마스킹후 금속막(24)이 증착되고 패시베이션막(25)이 형성된다. 종국에서는 제5도의 (g)와 같은 구조의 셀이 완성된다.Then, the buried contact portion 20 is formed, and the poly-II layer is deposited and masked to define the word gate control gate 11 portion of the memory device. Subsequently, N + ion implantation using an N + mask is performed as in the conventional method to form a source / drain doped with N-types shown in FIGS. 3B and 6 and 7, respectively. A BPSG oxide film 23 is formed, a metal film 24 is deposited after contact masking, and a passivation film 25 is formed. In the end, a cell having a structure as shown in FIG. 5 (g) is completed.

제6도(a)~(r)은 상기한 제5도의 제조방법들을 더욱 알기 쉽게 나타낸 사시도로서, 이들을 참조하여 제5도의 제조방법을 상세히 설명하면 다음과 같다.6 (a) to (r) are perspective views showing the manufacturing method of FIG. 5 more clearly, and the manufacturing method of FIG. 5 will be described in detail with reference to the following.

우선, 반도체기판의 셀영역상에 버퍼 산화막과 질화층을 적층하고, 이 버퍼 산화막과 질화층 위에 트랜치 마스크를 적층한 후, 트랜치 마스크로 에칭하여 트랜치영역을 형성하며, 이렇게 형성된 트랜치영역내에 산화막을 채움으로써, 셀영역내를 두개의 영역으로 나누는 트랜치 격리층(10)을 형성한다[제6도(a)~(b)].First, a buffer oxide film and a nitride layer are laminated on the cell region of the semiconductor substrate, and a trench mask is laminated on the buffer oxide film and the nitride layer, and then, a trench mask is formed by etching with a trench mask, and an oxide film is formed in the trench region thus formed. By filling, a trench isolation layer 10 is formed which divides the inside of the cell region into two regions (Figs. 6 (a) to (b)).

그리고나서, 셀영역의 한쪽 영역내에 트랜치 격리층(10)과 인접하여 소오스/드레인(6,7)을 형성하고[제6도(c)~(f)], 셀영역의 다른 한쪽 영역내에 트랜치 격리층(10)과 인접하여 컨트롤 게이트(11)을 형성한다[제6도(g)~(h)].Then, the source / drains 6 and 7 are formed adjacent to the trench isolation layer 10 in one region of the cell region (Fig. 6 (c) to (f)), and the trench is formed in the other region of the cell region. The control gate 11 is formed adjacent to the isolation layer 10 (Figs. 6 (g) to (h)).

그후, 컨트롤 게이트(11) 위의 일부를 제외한 셀영역 위에 제1산화막(12)을 형성하고[제6도(i)], 적어도 소오스/드레인(6,7,)의 상부를 포함하는 제1산화막(12) 위에 폴리-I층(13)을 형성하고나서[제6도(j)~(l)], 폴리 I층(13)을 둘러싸는 제2산화막(21)을 형성한다[제6도(m)~(n)].Thereafter, a first oxide film 12 is formed on the cell region except for a portion on the control gate 11 (FIG. 6 (i)), and includes at least the top of the source / drain 6,7. After forming the poly-I layer 13 on the oxide film 12 [FIG. 6 (j)-(l)], a second oxide film 21 surrounding the poly I layer 13 is formed [sixth Degrees (m) to (n)].

제2산화막(21)을 둘러싸고 컨트롤 게이트(11)와 전기적으로 접촉하도록 하는 폴리-II층(22)을 형성함으로써[제6도(o)~(q)], 마지막으로 셀이 완성된다[제6도(R)].By forming the poly-II layer 22 which surrounds the second oxide film 21 and makes electrical contact with the control gate 11 [FIG. 6 (o) to (q)], the cell is finally completed. 6 degrees (R)].

Claims (6)

반도체기판상에 전계 산화막에 의해 분리된 셀영역을 갖는 EPROM 셀에 있어서; 상기 셀영역을 분리하도록 상기 셀영역내에 트랜치 형태로 형성된 트랜치 격리층; 상기 분리된 셀영역의 한쪽에 트랜치 격리층과 인접하여 형성된 드레인영역; 상기 분리된 셀영역의 한쪽에 트랜치 격리층과 인접하고 상기 드레인영역과 떨어져 형성된 소오스영역; 상기 분리된 셀영역의 다른 한쪽내의 상기 트랜치 격리층과 인접하게 형성되어 플로팅 게이트를 제어하는 컨트롤 게이트영역; 상기 컨트롤 게이트영역의 일부만 제외하고 상기 셀영역 위에 형성되는 제1절연막; 상기 제1절연막 위에 부분적으로 형성되어 플로팅 게이트를 형성하는 폴리-I층; 상기 폴리-I층을 둘러싸서 형성된 제2절연막; 및 노출된 전체 표면위에 형성되어 상기 콘트롤 게이트영역의 부분과 전기적으로 접속되는 폴리-II층을 포함하는 것을 특징으로 하는 트랜치 분리를 이용한 EPROM 셀.An EPROM cell having a cell region separated by an electric field oxide film on a semiconductor substrate; A trench isolation layer formed in a trench in the cell region to separate the cell region; A drain region formed adjacent to a trench isolation layer on one side of the separated cell region; A source region adjacent to a trench isolation layer and spaced apart from the drain region on one side of the separated cell region; A control gate region formed adjacent to the trench isolation layer in the other side of the separated cell region to control a floating gate; A first insulating layer formed on the cell region except for a part of the control gate region; A poly-I layer partially formed on the first insulating layer to form a floating gate; A second insulating layer formed to surround the poly-I layer; And a poly-II layer formed over the entire exposed surface and electrically connected to a portion of the control gate region. 반도체기판상에 전계 산화막에 의해 셀영역을 갖는 EPROM 셀 제조방법에 있어서; 상기 셀영역내를 두개의 영역으로 나누는 트랜치 격리층을 형성하는 단계; 상기 셀영역의 한쪽 영역내에 트랜치 격리층과 인접하여 소오스영역과 드레인영역을 형성하는 단계; 상기 셀영역의 다른 한쪽 영역내에 트랜치 격리층과 인접하여 컨트롤 게이트영역을 형성하는 단계; 상기 컨트롤 게이트영역 위의 일부를 제외한 상기 셀영역 위에 제1절연막을 형성하는 단계; 적어도 상기 소오스영역 및 드레인영역의 상부를 포함하는 상기 제1절연막 위에 폴리-I층을 형성하는 단계; 상기 폴리-I층을 둘러싸는 제2절연막을 형성하는 단계; 및 상기 제2절연막을 둘러싸고 상기 컨트롤 게이트영역과 전기적으로 접촉하도록 하는 폴리-II층을 형성하는 단계를 포함하는 것을 특징으로 하는 트랜치 분리를 이용한 EPROM 셀의 제조방법.A method for manufacturing an EPROM cell having a cell region by an electric field oxide film on a semiconductor substrate; Forming a trench isolation layer dividing the cell region into two regions; Forming a source region and a drain region adjacent to the trench isolation layer in one region of the cell region; Forming a control gate region adjacent the trench isolation layer in the other region of the cell region; Forming a first insulating layer on the cell region except a portion of the control gate region; Forming a poly-I layer on the first insulating layer including at least an upper portion of the source region and the drain region; Forming a second insulating film surrounding the poly-I layer; And forming a poly-II layer surrounding the second insulating layer to be in electrical contact with the control gate region. 제1항에 있어서, 상기 트랜치 격리층을 산화막으로 형성하는 것을 특징으로 하는 트랜치 분리를 이용한 EPROM 셀.The EPROM cell using trench isolation according to claim 1, wherein the trench isolation layer is formed of an oxide film. 제1항에 있어서, 상기 폴리-I층은 적어도 상기 소오스영역 및 상기 드레인영역 위에 형성된 상기 제1절연막을 둘러싸고 형성되는 것을 특징으로 하는 트랜치 분리를 이용한 EPROM 셀.The EPROM cell of claim 1, wherein the poly-I layer is formed surrounding at least the first insulating layer formed on at least the source region and the drain region. 제2항에 있어서, 상기 트랜치 격리층을 형성하는 단계는 : 상기 셀영역상에 버퍼 산화막과 질화층을 적층하는 단계, 상기 버퍼 산화막과 질화층 위에 트랜치 마스크를 적층하는 단계, 상기 트랜치 마스크로 에칭하여 트랜치영역을 형성하는 단계, 상기 형성된 트랜치영역내에 산화막을 채우는 단계를 포함하는 것을 특징으로 하는 트랜치 분리를 이용한 EPROM 셀의 제조방법.The method of claim 2, wherein the forming of the trench isolation layer comprises: stacking a buffer oxide film and a nitride layer on the cell region, stacking a trench mask on the buffer oxide film and the nitride layer, etching the trench mask. Forming a trench region, and filling an oxide film in the formed trench region. 제5항에 있어서, 상기 컨트롤 게이트영역은 N형으로 도핑된 것을 특징으로 하는 트랜치 분리를 이용한 EPROM 셀의 제조방법.6. The method of claim 5, wherein the control gate region is doped with an N-type.
KR1019880007986A 1988-06-30 1988-06-30 EPROM cell and its manufacturing method using trench isolation Expired - Fee Related KR970000652B1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1019880007986A KR970000652B1 (en) 1988-06-30 1988-06-30 EPROM cell and its manufacturing method using trench isolation
NL8901545A NL194183C (en) 1988-06-30 1989-06-20 EPROM cell with slot insulation, and method for its manufacture.
DE3920451A DE3920451C2 (en) 1988-06-30 1989-06-22 EPROM cell structure with trench isolation and method of making the same
FR8908469A FR2633777B1 (en) 1988-06-30 1989-06-26 EPROM CELL USING TRENCH ISOLATION AND MANUFACTURING METHOD THEREOF
JP1166474A JPH02119185A (en) 1988-06-30 1989-06-28 EPROM cell
US07/804,478 US5223731A (en) 1988-06-30 1991-12-09 EPROM cell using trench isolation to provide leak current immunity
US08/051,621 US5296397A (en) 1988-06-30 1993-04-22 Method for manufacturing an EPROM cell

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880007986A KR970000652B1 (en) 1988-06-30 1988-06-30 EPROM cell and its manufacturing method using trench isolation

Publications (2)

Publication Number Publication Date
KR900001023A KR900001023A (en) 1990-01-31
KR970000652B1 true KR970000652B1 (en) 1997-01-16

Family

ID=19275680

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880007986A Expired - Fee Related KR970000652B1 (en) 1988-06-30 1988-06-30 EPROM cell and its manufacturing method using trench isolation

Country Status (5)

Country Link
JP (1) JPH02119185A (en)
KR (1) KR970000652B1 (en)
DE (1) DE3920451C2 (en)
FR (1) FR2633777B1 (en)
NL (1) NL194183C (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9937770B2 (en) 2015-05-26 2018-04-10 Hyundai Motor Company Method for controlling air flow for vehicle

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE68916335T2 (en) * 1988-08-08 1995-01-05 Nat Semiconductor Corp Electrically erasable and programmable read-only bipolar field effect memory cell and method for its production.
JP3083547B2 (en) 1990-07-12 2000-09-04 株式会社日立製作所 Semiconductor integrated circuit device
DE4200620C2 (en) * 1992-01-13 1994-10-06 Eurosil Electronic Gmbh Floating gate EEPROM cell with sandwich coupling capacitance
KR100790044B1 (en) * 2006-03-09 2008-01-02 엘지전자 주식회사 Chiller of electric hob
KR100701179B1 (en) * 2006-03-24 2007-03-28 주식회사 대우일렉트로닉스 Microwave Convection Motor Cooling System

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3472604D1 (en) * 1983-10-11 1988-08-11 American Telephone & Telegraph Semiconductor integrated circuits containing complementary metal oxide semiconductor devices
JPS60260147A (en) * 1984-06-06 1985-12-23 Fujitsu Ltd Semiconductor device
US4698900A (en) * 1986-03-27 1987-10-13 Texas Instruments Incorporated Method of making a non-volatile memory having dielectric filled trenches

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9937770B2 (en) 2015-05-26 2018-04-10 Hyundai Motor Company Method for controlling air flow for vehicle

Also Published As

Publication number Publication date
NL194183C (en) 2001-08-03
KR900001023A (en) 1990-01-31
NL194183B (en) 2001-04-02
DE3920451A1 (en) 1990-01-04
NL8901545A (en) 1990-01-16
FR2633777B1 (en) 1993-12-31
DE3920451C2 (en) 1993-12-02
FR2633777A1 (en) 1990-01-05
JPH02119185A (en) 1990-05-07

Similar Documents

Publication Publication Date Title
US5173436A (en) Method of manufacturing an EEPROM with trench-isolated bitlines
US5231299A (en) Structure and fabrication method for EEPROM memory cell with selective channel implants
KR940006094B1 (en) Nonvolatile Semiconductor Memory and Manufacturing Method Thereof
US5019879A (en) Electrically-flash-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area
US5411905A (en) Method of making trench EEPROM structure on SOI with dual channels
US6479859B2 (en) Split gate flash memory with multiple self-alignments
US4794565A (en) Electrically programmable memory device employing source side injection
US5284784A (en) Buried bit-line source-side injection flash memory cell
KR100274491B1 (en) Spacer Flash Cell Process
US4833514A (en) Planar FAMOS transistor with sealed floating gate and DCS+N2 O oxide
US6017795A (en) Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash
US5907172A (en) Split-gate flash memory cell structure
US5923063A (en) Double density V nonvolatile memory cell
US5885871A (en) Method of making EEPROM cell structure
KR0144421B1 (en) Manufacturing method of fresh E.P.Rom
US5051795A (en) EEPROM with trench-isolated bitlines
US5057886A (en) Non-volatile memory with improved coupling between gates
US5194929A (en) Nonvolatile semiconductor memory and a memory of manufacturing the same
KR100262830B1 (en) Manufactruing method of semiconductor device
US6573142B1 (en) Method to fabricate self-aligned source and drain in split gate flash
KR20050007373A (en) Ultra small thin windows in floating gate transistors defined by lost nitride spacers
KR970000652B1 (en) EPROM cell and its manufacturing method using trench isolation
KR100585097B1 (en) Ypyrom element and its manufacturing method
US5296397A (en) Method for manufacturing an EPROM cell
US5032533A (en) Method of making a nonvolatile memory cell with field-plate switch

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

G160 Decision to publish patent application
R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1605 Publication of application before grant of patent

St.27 status event code: A-2-2-Q10-Q13-nap-PG1605

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 12

FPAY Annual fee payment

Payment date: 20090102

Year of fee payment: 13

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 13

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20100117

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20100117

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000