KR970010689B1 - Thin film transistor semiconductor device - Google Patents
Thin film transistor semiconductor device Download PDFInfo
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- KR970010689B1 KR970010689B1 KR1019930031519A KR930031519A KR970010689B1 KR 970010689 B1 KR970010689 B1 KR 970010689B1 KR 1019930031519 A KR1019930031519 A KR 1019930031519A KR 930031519 A KR930031519 A KR 930031519A KR 970010689 B1 KR970010689 B1 KR 970010689B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
- H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
- H10D30/6732—Bottom-gate only TFTs
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Abstract
내용없음No content
Description
제1도는 종래의 박막트랜지스터 단면구조도,1 is a cross-sectional structure of a conventional thin film transistor,
제2도는 본 발명의 일실시예에 의한 박막트랜지스터 단면구조도,2 is a cross-sectional structure of a thin film transistor according to an embodiment of the present invention,
제3도는 본 발명의 일실시예에 의한 박막트랜지스터 제조방법을 도시한 공정순서도,3 is a process flowchart showing a thin film transistor manufacturing method according to an embodiment of the present invention,
제4도는 본 발명의 다른 실시예에 의한 박막트랜지스터 단면구조도.4 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 절연기판 2 : 게이트전극1 Insulation substrate 2 Gate electrode
3 : 게이트절연막 4 : 비정질실리콘 활성층3: gate insulating film 4: amorphous silicon active layer
5 : 채널보호층 6 : 도핑된 비정질실리콘층5: channel protective layer 6: doped amorphous silicon layer
7 : 소오스전극 및 드레인전극 8 : 절연층7 source electrode and drain electrode 8 insulating layer
본 발명은 액정표시소자용 박막트랜지스터에 관한 것으로, 특히 광조사시 박막 트랜지스터의 누설전류를 줄일 수 있도록 한 박막트랜지스터구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors for liquid crystal display devices, and more particularly, to a thin film transistor structure capable of reducing leakage current of thin film transistors during light irradiation.
종래의 액정표시소자용 박막트랜지스터는 제1도에 도시된 바와 같이 유리기판(l)상에 게이트전극(2)이 형성되고, 그 전면에 게이트절연막(3)과 비정질실리콘(a-Si : H)으로 된 활성층(4), 비정질 나이트라이드(a-SiN : H)로 된 채널보호층(5), 오믹 접촉을 위해 인(P) 도핑된 비정질 실리콘층(6), 소오스 및 드레인극(7)이 순차적으로 형성된 구조로 되어 있다.In the conventional thin film transistor for liquid crystal display device, as shown in FIG. 1, the gate electrode 2 is formed on the glass substrate 1, and the gate insulating film 3 and the amorphous silicon (a-Si: H) are formed on the entire surface thereof. ) Active layer (4), channel protective layer (5) of amorphous nitride (a-SiN: H), phosphorus (P) doped amorphous silicon layer (6) for ohmic contact, source and drain electrode (7) ) Is formed in sequence.
상술한 종래 기술에 있어서, 액정표시소자에서 스위치 역할을 하는 박막트랜지스터의 오프(off)시의 누설 전류는 액정표시소자 픽셀의 전압에 변동을 주게 되어 화질에 나쁜 영향을 미친다.In the above-described prior art, the leakage current at the time of turning off the thin film transistor serving as a switch in the liquid crystal display device changes the voltage of the pixel of the liquid crystal display device, which adversely affects the image quality.
특히, 백라이트(Back light) 조사시 비정질 실리콘으로 된 활성층의 소오스 및 드레인접합부근(제1도의 빗금친 부분)에 빛이 흡수되어 전자와 정공이 생성되어 누설전류가 커지게 되는 문제가 있다.In particular, when the backlight is irradiated with light, light is absorbed near the source and drain junctions (hatched portions of FIG. 1) of the active layer made of amorphous silicon to generate electrons and holes, thereby increasing leakage current.
본 발명은 상술한 문제를 해결하기 위한 것으로, 광조사시의 박막트랜지스터의 누설전류를 줄이는데 적합한 박막트랜지스터구조를 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a thin film transistor structure suitable for reducing leakage current of a thin film transistor during light irradiation.
상기 목적을 달성하기 위한 본 발명의 박막트랜지스터는 절연기판(1)상부에 형성된 게이트전극(2)과, 상기 게이트전극(2)이 형성된 절연기판(1) 전면에 형성된 게이트절연막(3), 상기 게이트절연막(3) 상부에 형성된 채널보호층(5), 상기 채널보호층(5) 하부에만 한정되는 형성된 비정질실리콘 활성층(4), 상기 채널보호층(5) 상부 양단부에서 상기 게이트절연막(3) 상부에 걸쳐 형성된 오믹접촉용의 도핑된 반도체층(6), 및 상기 도핑된 반도체층(6) 상부에 형성된 소오스전극 및 드레인전극(7)을 포함하여 구성된 것을 특징으로 한다.The thin film transistor of the present invention for achieving the above object is a gate electrode (2) formed on the insulating substrate 1, the gate insulating film (3) formed on the entire surface of the insulating substrate (1) formed with the gate electrode (2), A channel protection layer 5 formed on the gate insulating film 3, an amorphous silicon active layer 4 defined only below the channel protection layer 5, and the gate insulating film 3 at both ends of the channel protection layer 5. And a doped semiconductor layer 6 for ohmic contact formed over the top, and a source electrode and a drain electrode 7 formed on the doped semiconductor layer 6.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
본 발명은 종래의 박막트랜지스터와는 달리 소오스 및 드레인접합부분의 비정질 실리콘 활성층을 채널 부분과 다른 특성을 갖게 함으로서 오프시 빛에 의한 누설 전류를 줄이도록 한 것이다.According to the present invention, unlike the conventional thin film transistor, the amorphous silicon active layer of the source and drain junction portions has different characteristics from those of the channel portion so as to reduce leakage current due to light during off.
트랜지스터의 게이트전극에 음의 전압이 인가되면 비정질실리콘 활성층에는 정공이 축적되지만 소오스 및 드레인전극에 접촉되어 있는 인(P) 도핑된 비정질실리콘에 의해 차단되어 매우 적은 전류가 흐르게 된다. 이때, 소오스 및 드레인접합부분에 빛이 조사되면 전자와 정공이 생성되어 전류가 커지게 된다. 이 전류는 빛에 의해 생성되는 전자-정공의 갯수와 이들의 평균 생존시간의 곱에 비례하게 된다.When a negative voltage is applied to the gate electrode of the transistor, holes are accumulated in the amorphous silicon active layer, but are blocked by phosphorus (P) doped amorphous silicon in contact with the source and drain electrodes so that very little current flows. At this time, when light is irradiated to the source and drain junctions, electrons and holes are generated to increase the current. This current is proportional to the product of the number of electron-holes generated by light and their average survival time.
이와 같이 트랜지스터의 광조사시 누설전류는 소오스 및 드레인접합부근에서 광전기 전도성과 밀접한 관련이 있는 바, 본 발명은 이를 이용하여 광전기 전도성이 작은 새로운 접합층을 포함시켜 누설전류를 감소시키도록 한 것이다.As described above, the leakage current during light irradiation of the transistor is closely related to the photoelectric conductivity near the source and drain junctions. The present invention uses the same to reduce the leakage current by including a new bonding layer having a low photoelectric conductivity.
제2도에 본 발명에 의한 박막트랜지스터 단면구조를 도시하였다.2 shows a cross-sectional structure of a thin film transistor according to the present invention.
본 발명의 박막트랜지스터는 절연기판(1) 상부에 형성된 게이트전극(2)과 상기 게이트전극(2) 상부에 형성된 게이트절연막(3), 상기 게이트절연막(3)상에 형성된 비정질실리콘 활성층(4), 상기 비정질실리콘층(4)상에 형성된 채널보호층(5), 상기 채널보호층(5) 상부 양단부에서 상기 게이트절연막(3) 상부에 걸쳐 형성된 오믹접촉용의 도핑된 반도체층(6) 그리고 상기 도핑된 반도체층(6) 상부에 형성된 소오스 전극 및 드레인전극(7)으로 구성된다.The thin film transistor of the present invention includes a gate electrode 2 formed on the insulating substrate 1, a gate insulating film 3 formed on the gate electrode 2, and an amorphous silicon active layer 4 formed on the gate insulating film 3. A channel protection layer 5 formed on the amorphous silicon layer 4, a doped semiconductor layer 6 for ohmic contact formed over the gate insulating layer 3 at both ends of the channel protection layer 5, and And a source electrode and a drain electrode 7 formed on the doped semiconductor layer 6.
상기 본 발명의 박막트랜지스터에 있어서, 상기 도핑된 반도체층(6)과 소오스 전극 및 드레인전극(7) 사이에 접합층(8)을 형성함으로써 광전기 전도성을 감소시키는 것도 가능하다.In the thin film transistor of the present invention, it is also possible to reduce the photoelectric conductivity by forming the bonding layer 8 between the doped semiconductor layer 6 and the source electrode and the drain electrode 7.
제3도를 참조하여 상기한 본 발명의 박막트랜지스터 제조방법을 설명하면 다음과 같다.Referring to Figure 3 described above the thin film transistor manufacturing method of the present invention as follows.
먼저, 제3도(a)에 도시된 바와 같이 유리기판(1)상에 도전층을 형성한후 패터닝하여 게이트전극(2)을 형성한 다음, 제3도(b)에 도시된 바와 같이 상기 게이트전극(2)이 형성된 유리기판(1) 전면에 게이트절연막(3), 비정질실리콘 활성층(4), 채널보호층(5)을 차례로 형성한다.First, as shown in FIG. 3A, a conductive layer is formed on the glass substrate 1, and then patterned to form a gate electrode 2. Then, as shown in FIG. A gate insulating film 3, an amorphous silicon active layer 4, and a channel protective layer 5 are sequentially formed on the entire glass substrate 1 on which the gate electrode 2 is formed.
이어서 제3도(c)에 도시된 바와 같이 상기 채널보호층(5) 및 비정질실리콘 활성층(4)을 선택적으로 식각하여 채널영역이외의 비정질실리콘 활성층(4)을 제거한 후, 제3도(d)에 도시된 바와 같이 결과물 전면에 광전기 전도성을 줄이기 위한 접합층(8)을 형성한 다음 이위에 오믹접촉을 위해 인(P)으로 도핑된 비정질실리콘층(6)을 형성한 후 상기 도핑된 비정질실리콘층(6) 및 접합층(8)을 선택적으로 식각하여 상기 채널보호층(5) 상부 양단부에서 상기 게이트절연막(3) 상부에 걸치는 영역에만 남도록 한다.Subsequently, as shown in FIG. 3 (c), the channel protective layer 5 and the amorphous silicon active layer 4 are selectively etched to remove the amorphous silicon active layer 4 other than the channel region. As shown in Fig. 6), a junction layer 8 is formed on the entire surface of the resultant, and then an amorphous silicon layer 6 doped with phosphorus (P) for ohmic contact is formed thereon. The silicon layer 6 and the bonding layer 8 are selectively etched so as to remain only in an area over the gate insulating layer 3 at both ends of the upper portion of the channel protection layer 5.
상기 접합층(8)은 빛의 흡수계수를 줄이기 위해 밴드갭이 큰 비정질실리콘을 증착하여 형성하는 것이 바람직하다.The bonding layer 8 is preferably formed by depositing amorphous silicon having a large band gap in order to reduce the absorption coefficient of light.
통상 비정질실리콘의 밴드갭은 ∼1.7eV 정도이나, 이는 증착시의 조건들(온도, 반응기압력, 수소가스농도등)을 바꿈으로써 조절할 수 있다.Typically, the amorphous silicon has a bandgap of about 1.7 eV, which can be controlled by changing the deposition conditions (temperature, reactor pressure, hydrogen gas concentration, etc.).
상기와 같이 접합층의 밴드갭을 크게 함으로써 빛이 조사되더라도 흡수되는 양은 작아져 전지-정공의 발생이 줄어들게 되므로 누설전류가 감소하게 된다.By increasing the band gap of the bonding layer as described above, even if light is irradiated, the amount of absorption is reduced and the generation of battery-holes is reduced, thereby reducing leakage current.
상기 접합층(8)을 비정질실리콘합금으로 형성할 수도 있고, 비정질실리콘-카본합금으로 형성하는 것도 가능한데, 카본의 양에 따라 밴드갭이 ∼1.9eV 이상의 큰 값을 가진다. 이때, 트랜지스터 온(on) 상태에서의 접합저항을 줄이기 위해 상기 비정질실리콘-카본에 인(P)을 도핑명하는테 도핑은 1∼1000ppm 정도의 균일한 도핑이나 델타도핑기법을 사용하여 행한다.The bonding layer 8 may be formed of an amorphous silicon alloy or an amorphous silicon-carbon alloy, and the band gap has a large value of ˜1.9 eV or more depending on the amount of carbon. At this time, in order to reduce the junction resistance in the transistor on state, the doping of phosphorus (P) into the amorphous silicon-carbon is performed using a uniform doping or delta doping technique of about 1 to 1000 ppm.
다음에 제3도(e)에 도시된 바와 같이 상기 결과물 전면에 금속을 증착한 후, 이를 패터닝하여 상기 도핑된 비정질실리콘층(6) 상부에 소오스전극 및 드레인전극(7)을 형성함으로써 박막트랜지스터 제조를 완료한다.Next, as shown in FIG. 3E, a metal is deposited on the entire surface of the resultant, and then patterned to form a source electrode and a drain electrode 7 on the doped amorphous silicon layer 6. Complete the manufacture.
한편, 본 발명의 박막트랜지스터 제조에 있어서, 상기 접합층을 형성하지 않는 경우도 광조사시의 누설 전류를 줄일 수 있다.On the other hand, in the manufacture of the thin film transistor of the present invention, even when the bonding layer is not formed, the leakage current during light irradiation can be reduced.
즉, 제4도에 도시된 바와 같이 비정질실리콘 활성층(4)을 채널보호층(5) 하부에만 국한되도록 형성하고, 오믹접촉용의 도핑된 비정질실리콘층(6)을 게이트절연막(3)과 바로 접촉되게 형성한다.That is, as shown in FIG. 4, the amorphous silicon active layer 4 is formed so as to be limited to the lower portion of the channel protective layer 5, and the doped amorphous silicon layer 6 for ohmic contact is directly formed with the gate insulating film 3. Form contact.
이 경우, 소오스 및 드레인전극(7) 하부에 비정질실리콘으로 된 접합층이 존재하지 않으므로 광조사시 전자-정공의 생성이 억제된다. 따라서 이온도핑을 한 경우와 같이 광조사시의 누설전류를 줄일 수 있다.In this case, since there is no bonding layer made of amorphous silicon under the source and drain electrodes 7, generation of electron-holes is suppressed during light irradiation. Therefore, leakage current during light irradiation can be reduced as in the case of ion doping.
상기 접합층(8)이 존재하지 않는 박막트랜지스터 제조방법은 제3도의 공정에서 접합층(8)을 형성하는 공정을 생략하고 나머지 공정을 동일하게 진행하는 것으로 그 설명은 생략한다.In the method of manufacturing a thin film transistor in which the bonding layer 8 does not exist, the process of forming the bonding layer 8 in the process of FIG. 3 is omitted, and the description thereof is omitted.
이상 상술한 바와 같이 본 발명에 의하면, 밴드갭이 커 광흡수계수가 작은 비정질실리콘으로 접합층을 형성함으로서 박막트랜지스터 오프시의 광전기 전류에 의한 누설전류를 줄일 수 있게 된다.As described above, according to the present invention, by forming a bonding layer made of amorphous silicon having a large band gap and a small light absorption coefficient, it is possible to reduce the leakage current due to the photoelectric current when the thin film transistor is turned off.
따라서 박막트랜지스터 액정표시장치에 있어서의 트랜지스터의 누설전류를 감소시켜 화질의 향상을 피할 수 있다.Therefore, the leakage current of the transistor in the thin film transistor liquid crystal display device can be reduced to improve the image quality.
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