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KR970029875A - Confirmation method of erasing flash memory cell and its confirmation circuit - Google Patents

Confirmation method of erasing flash memory cell and its confirmation circuit Download PDF

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Publication number
KR970029875A
KR970029875A KR1019950039315A KR19950039315A KR970029875A KR 970029875 A KR970029875 A KR 970029875A KR 1019950039315 A KR1019950039315 A KR 1019950039315A KR 19950039315 A KR19950039315 A KR 19950039315A KR 970029875 A KR970029875 A KR 970029875A
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cell block
circuit
erase
block
cell
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KR0182867B1 (en
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권규완
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김주용
현대전자산업 주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

본 발명은 플래쉬 메모리 셀의 소거 확인방법 및 그 확인회로에 관한 것으로서, 세어레이를 다수의 셀블럭으로 나누어서 소거동작을 시행할 때, 소거동작을 하는 현재의 셀블럭에서 불량셀이 발생되더라도 불량셀의 정보를 저장하고 그 다음블럭의 소거동작이 계속 진행되도록 하며 마지막 블록까지 소거동작이 끝난후에 최종적으로 상기 불량셀의 정보를 별도로 발생 시키도록 하므로써, 테스트 시간을 줄일 수 있고, 시스템에서 데이터 플링의 방법으로 칩의 동작을 체크할 때 발생되는 오류를 방지할 수 있도록 한 플래쉬 메모리 셀의 소거 확인방법 및 그 확인회로에 관한 것이다.The present invention relates to an erase confirmation method and a confirmation circuit for a flash memory cell. When an erase operation is performed by dividing a series into a plurality of cell blocks, a defective cell is generated even if a defective cell is generated in the current cell block performing the erase operation. The test time can be reduced and the test time can be reduced by storing the information of the next block and continuing the erase operation of the next block, and finally generating the information of the defective cell separately after the erase operation is completed until the last block. The present invention relates to an erase confirmation method and a confirmation circuit of a flash memory cell that can prevent an error occurring when checking an operation of a chip.

Description

플래쉬 메모리셀의 소거 확인방법 및 그 확인회로Confirmation method of flash memory cell and its confirmation circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 플래쉬 메모리 셀의 소거 확인방법을 설명하기 위해 도시한 플로우 챠트도.1 is a flowchart illustrating an erase confirmation method of a flash memory cell according to the present invention.

제2도는 본 발명에 따른 플래쉬 메모리 셀의 소거 확인회로의 블럭도.2 is a block diagram of an erase confirmation circuit of a flash memory cell according to the present invention.

제3도는 제2도의 불량 셀블럭 감출회로의 상세 회로도.3 is a detailed circuit diagram of the defective cell block detecting circuit of FIG.

제4도는 제3도의 래치회로의 상세 회로도.4 is a detailed circuit diagram of the latch circuit of FIG.

Claims (10)

플래쉬 메모리 셀의 소거 확인방법에 있어서, 칩내부의 최초의 셀블럭이 선택되어 셀 블록의 소거상태가 정상적으로 소거 되었는지를 확인하는 단계와, 셀 블록의 소거상태가 정상적인 소거상태로 되지 않았으면 정상적으로 소거된지 않은 불량난 셀 블록의 데이터를 저장한 후 칩내부에 사전에 설정된 최종 셀 블록과 동일함 여부를 확인하는 단계와, 셀 블록의 소거상태가 정상적인 소거상태로 되었으면 칩내부에 사전에 설정된 최종셀 블록과 동일함 여부를 확인하는 단계와, 칩 내부에 사전에 설정된 최종 셀블럭과 동일하지 않을 경우에는 셀 블록을 증가시켜 상기 소거확인 단계로 복귀하여 상기 셀 블록의 소거 확인 동작을 반복 시행하는 단계와, 칩 내부에 사전에 설정된 최종 셀블럭과 동일한 경우에는 다수의 셀블럭중 불량인 셀블럭의 데이터가 저장되어 있는지를 확인하는 단계와, 불량인 셀블럭의 데이터가 저장되어 있으면 셀 블록이 불량임을 판정하고 소거확인동작을 종료하는 단계와, 불량인 셀블럭의 데이터가 저장되어 있지 않으면 셀 블록이 정상임을 판정하고소거 확인동작을 종료하는 단계로 이루어지는 것을 특징으로 하는 플래쉬 메모리 셀의 소거 확인방법.A method of confirming erasure of a flash memory cell, the method comprising: checking whether an erased state of a cell block is normally erased by selecting the first cell block in a chip; and erasing normally if the erased state of the cell block does not become a normal erased state. Storing the data of the unsuccessful cell block and confirming whether it is the same as the last cell block preset in the chip, or if the erased state of the cell block is in the normal erase state, the last cell preset in the chip Checking whether or not it is the same as a block; and if it is not the same as the last cell block preset in the chip, increasing the cell block to return to the erase check step and repeatedly performing the erase check operation of the cell block. If the same as the last cell block preset in the chip, the data of the cell block that is bad among the plurality of cell blocks Determining whether the cell block is stored, determining that the cell block is defective if data of the defective cell block is stored, terminating the erase check operation, and if the data of the defective cell block is not stored, And determining to be normal and ending the erasing confirmation operation. 플래시 메모리 셀의 소거 확인회로에 있어서, 셀블럭 소거 확인신호 및 다수의 제어신호에 따라 소거상태가 불량인 셀블럭을 검출하기 위한 불량 셀블럭 검출회로와, 상기 불량 셀블럭 검출회로의 출력신호에 따라 셀블럭에 대한 동작모드를 설정하기 위한 상태 카운터 콘트롤회로와, 상기 상태 카운터 콘트롤회로의 출력신호에따라 셀블럭을 선택하여 상기 선택된 셀블럭의 데이터를 상기 불량 셀블럭 검출회로로 공급하기 위한 셀블럭카운터 콘트롤회로와, 상기 셀블럭 카운터 콘트롤회로 및 상기 불량 셀블럭 검출회로의 출력신호에 따라 셀블럭의 상태를 저장하기 위한 콤맨드 래치회로와, 상기 콤맨드 래치외로의 데이터를 출력 시키기 위한 데이터 플링회로로 구성되는 것을 특징으로 하는 플래쉬 메모리 셀의 소거 확인회로.An erase confirmation circuit of a flash memory cell, comprising: a defective cell block detection circuit for detecting a cell block in which an erase state is defective according to a cell block erase confirmation signal and a plurality of control signals, and an output signal of the defective cell block detection circuit. And a cell for supplying the data of the selected cell block to the defective cell block detection circuit by selecting a cell block according to an output signal of the state counter control circuit and a state counter control circuit for setting an operation mode for the cell block. A block latch control circuit, a command latch circuit for storing a state of a cell block according to output signals of the cell block counter control circuit and the bad cell block detection circuit, and data for outputting data outside the command latch An erase confirmation circuit of a flash memory cell, comprising: a fling circuit. 제2항에 있어서, 상기 불량 셀블럭 검출회로는 소거 확인신호, 소거확인 최대루핑신호 및 데이터 비교신호의 입력에 따라 불량 셀블럭 최대루핑신호를 래치시키기 위한 래치회로와, 상기 소거 확인신호, 소거확인 최대루핑신호 및 데이타 비교신호를 각각 입력으로 하며, 셀블럭의 소거 확인동작시 불량 셀블럭이 발생될 때 불량 셀블럭 신호를 발생시키도록 하는 래치회로와, 상기 래치회로의 데이터를 다음 셀블럭의 소거 확인동작시리셋시키도록 하는 다수의 논리게이트 소자와, 상기 래치회로의 데이터를 입력으로 하며, 블록앤드신호에 따라 최종 불량 셀블럭 최대루핑신호를 출력하도록 하는 디-플립플롭회로로 구성되는 것을 특징으로 하는 플래쉬 메모리 셀의 소거 확인회로.The method of claim 2, wherein the bad cell block detection circuit comprises: a latch circuit for latching a bad cell block maximum looping signal according to an input of an erase confirmation signal, an erase confirmation maximum looping signal, and a data comparison signal; A latch circuit for inputting a confirming maximum looping signal and a data comparison signal, respectively, to generate a defective cell block signal when a defective cell block is generated during an erase confirmation operation of the cell block, and the data of the latch circuit to the next cell block. And a de-flip-flop circuit for inputting the data of the latch circuit and outputting the final defective cell block maximum looping signal according to the block and signal. And an erase confirmation circuit of the flash memory cell. 제2항에 있어서, 상기 상태 카운터 콘트롤회로는 셀블럭이 불량일 경우 상태 카운터를 리셋 시켜서 다음 블럭의 소거 확인동작이 진행될 수 있도록 하기 위해 소거 바이어스 상태가 되도록 구성되는 것을 특징으로 하는 플래쉬 메모리 셀의 소거 확인회로.The flash memory cell of claim 2, wherein the state counter control circuit is configured to be in an erase bias state to reset the state counter so that an erase check operation of a next block can be performed when the cell block is defective. Erasure confirmation circuit. 제2항에 있어서, 상기 상태 카운터 콘트롤회로는 소거 바이어스 신호 및 기준클럭신호에 의해 다음블럭으로 소거 바이어스가 가해질수 있도록 블록클럭신호가 출력되도록 구성되는 것을 특징으로 하는 플래쉬 메모리 셀의 소거 확인회로.3. The erase confirmation circuit of claim 2, wherein the state counter control circuit is configured to output a block clock signal such that an erase bias is applied to the next block by an erase bias signal and a reference clock signal. 제2항에 있어서, 상기 셀블럭 카운터 콘트롤회로는 블록클럭신호의 입력에 따라 최종 셀블럭 확인이 종료되었음을 알려주도록 하는 블록앤드신호가 출력되도록 구성되는 것을 특징으로 하는 플래쉬 메모리 셀의 소거 확인회로.3. The erase check circuit of claim 2, wherein the cell block counter control circuit is configured to output a block and signal for informing that the final cell block check is completed according to the input of the block clock signal. 제2항에 있어서, 상기 콤맨드 래치회로는 셀블럭앤드신호의 페일링 엣지에서 리셋되며 최종 불량 셀블럭 최대 루핑신호의 입력신호에 의해 리셋 되지않는 래치회로로 구성되는 것을 특징으로 하는 플래쉬 메모리 셀의 소거 확인회로.3. The flash memory cell of claim 2, wherein the command latch circuit is configured as a latch circuit that is reset at a failing edge of a cell block and signal and is not reset by an input signal of a final bad cell block maximum looping signal. Erase confirmation circuit. 제2항에 있어서, 상기 콤맨드 래치회로는 셀블럭의 소거 확인동작중이거나 확인동작이 종료되었더라도 어느 한 셀블럭에서 불량 셀블럭이 검출되면 상기 콤맨드 래치회로의 출력이 로우상태가 되도록 구성되는 것을 특징으로 하는 플래쉬 메모리 셀의 소거 확인회로.The command latch circuit of claim 2, wherein the command latch circuit is configured such that an output of the command latch circuit is set to a low state when a bad cell block is detected in any one of the cell blocks even when an erase check operation or a check operation is terminated. And an erase confirmation circuit of the flash memory cell. 제2항에 있어서, 상기 콤맨드 래치회로는 셀블럭의 소거 확인동작시 칩소거가 정상일 경우 상기 콤맨드 래치회로의 출력이 하이상태가 되도록 구성되는 것을 특징으로 하는 플래쉬 메모리 셀의 소거 확인회로.The erase check circuit of claim 2, wherein the command latch circuit is configured such that an output of the command latch circuit is in a high state when chip erasing is normal during an erase check operation of a cell block. 제2항에 있어서, 상기 데이터 플링회로는 출력인에이블 신호에 따라 상기 콤맨드래치회로의 출력데이타를 출력시키기 위한 다수의 논리게이트 소자로 구성되는 것을 특징으로 하는 플래쉬 메모리 셀의 소거 확인회로.3. The erase confirmation circuit of claim 2, wherein the data flickering circuit comprises a plurality of logic gate elements for outputting output data of the command latch circuit according to an output enable signal.
KR1019950039315A 1995-11-02 1995-11-02 Flash memory cell Expired - Fee Related KR0182867B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7298654B2 (en) 2004-12-01 2007-11-20 Samsung Electronics Co., Ltd. Non-volatile memory device and associated method of erasure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7298654B2 (en) 2004-12-01 2007-11-20 Samsung Electronics Co., Ltd. Non-volatile memory device and associated method of erasure

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